| 1 |
13 |
dinesha |
irun: 11.10-s021: (c) Copyright 1995-2012 Cadence Design Systems, Inc.
|
| 2 |
|
|
TOOL: irun 11.10-s021: Started on Aug 08, 2014 at 12:26:32 IST
|
| 3 |
|
|
irun
|
| 4 |
|
|
fifo_tb.v
|
| 5 |
|
|
ram_dp_ar_aw.v
|
| 6 |
|
|
syn_fifo_assert.v
|
| 7 |
|
|
+incdir+../std_ovl/
|
| 8 |
|
|
-y ../std_ovl/
|
| 9 |
|
|
+notimingchecks
|
| 10 |
|
|
+nospecify
|
| 11 |
|
|
file: fifo_tb.v
|
| 12 |
|
|
module worklib.fifo_tb:v
|
| 13 |
|
|
errors: 0, warnings: 0
|
| 14 |
|
|
file: ram_dp_ar_aw.v
|
| 15 |
|
|
module worklib.ram_dp_ar_aw:v
|
| 16 |
|
|
errors: 0, warnings: 0
|
| 17 |
|
|
file: syn_fifo_assert.v
|
| 18 |
|
|
module worklib.assert_fifo_index:vlib
|
| 19 |
|
|
errors: 0, warnings: 0
|
| 20 |
|
|
module worklib.assert_always:vlib
|
| 21 |
|
|
errors: 0, warnings: 0
|
| 22 |
|
|
module worklib.assert_never:vlib
|
| 23 |
|
|
errors: 0, warnings: 0
|
| 24 |
|
|
module worklib.assert_increment:vlib
|
| 25 |
|
|
errors: 0, warnings: 0
|
| 26 |
|
|
module worklib.syn_fifo:v
|
| 27 |
|
|
errors: 0, warnings: 0
|
| 28 |
|
|
ncvlog: *W,LIBNOU: Library "../std_ovl/" given but not used.
|
| 29 |
|
|
Total errors/warnings found outside modules and primitives:
|
| 30 |
|
|
errors: 0, warnings: 1
|
| 31 |
|
|
Caching library 'worklib' ....... Done
|
| 32 |
|
|
Elaborating the design hierarchy:
|
| 33 |
|
|
Top level design units:
|
| 34 |
|
|
fifo_tb
|
| 35 |
|
|
Building instance overlay tables: .................... Done
|
| 36 |
|
|
Generating native compiled code:
|
| 37 |
|
|
worklib.assert_always:vlib <0x28e7f6e4>
|
| 38 |
|
|
streams: 12, words: 4811
|
| 39 |
|
|
worklib.assert_fifo_index:vlib <0x43df550e>
|
| 40 |
|
|
streams: 17, words: 6669
|
| 41 |
|
|
worklib.assert_increment:vlib <0x7377a130>
|
| 42 |
|
|
streams: 16, words: 5594
|
| 43 |
|
|
worklib.assert_never:vlib <0x4a4ba4b2>
|
| 44 |
|
|
streams: 12, words: 4811
|
| 45 |
|
|
worklib.fifo_tb:v <0x241a9e72>
|
| 46 |
|
|
streams: 7, words: 6217
|
| 47 |
|
|
worklib.ram_dp_ar_aw:v <0x6ed586d3>
|
| 48 |
|
|
streams: 9, words: 2573
|
| 49 |
|
|
worklib.syn_fifo:v <0x52fefc94>
|
| 50 |
|
|
streams: 13, words: 2833
|
| 51 |
|
|
Loading native compiled code: .................... Done
|
| 52 |
|
|
Building instance specific data structures.
|
| 53 |
|
|
Design hierarchy summary:
|
| 54 |
|
|
Instances Unique
|
| 55 |
|
|
Modules: 7 7
|
| 56 |
|
|
Resolved nets: 0 1
|
| 57 |
|
|
Registers: 67 67
|
| 58 |
|
|
Scalar wires: 27 -
|
| 59 |
|
|
Vectored wires: 8 -
|
| 60 |
|
|
Always blocks: 19 19
|
| 61 |
|
|
Initial blocks: 16 16
|
| 62 |
|
|
Cont. assignments: 6 11
|
| 63 |
|
|
Pseudo assignments: 9 9
|
| 64 |
|
|
Writing initial simulation snapshot: worklib.fifo_tb:v
|
| 65 |
|
|
Loading snapshot worklib.fifo_tb:v .................... Done
|
| 66 |
|
|
ncsim> source /tools/INCISIV111/tools/inca/files/ncsimrc
|
| 67 |
|
|
ncsim> run
|
| 68 |
|
|
OVL_NOTE: V2.5: ASSERT_FIFO_INDEX initialized @ fifo_tb.fifo.no_over_under_flow.ovl_init_msg_t Severity: 1, Message: my_module_err
|
| 69 |
|
|
OVL_NOTE: V2.5: ASSERT_ALWAYS initialized @ fifo_tb.fifo.no_full_write.ovl_init_msg_t Severity: 1, Message: fifo_full_write
|
| 70 |
|
|
OVL_NOTE: V2.5: ASSERT_NEVER initialized @ fifo_tb.fifo.no_empty_read.ovl_init_msg_t Severity: 1, Message: fifo_empty_read
|
| 71 |
|
|
OVL_NOTE: V2.5: ASSERT_INCREMENT initialized @ fifo_tb.fifo.write_count.ovl_init_msg_t Severity: 1, Message: Write_Pointer_Error
|
| 72 |
|
|
|
| 73 |
|
|
OVL_ERROR : ASSERT_INCREMENT : Write_Pointer_Error : test_expr contains X or Z : severity 1 : time 1 : fifo_tb.fifo.write_count.ovl_error_t
|
| 74 |
|
|
OVL_ERROR : ASSERT_INCREMENT : Write_Pointer_Error : test_expr contains X or Z : severity 1 : time 3 : fifo_tb.fifo.write_count.ovl_error_t
|
| 75 |
|
|
OVL_ERROR : ASSERT_INCREMENT : Write_Pointer_Error : test_expr contains X or Z : severity 1 : time 5 : fifo_tb.fifo.write_count.ovl_error_t
|
| 76 |
|
|
5 wr:0 wr_data:00 rd:0 rd_data:00
|
| 77 |
|
|
10 wr:1 wr_data:00 rd:0 rd_data:00
|
| 78 |
|
|
12 wr:1 wr_data:01 rd:0 rd_data:00
|
| 79 |
|
|
14 wr:1 wr_data:02 rd:0 rd_data:00
|
| 80 |
|
|
16 wr:1 wr_data:03 rd:0 rd_data:00
|
| 81 |
|
|
18 wr:1 wr_data:04 rd:0 rd_data:00
|
| 82 |
|
|
20 wr:1 wr_data:05 rd:0 rd_data:00
|
| 83 |
|
|
22 wr:1 wr_data:06 rd:0 rd_data:00
|
| 84 |
|
|
24 wr:1 wr_data:07 rd:0 rd_data:00
|
| 85 |
|
|
OVL_ERROR : ASSERT_ALWAYS : fifo_full_write : Test expression is FALSE : severity 1 : time 25 : fifo_tb.fifo.no_full_write.ovl_error_t
|
| 86 |
|
|
OVL_ERROR : ASSERT_FIFO_INDEX : my_module_err : Fifo overflow detected : severity 1 : time 25 : fifo_tb.fifo.no_over_under_flow.ovl_error_t
|
| 87 |
|
|
26 wr:1 wr_data:08 rd:0 rd_data:00
|
| 88 |
|
|
OVL_ERROR : ASSERT_FIFO_INDEX : my_module_err : Fifo overflow detected : severity 1 : time 27 : fifo_tb.fifo.no_over_under_flow.ovl_error_t
|
| 89 |
|
|
28 wr:1 wr_data:09 rd:0 rd_data:00
|
| 90 |
|
|
OVL_ERROR : ASSERT_FIFO_INDEX : my_module_err : Fifo overflow detected : severity 1 : time 29 : fifo_tb.fifo.no_over_under_flow.ovl_error_t
|
| 91 |
|
|
30 wr:0 wr_data:09 rd:0 rd_data:00
|
| 92 |
|
|
32 wr:0 wr_data:09 rd:1 rd_data:00
|
| 93 |
|
|
33 wr:0 wr_data:09 rd:1 rd_data:08
|
| 94 |
|
|
35 wr:0 wr_data:09 rd:1 rd_data:09
|
| 95 |
|
|
39 wr:0 wr_data:09 rd:1 rd_data:03
|
| 96 |
|
|
41 wr:0 wr_data:09 rd:1 rd_data:04
|
| 97 |
|
|
43 wr:0 wr_data:09 rd:1 rd_data:05
|
| 98 |
|
|
45 wr:0 wr_data:09 rd:1 rd_data:06
|
| 99 |
|
|
OVL_ERROR : ASSERT_FIFO_INDEX : my_module_err : Fifo underflow detected : severity 1 : time 47 : fifo_tb.fifo.no_over_under_flow.ovl_error_t
|
| 100 |
|
|
47 wr:0 wr_data:09 rd:1 rd_data:07
|
| 101 |
|
|
OVL_ERROR : ASSERT_NEVER : fifo_empty_read : Test expression is not FALSE : severity 1 : time 49 : fifo_tb.fifo.no_empty_read.ovl_error_t
|
| 102 |
|
|
OVL_ERROR : ASSERT_FIFO_INDEX : my_module_err : Fifo underflow detected : severity 1 : time 49 : fifo_tb.fifo.no_over_under_flow.ovl_error_t
|
| 103 |
|
|
49 wr:0 wr_data:09 rd:1 rd_data:08
|
| 104 |
|
|
OVL_ERROR : ASSERT_NEVER : fifo_empty_read : Test expression is not FALSE : severity 1 : time 51 : fifo_tb.fifo.no_empty_read.ovl_error_t
|
| 105 |
|
|
OVL_ERROR : ASSERT_FIFO_INDEX : my_module_err : Fifo underflow detected : severity 1 : time 51 : fifo_tb.fifo.no_over_under_flow.ovl_error_t
|
| 106 |
|
|
51 wr:0 wr_data:09 rd:1 rd_data:09
|
| 107 |
|
|
52 wr:0 wr_data:09 rd:0 rd_data:09
|
| 108 |
|
|
Simulation complete via $finish(1) at time 152 NS + 0
|
| 109 |
|
|
./fifo_tb.v:37 #100 $finish;
|
| 110 |
|
|
ncsim> exit
|
| 111 |
|
|
TOOL: irun 11.10-s021: Exiting on Aug 08, 2014 at 12:26:35 IST (total: 00:00:03)
|
