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[/] [oms8051mini/] [trunk/] [example/] [systemverilog/] [assertion/] [test2/] [test.sv] - Blame information for rev 13

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1 13 dinesha
//+++++++++++++++++++++++++++++++++++++++++++++++++
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//   DUT With assertions
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//+++++++++++++++++++++++++++++++++++++++++++++++++
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module concurrent_assertion(
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  input wire clk,req,reset,
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  input wire gnt);
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//=================================================
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// Sequence Layer
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//=================================================
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sequence req_gnt_seq;
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  // (~req & gnt) and (~req & ~gnt) is Boolean Layer
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 (req & ~gnt) ##1 (~req & gnt) ##1 (~req & ~gnt) ;
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endsequence
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//=================================================
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// Property Specification Layer
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//=================================================
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property req_gnt_prop;
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  @ (posedge clk)
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    disable iff (reset)
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      req |-> req_gnt_seq;
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endproperty
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//=================================================
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// Assertion Directive Layer
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//=================================================
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req_gnt_assert : assert property (req_gnt_prop)
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                 else
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                 $display("@%0dns Assertion Failed", $time);
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endmodule
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//+++++++++++++++++++++++++++++++++++++++++++++++
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//   Testbench Code
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//+++++++++++++++++++++++++++++++++++++++++++++++
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module concurrent_assertion_tb();
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reg clk = 0;
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reg reset, req = 0;
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reg gnt;
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always #3 clk ++;
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initial begin
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  reset <= 1;
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  #20 reset <= 0;
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  repeat (100) @ (posedge clk);
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  // Make the assertion pass
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  @ (posedge clk) #1 req  <= 1;
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  @ (posedge clk) #1 req <= 0;
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  repeat (100) @ (posedge clk);
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  // Make the assertion fail
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  @ (posedge clk) #1 req  <= 1;
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  repeat (5) @ (posedge clk);
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  @ (posedge clk) #1 req <= 0;
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  req <= 0;
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  repeat (100) @ (posedge clk);
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  #10 $finish;
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end
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//=================================================
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// Actual DUT RTL
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//=================================================
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always @ (posedge clk)
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  gnt <= #1 req ;
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concurrent_assertion dut (clk,req,reset,gnt);
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// Dumping Waveforms
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initial begin //{
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    $shm_open("simvision.shm");
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    $shm_probe("AC");
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end //}
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endmodule

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