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[/] [oms8051mini/] [trunk/] [rtl/] [8051/] [oc8051_alu.v] - Blame information for rev 2

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1 2 dinesha
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// alu for 8051 Core                                            ////
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////                                                              ////
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//// This file is part of the 8051 cores project                  ////
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////  http://www.opencores.org/cores/oms8051mini/                 ////
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////                                                              ////
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//// Description                                                  ////
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//// Implementation of aritmetic unit  according to               ////
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//// 8051 IP core specification document. Uses divide.v and       ////
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//// multiply.v                                                   ////
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////                                                              ////
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//// To Do:                                                       ////
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////  pc signed add                                               ////
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////                                                              ////
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//// Author(s):                                                   ////
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////      - Simon Teran, simont@opencores.org                     ////
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////      - Dinesh Annayya, dinesha@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE. See the GNU Lesser General Public License for more  ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.18  2003/07/01 18:51:11  simont
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// x replaced with 0.
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//
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// Revision 1.17  2003/06/09 16:51:16  simont
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// fix bug in DA operation.
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//
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// Revision 1.16  2003/06/03 17:15:06  simont
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// sub_result output added.
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//
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// Revision 1.15  2003/05/07 12:31:53  simont
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// add wire sub_result, conect it to des_acc and des1.
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//
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// Revision 1.14  2003/05/05 15:46:36  simont
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// add aditional alu destination to solve critical path.
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//
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// Revision 1.13  2003/04/29 08:35:12  simont
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// fix bug in substraction.
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//
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// Revision 1.12  2003/04/25 17:15:51  simont
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// change branch instruction execution (reduse needed clock periods).
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//
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// Revision 1.11  2003/04/14 14:29:42  simont
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// fiz bug iv pcs operation.
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//
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// Revision 1.10  2003/01/13 14:14:40  simont
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// replace some modules
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//
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// Revision 1.9  2002/09/30 17:33:59  simont
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// prepared header
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//
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//
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`include "top_defines.v"
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module oc8051_alu (clk, rst, op_code, src1, src2, src3, srcCy, srcAc, bit_in,
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                  des1, des2, des_acc, desCy, desAc, desOv, sub_result);
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//
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// op_code      (in)  operation code [oc8051_decoder.alu_op -r]
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// src1         (in)  first operand [oc8051_alu_src1_sel.des]
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// src2         (in)  second operand [oc8051_alu_src2_sel.des]
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// src3         (in)  third operand [oc8051_alu_src3_sel.des]
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// srcCy        (in)  carry input [oc8051_cy_select.data_out]
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// srcAc        (in)  auxiliary carry input [oc8051_psw.data_out[6] ]
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// bit_in       (in)  bit input, used for logic operatins on bits [oc8051_ram_sel.bit_out]
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// des1         (out)
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// des2         (out)
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// desCy        (out) carry output [oc8051_ram_top.bit_data_in, oc8051_acc.bit_in, oc8051_b_register.bit_in, oc8051_psw.cy_in, oc8051_ports.bit_in]
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// desAc        (out) auxiliary carry output [oc8051_psw.ac_in]
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// desOv        (out) Overflow output [oc8051_psw.ov_in]
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//
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input        srcCy, srcAc, bit_in, clk, rst;
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input  [3:0] op_code;
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input  [7:0] src1, src2, src3;
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output       desCy, desAc, desOv;
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output [7:0] des1, des2, des_acc, sub_result;
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reg desCy, desAc, desOv;
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reg [7:0] des1, des2, des_acc;
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//
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//add
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//
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wire [4:0] add1, add2, add3, add4;
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wire [3:0] add5, add6, add7, add8;
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wire [1:0] add9, adda, addb, addc;
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//
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//sub
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//
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wire [4:0] sub1, sub2, sub3, sub4;
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wire [3:0] sub5, sub6, sub7, sub8;
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wire [1:0] sub9, suba, subb, subc;
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wire [7:0] sub_result;
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//
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//mul
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//
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  wire [7:0] mulsrc1, mulsrc2;
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  wire mulOv;
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  reg enable_mul;
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//
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//div
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//
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wire [7:0] divsrc1,divsrc2;
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wire divOv;
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reg enable_div;
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//
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//da
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//
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reg da_tmp, da_tmp1;
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//reg [8:0] da1;
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//
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// inc
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//
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wire [15:0] inc, dec;
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oc8051_multiply oc8051_mul1(.clk(clk), .rst(rst), .enable(enable_mul), .src1(src1), .src2(src2), .des1(mulsrc1), .des2(mulsrc2), .desOv(mulOv));
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oc8051_divide oc8051_div1(.clk(clk), .rst(rst), .enable(enable_div), .src1(src1), .src2(src2), .des1(divsrc1), .des2(divsrc2), .desOv(divOv));
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/* Add */
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assign add1 = {1'b0,src1[3:0]};
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assign add2 = {1'b0,src2[3:0]};
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assign add3 = {3'b000,srcCy};
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assign add4 = add1+add2+add3;
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assign add5 = {1'b0,src1[6:4]};
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assign add6 = {1'b0,src2[6:4]};
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assign add7 = {1'b0,1'b0,1'b0,add4[4]};
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assign add8 = add5+add6+add7;
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assign add9 = {1'b0,src1[7]};
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assign adda = {1'b0,src2[7]};
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assign addb = {1'b0,add8[3]};
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assign addc = add9+adda+addb;
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/* Sub */
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assign sub1 = {1'b1,src1[3:0]};
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assign sub2 = {1'b0,src2[3:0]};
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assign sub3 = {1'b0,1'b0,1'b0,srcCy};
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assign sub4 = sub1-sub2-sub3;
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186
assign sub5 = {1'b1,src1[6:4]};
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assign sub6 = {1'b0,src2[6:4]};
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assign sub7 = {1'b0,1'b0,1'b0, !sub4[4]};
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assign sub8 = sub5-sub6-sub7;
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191
assign sub9 = {1'b1,src1[7]};
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assign suba = {1'b0,src2[7]};
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assign subb = {1'b0,!sub8[3]};
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assign subc = sub9-suba-subb;
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196
assign sub_result = {subc[0],sub8[2:0],sub4[3:0]};
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198
/* inc */
199
assign inc = {src2, src1} + {15'h0, 1'b1};
200
assign dec = {src2, src1} - {15'h0, 1'b1};
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202
always @(op_code or src1 or src2 or srcCy or srcAc or bit_in or src3 or mulsrc1
203
      or mulsrc2 or mulOv or divsrc1 or divsrc2 or divOv or addc or add8 or add4
204
      or sub4 or sub8 or subc or da_tmp or inc or dec or sub_result)
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begin
206
 
207
  case (op_code) /* synopsys full_case parallel_case */
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//operation add
209
    `OC8051_ALU_ADD: begin
210
      des_acc = {addc[0],add8[2:0],add4[3:0]};
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      des1 = src1;
212
      des2 = src3+ {7'b0, addc[1]};
213
      desCy = addc[1];
214
      desAc = add4[4];
215
      desOv = addc[1] ^ add8[3];
216
 
217
      enable_mul = 1'b0;
218
      enable_div = 1'b0;
219
    end
220
//operation subtract
221
    `OC8051_ALU_SUB: begin
222
      des_acc = sub_result;
223
//      des1 = sub_result;
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      des1 = 8'h00;
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      des2 = 8'h00;
226
      desCy = !subc[1];
227
      desAc = !sub4[4];
228
      desOv = !subc[1] ^ !sub8[3];
229
 
230
      enable_mul = 1'b0;
231
      enable_div = 1'b0;
232
    end
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//operation multiply
234
    `OC8051_ALU_MUL: begin
235
      des_acc = mulsrc1;
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      des1 = src1;
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      des2 = mulsrc2;
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      desOv = mulOv;
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      desCy = 1'b0;
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      desAc = 1'b0;
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      enable_mul = 1'b1;
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      enable_div = 1'b0;
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    end
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//operation divide
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    `OC8051_ALU_DIV: begin
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      des_acc = divsrc1;
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      des1 = src1;
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      des2 = divsrc2;
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      desOv = divOv;
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      desAc = 1'b0;
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      desCy = 1'b0;
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      enable_mul = 1'b0;
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      enable_div = 1'b1;
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    end
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//operation decimal adjustment
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    `OC8051_ALU_DA: begin
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258
      if (srcAc==1'b1 | src1[3:0]>4'b1001) {da_tmp, des_acc[3:0]} = {1'b0, src1[3:0]}+ 5'b00110;
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      else {da_tmp, des_acc[3:0]} = {1'b0, src1[3:0]};
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      if (srcCy | da_tmp | src1[7:4]>4'b1001)
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        {da_tmp1, des_acc[7:4]} = {srcCy, src1[7:4]}+ 5'b00110 + {4'b0, da_tmp};
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      else {da_tmp1, des_acc[7:4]} = {srcCy, src1[7:4]} + {4'b0, da_tmp};
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      desCy = da_tmp | da_tmp1;
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      des1 = src1;
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      des2 = 8'h00;
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      desAc = 1'b0;
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      desOv = 1'b0;
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      enable_mul = 1'b0;
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      enable_div = 1'b0;
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    end
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//operation not
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// bit operation not
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    `OC8051_ALU_NOT: begin
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      des_acc = ~src1;
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      des1 = ~src1;
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      des2 = 8'h00;
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      desCy = !srcCy;
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      desAc = 1'b0;
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      desOv = 1'b0;
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      enable_mul = 1'b0;
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      enable_div = 1'b0;
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    end
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//operation and
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//bit operation and
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    `OC8051_ALU_AND: begin
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      des_acc = src1 & src2;
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      des1 = src1 & src2;
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      des2 = 8'h00;
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      desCy = srcCy & bit_in;
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      desAc = 1'b0;
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      desOv = 1'b0;
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      enable_mul = 1'b0;
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      enable_div = 1'b0;
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    end
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//operation xor
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// bit operation xor
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    `OC8051_ALU_XOR: begin
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      des_acc = src1 ^ src2;
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      des1 = src1 ^ src2;
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      des2 = 8'h00;
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      desCy = srcCy ^ bit_in;
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      desAc = 1'b0;
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      desOv = 1'b0;
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      enable_mul = 1'b0;
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      enable_div = 1'b0;
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    end
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//operation or
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// bit operation or
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    `OC8051_ALU_OR: begin
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      des_acc = src1 | src2;
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      des1 = src1 | src2;
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      des2 = 8'h00;
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      desCy = srcCy | bit_in;
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      desAc = 1'b0;
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      desOv = 1'b0;
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      enable_mul = 1'b0;
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      enable_div = 1'b0;
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    end
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//operation rotate left
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// bit operation cy= cy or (not ram)
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    `OC8051_ALU_RL: begin
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      des_acc = {src1[6:0], src1[7]};
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      des1 = src1 ;
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      des2 = 8'h00;
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      desCy = srcCy | !bit_in;
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      desAc = 1'b0;
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      desOv = 1'b0;
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      enable_mul = 1'b0;
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      enable_div = 1'b0;
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    end
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//operation rotate left with carry and swap nibbles
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    `OC8051_ALU_RLC: begin
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      des_acc = {src1[6:0], srcCy};
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      des1 = src1 ;
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      des2 = {src1[3:0], src1[7:4]};
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      desCy = src1[7];
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      desAc = 1'b0;
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      desOv = 1'b0;
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      enable_mul = 1'b0;
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      enable_div = 1'b0;
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    end
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//operation rotate right
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    `OC8051_ALU_RR: begin
346
      des_acc = {src1[0], src1[7:1]};
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      des1 = src1 ;
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      des2 = 8'h00;
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      desCy = srcCy & !bit_in;
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      desAc = 1'b0;
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      desOv = 1'b0;
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      enable_mul = 1'b0;
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      enable_div = 1'b0;
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    end
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//operation rotate right with carry
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    `OC8051_ALU_RRC: begin
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      des_acc = {srcCy, src1[7:1]};
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      des1 = src1 ;
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      des2 = 8'h00;
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      desCy = src1[0];
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      desAc = 1'b0;
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      desOv = 1'b0;
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      enable_mul = 1'b0;
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      enable_div = 1'b0;
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    end
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//operation pcs Add
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    `OC8051_ALU_INC: begin
368
      if (srcCy) begin
369
        des_acc = dec[7:0];
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        des1 = dec[7:0];
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        des2 = dec[15:8];
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      end else begin
373
        des_acc = inc[7:0];
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        des1 = inc[7:0];
375
        des2 = inc[15:8];
376
      end
377
      desCy = 1'b0;
378
      desAc = 1'b0;
379
      desOv = 1'b0;
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      enable_mul = 1'b0;
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      enable_div = 1'b0;
382
    end
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//operation exchange
384
//if carry = 0 exchange low order digit
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    `OC8051_ALU_XCH: begin
386
      if (srcCy)
387
      begin
388
        des_acc = src2;
389
        des1 = src2;
390
        des2 = src1;
391
      end else begin
392
        des_acc = {src1[7:4],src2[3:0]};
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        des1 = {src1[7:4],src2[3:0]};
394
        des2 = {src2[7:4],src1[3:0]};
395
      end
396
      desCy = 1'b0;
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      desAc = 1'b0;
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      desOv = 1'b0;
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      enable_mul = 1'b0;
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      enable_div = 1'b0;
401
    end
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    `OC8051_ALU_NOP: begin
403
      des_acc = src1;
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      des1 = src1;
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      des2 = src2;
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      desCy = srcCy;
407
      desAc = srcAc;
408
      desOv = 1'b0;
409
      enable_mul = 1'b0;
410
      enable_div = 1'b0;
411
    end
412
  endcase
413
end
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endmodule

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