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[/] [oms8051mini/] [trunk/] [rtl/] [8051/] [oc8051_alu_src_sel.v] - Blame information for rev 36

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 alu source select module                               ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/oms8051mini/                 ////
////                                                              ////
////  Description                                                 ////
////   Multiplexer wiht whitch we select data on alu sources      ////
////                                                              ////
////  To Do:                                                      ////
////   nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////   v0.0 - Dinesh A, 5th Jan 2017
////        1. Active edge of reset changed from High to Low
////   v0.1 - Dinesh A, 19th Jan 2017
////        1. Lint Error fix
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3  2003/06/03 17:13:57  simont
// remove pc_r register.
//
// Revision 1.2  2003/05/06 09:41:35  simont
// remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.
//
// Revision 1.1  2003/01/13 14:13:12  simont
// initial import
//
//
//
 
`include "top_defines.v"
 
 
module oc8051_alu_src_sel (clk, resetn, rd, sel1, sel2, sel3,
                     acc, ram, pc, dptr,
 
                     op1, op2, op3,
 
                     src1, src2, src3);
 
 
input clk, resetn, rd, sel3;
input [1:0] sel2;
input [2:0] sel1;
input [7:0] acc, ram;
input [15:0] dptr;
input [15:0] pc;
 
 
input [7:0] op1, op2, op3;
 
output [7:0] src1, src2, src3;
 
reg [7:0] src1, src2, src3;
 
reg [7:0] op1_r, op2_r, op3_r;
 
///////
//
// src1
//
///////
always @(sel1 or op1_r or op2_r or op3_r or pc or acc or ram)
begin
  case (sel1) /* synopsys full_case parallel_case */
    `OC8051_AS1_RAM: src1 = ram;
    `OC8051_AS1_ACC: src1 = acc;
    `OC8051_AS1_OP1: src1 = op1_r;
    `OC8051_AS1_OP2: src1 = op2_r;
    `OC8051_AS1_OP3: src1 = op3_r;
    `OC8051_AS1_PCH: src1 = pc[15:8];
    `OC8051_AS1_PCL: src1 = pc[7:0];
    default: src1 = 8'h00;
  endcase
end
 
///////
//
// src2
//
///////
always @(sel2 or op2_r or acc or ram or op1_r)
begin
  case (sel2) /* synopsys full_case parallel_case */
    `OC8051_AS2_ACC: src2= acc;
    `OC8051_AS2_ZERO: src2= 8'h00;
    `OC8051_AS2_RAM: src2= ram;
    `OC8051_AS2_OP2: src2= op2_r;
//    default: src2= 8'h00;
  endcase
end
 
///////
//
// src3
//
///////
 
always @(sel3 or pc[15:8] or dptr[15:8] or op1_r)
begin
  case (sel3) /* synopsys full_case parallel_case */
    `OC8051_AS3_DP:   src3= dptr[15:8];
    `OC8051_AS3_PC:   src3= pc[15:8];
//    default: src3= 16'h0;
  endcase
end
 
 
always @(posedge clk or negedge resetn)
  if (resetn == 1'b0) begin
    op1_r <= 8'h00;
    op2_r <= 8'h00;
    op3_r <= 8'h00;
  end else begin
    op1_r <= op1;
    op2_r <= op2;
    op3_r <= op3;
  end
 
endmodule

Line No.	Rev	Author	Line
1	2	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 alu source select module ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/oms8051mini/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Multiplexer wiht whitch we select data on alu sources ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16			`//// - Dinesh Annayya, dinesha@opencores.org ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19	25	dinesha	`//// v0.0 - Dinesh A, 5th Jan 2017`
20			`//// 1. Active edge of reset changed from High to Low`
21	36	dinesha	`//// v0.1 - Dinesh A, 19th Jan 2017`
22			`//// 1. Lint Error fix`
23	25	dinesha	`//////////////////////////////////////////////////////////////////////`
24	2	dinesha	`//// ////`
25			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
26			`//// ////`
27			`//// This source file may be used and distributed without ////`
28			`//// restriction provided that this copyright statement is not ////`
29			`//// removed from the file and that any derivative work contains ////`
30			`//// the original copyright notice and the associated disclaimer. ////`
31			`//// ////`
32			`//// This source file is free software; you can redistribute it ////`
33			`//// and/or modify it under the terms of the GNU Lesser General ////`
34			`//// Public License as published by the Free Software Foundation; ////`
35			`//// either version 2.1 of the License, or (at your option) any ////`
36			`//// later version. ////`
37			`//// ////`
38			`//// This source is distributed in the hope that it will be ////`
39			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
40			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
41			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
42			`//// details. ////`
43			`//// ////`
44			`//// You should have received a copy of the GNU Lesser General ////`
45			`//// Public License along with this source; if not, download it ////`
46			`//// from http://www.opencores.org/lgpl.shtml ////`
47			`//// ////`
48			`//////////////////////////////////////////////////////////////////////`
49			`//`
50			`// CVS Revision History`
51			`//`
52			`// $Log: not supported by cvs2svn $`
53			`// Revision 1.3 2003/06/03 17:13:57 simont`
54			`// remove pc_r register.`
55			`//`
56			`// Revision 1.2 2003/05/06 09:41:35 simont`
57			`// remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.`
58			`//`
59			`// Revision 1.1 2003/01/13 14:13:12 simont`
60			`// initial import`
61			`//`
62			`//`
63			`//`
64
65			`include "top_defines.v"
66
67
68	25	dinesha	`module oc8051_alu_src_sel (clk, resetn, rd, sel1, sel2, sel3,`
69	2	dinesha	`acc, ram, pc, dptr,`
70
71			`op1, op2, op3,`
72
73			`src1, src2, src3);`
74
75
76	25	dinesha	`input clk, resetn, rd, sel3;`
77	2	dinesha	`input [1:0] sel2;`
78			`input [2:0] sel1;`
79			`input [7:0] acc, ram;`
80			`input [15:0] dptr;`
81			`input [15:0] pc;`
82
83
84			`input [7:0] op1, op2, op3;`
85
86			`output [7:0] src1, src2, src3;`
87
88			`reg [7:0] src1, src2, src3;`
89
90			`reg [7:0] op1_r, op2_r, op3_r;`
91
92			`///////`
93			`//`
94			`// src1`
95			`//`
96			`///////`
97			`always @(sel1 or op1_r or op2_r or op3_r or pc or acc or ram)`
98			`begin`
99			`case (sel1) /* synopsys full_case parallel_case */`
100			`OC8051_AS1_RAM: src1 = ram;
101			`OC8051_AS1_ACC: src1 = acc;
102			`OC8051_AS1_OP1: src1 = op1_r;
103			`OC8051_AS1_OP2: src1 = op2_r;
104			`OC8051_AS1_OP3: src1 = op3_r;
105			`OC8051_AS1_PCH: src1 = pc[15:8];
106			`OC8051_AS1_PCL: src1 = pc[7:0];
107	36	dinesha	`default: src1 = 8'h00;`
108	2	dinesha	`endcase`
109			`end`
110
111			`///////`
112			`//`
113			`// src2`
114			`//`
115			`///////`
116			`always @(sel2 or op2_r or acc or ram or op1_r)`
117			`begin`
118			`case (sel2) /* synopsys full_case parallel_case */`
119			`OC8051_AS2_ACC: src2= acc;
120			`OC8051_AS2_ZERO: src2= 8'h00;
121			`OC8051_AS2_RAM: src2= ram;
122			`OC8051_AS2_OP2: src2= op2_r;
123			`// default: src2= 8'h00;`
124			`endcase`
125			`end`
126
127			`///////`
128			`//`
129			`// src3`
130			`//`
131			`///////`
132
133			`always @(sel3 or pc[15:8] or dptr[15:8] or op1_r)`
134			`begin`
135			`case (sel3) /* synopsys full_case parallel_case */`
136			`OC8051_AS3_DP: src3= dptr[15:8];
137			`OC8051_AS3_PC: src3= pc[15:8];
138			`// default: src3= 16'h0;`
139			`endcase`
140			`end`
141
142
143	25	dinesha	`always @(posedge clk or negedge resetn)`
144			`if (resetn == 1'b0) begin`
145	36	dinesha	`op1_r <= 8'h00;`
146			`op2_r <= 8'h00;`
147			`op3_r <= 8'h00;`
148	2	dinesha	`end else begin`
149	36	dinesha	`op1_r <= op1;`
150			`op2_r <= op2;`
151			`op3_r <= op3;`
152	2	dinesha	`end`
153
154			`endmodule`

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[/] [oms8051mini/] [trunk/] [rtl/] [8051/] [oc8051_alu_src_sel.v] - Blame information for rev 36