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[/] [oms8051mini/] [trunk/] [rtl/] [8051/] [oc8051_b_register.v] - Blame information for rev 25

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 cores b register                                       ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/oms8051mini/                 ////
////                                                              ////
////  Description                                                 ////
////   b register for 8051 core                                   ////
////                                                              ////
////  To Do:                                                      ////
////   Nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////   v0.0 - Dinesh A, 5th Jan 2017
////        1. Active edge of reset changed from High to Low
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8  2003/04/07 14:58:02  simont
// change sfr's interface.
//
// Revision 1.7  2003/01/13 14:14:40  simont
// replace some modules
//
// Revision 1.6  2002/09/30 17:33:59  simont
// prepared header
//
//
 
`include "top_defines.v"
 
 
module oc8051_b_register (clk, resetn, bit_in, data_in, wr, wr_bit,
              wr_addr, data_out);
 
 
input clk, resetn, wr, wr_bit, bit_in;
input [7:0] wr_addr, data_in;
 
output [7:0] data_out;
 
reg [7:0] data_out;
 
//
//writing to b
//must check if write high and correct address
always @(posedge clk or negedge resetn)
begin
  if (resetn == 1'b0)
    data_out <= #1 `OC8051_RST_B;
  else if (wr) begin
    if (!wr_bit) begin
      if (wr_addr==`OC8051_SFR_B)
        data_out <= #1 data_in;
    end else begin
      if (wr_addr[7:3]==`OC8051_SFR_B_B)
        data_out[wr_addr[2:0]] <= #1 bit_in;
    end
  end
end
 
endmodule

Line No.	Rev	Author	Line
1	2	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 cores b register ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/oms8051mini/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// b register for 8051 core ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// Nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16			`//// - Dinesh Annayya, dinesha@opencores.org ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19	25	dinesha	`//// v0.0 - Dinesh A, 5th Jan 2017`
20			`//// 1. Active edge of reset changed from High to Low`
21			`//////////////////////////////////////////////////////////////////////`
22	2	dinesha	`//// ////`
23			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
24			`//// ////`
25			`//// This source file may be used and distributed without ////`
26			`//// restriction provided that this copyright statement is not ////`
27			`//// removed from the file and that any derivative work contains ////`
28			`//// the original copyright notice and the associated disclaimer. ////`
29			`//// ////`
30			`//// This source file is free software; you can redistribute it ////`
31			`//// and/or modify it under the terms of the GNU Lesser General ////`
32			`//// Public License as published by the Free Software Foundation; ////`
33			`//// either version 2.1 of the License, or (at your option) any ////`
34			`//// later version. ////`
35			`//// ////`
36			`//// This source is distributed in the hope that it will be ////`
37			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
38			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
39			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
40			`//// details. ////`
41			`//// ////`
42			`//// You should have received a copy of the GNU Lesser General ////`
43			`//// Public License along with this source; if not, download it ////`
44			`//// from http://www.opencores.org/lgpl.shtml ////`
45			`//// ////`
46			`//////////////////////////////////////////////////////////////////////`
47			`//`
48			`// CVS Revision History`
49			`//`
50			`// $Log: not supported by cvs2svn $`
51			`// Revision 1.8 2003/04/07 14:58:02 simont`
52			`// change sfr's interface.`
53			`//`
54			`// Revision 1.7 2003/01/13 14:14:40 simont`
55			`// replace some modules`
56			`//`
57			`// Revision 1.6 2002/09/30 17:33:59 simont`
58			`// prepared header`
59			`//`
60			`//`
61
62			`include "top_defines.v"
63
64
65	25	dinesha	`module oc8051_b_register (clk, resetn, bit_in, data_in, wr, wr_bit,`
66	2	dinesha	`wr_addr, data_out);`
67
68
69	25	dinesha	`input clk, resetn, wr, wr_bit, bit_in;`
70	2	dinesha	`input [7:0] wr_addr, data_in;`
71
72			`output [7:0] data_out;`
73
74			`reg [7:0] data_out;`
75
76			`//`
77			`//writing to b`
78			`//must check if write high and correct address`
79	25	dinesha	`always @(posedge clk or negedge resetn)`
80	2	dinesha	`begin`
81	25	dinesha	`if (resetn == 1'b0)`
82	2	dinesha	data_out <= #1 `OC8051_RST_B;
83			`else if (wr) begin`
84			`if (!wr_bit) begin`
85			if (wr_addr==`OC8051_SFR_B)
86			`data_out <= #1 data_in;`
87			`end else begin`
88			if (wr_addr[7:3]==`OC8051_SFR_B_B)
89			`data_out[wr_addr[2:0]] <= #1 bit_in;`
90			`end`
91			`end`
92			`end`
93
94			`endmodule`

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[/] [oms8051mini/] [trunk/] [rtl/] [8051/] [oc8051_b_register.v] - Blame information for rev 25