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[/] [oms8051mini/] [trunk/] [rtl/] [8051/] [oc8051_ram_256x8_two_bist.v] - Blame information for rev 36

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 internal ram                                           ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/oms8051mini/                 ////
////                                                              ////
////  Description                                                 ////
////   256 bytes two port ram                                     ////
////                                                              ////
////  To Do:                                                      ////
////   nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////   v0.0 - Dinesh A, 5th Jan 2017
////        1. Active edge of reset changed from High to Low
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
//
 
 
`include "top_defines.v"
 
//
// two port ram
//
module oc8051_ram_256x8_two_bist (
                     clk,
                     resetn,
                     rd_addr,
                     rd_data,
                     rd_en,
                     wr_addr,
                     wr_data,
                     wr_en,
                     wr
`ifdef OC8051_BIST
         ,
         scanb_rst,
         scanb_clk,
         scanb_si,
         scanb_so,
         scanb_en
`endif
                     );
 
 
input         clk,
              wr,
              resetn,
              rd_en,
              wr_en;
input  [7:0]  wr_data;
input  [7:0]  rd_addr,
              wr_addr;
output [7:0]  rd_data;
 
`ifdef OC8051_BIST
input   scanb_rst;
input   scanb_clk;
input   scanb_si;
output  scanb_so;
input   scanb_en;
`endif
 
 
`ifdef OC8051_RAM_XILINX
  xilinx_ram_dp u_ram(
        // read port
        .CLKA(clk),
        .RSTA(resetn),
        .ENA(rd_en),
        .ADDRA(rd_addr),
        .DIA(8'h00),
        .WEA(1'b0),
        .DOA(rd_data),
 
        // write port
        .CLKB(clk),
        .RSTB(resetn),
        .ENB(wr_en),
        .ADDRB(wr_addr),
        .DIB(wr_data),
        .WEB(wr),
        .DOB()
  );
 
  defparam
        xilinx_ram.dwidth = 8,
        xilinx_ram.awidth = 8;
 
`elsif OC8051_RAM_VIRTUALSILICON
 
`elsif  OC8051_RAM_ACTEL
 
      oc8051_actel_ram_256x8  u_ram(
        .RWCLK  ( clk            ),
        .RESET  ( resetn            ),
        .REN   ( rd_en          ),
        .RADDR ( rd_addr        ),
        .RD    ( rd_data        ),
 
        .WEN    ( wr             ),
        .WADDR ( wr_addr        ),
        .WD    ( wr_data        )
      );
 
 
`elsif  OC8051_RAM_GENERIC
 
      generic_dpram #(8, 8) u_ram(
        .rclk  ( clk            ),
        .rresetn( resetn            ),
        .rce   ( rd_en          ),
        .oe    ( 1'b1           ),
        .raddr ( rd_addr        ),
        .do    ( rd_data        ),
 
        .wclk  ( clk            ),
        .wresetn  ( resetn            ),
        .wce   ( wr_en          ),
        .we    ( wr             ),
        .waddr ( wr_addr        ),
        .di    ( wr_data        )
      );
 
`else
 
      reg    [7:0]  rd_data;
      //
      // buffer
      reg    [7:0]  buff [0:256];
 
 
      //
      // writing to ram
      always @(posedge clk)
      begin
       if (wr)
          buff[wr_addr] <= wr_data;
      end
 
      //
      // reading from ram
      always @(posedge clk or negedge resetn)
      begin
        if (resetn == 1'b0)
          rd_data <= 8'h0;
        else if ((wr_addr==rd_addr) & wr & rd_en)
          rd_data <= wr_data;
        else if (rd_en)
          rd_data <= buff[rd_addr];
      end
`endif      //OC8051_RAM_XILINX
 
endmodule

Line No.	Rev	Author	Line
1	2	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 internal ram ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/oms8051mini/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// 256 bytes two port ram ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16			`//// - Dinesh Annayya, dinesha@opencores.org ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19	25	dinesha	`//// v0.0 - Dinesh A, 5th Jan 2017`
20			`//// 1. Active edge of reset changed from High to Low`
21			`//////////////////////////////////////////////////////////////////////`
22	2	dinesha	`//// ////`
23			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
24			`//// ////`
25			`//// This source file may be used and distributed without ////`
26			`//// restriction provided that this copyright statement is not ////`
27			`//// removed from the file and that any derivative work contains ////`
28			`//// the original copyright notice and the associated disclaimer. ////`
29			`//// ////`
30			`//// This source file is free software; you can redistribute it ////`
31			`//// and/or modify it under the terms of the GNU Lesser General ////`
32			`//// Public License as published by the Free Software Foundation; ////`
33			`//// either version 2.1 of the License, or (at your option) any ////`
34			`//// later version. ////`
35			`//// ////`
36			`//// This source is distributed in the hope that it will be ////`
37			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
38			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
39			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
40			`//// details. ////`
41			`//// ////`
42			`//// You should have received a copy of the GNU Lesser General ////`
43			`//// Public License along with this source; if not, download it ////`
44			`//// from http://www.opencores.org/lgpl.shtml ////`
45			`//// ////`
46			`//////////////////////////////////////////////////////////////////////`
47			`//`
48			`// CVS Revision History`
49			`//`
50			`// $Log: not supported by cvs2svn $`
51			`//`
52			`//`
53
54
55			`include "top_defines.v"
56
57			`//`
58			`// two port ram`
59			`//`
60			`module oc8051_ram_256x8_two_bist (`
61			`clk,`
62	25	dinesha	`resetn,`
63	2	dinesha	`rd_addr,`
64			`rd_data,`
65			`rd_en,`
66			`wr_addr,`
67			`wr_data,`
68			`wr_en,`
69			`wr`
70			`ifdef OC8051_BIST
71			`,`
72			`scanb_rst,`
73			`scanb_clk,`
74			`scanb_si,`
75			`scanb_so,`
76			`scanb_en`
77			`endif
78			`);`
79
80
81			`input clk,`
82			`wr,`
83	25	dinesha	`resetn,`
84	2	dinesha	`rd_en,`
85			`wr_en;`
86			`input [7:0] wr_data;`
87			`input [7:0] rd_addr,`
88			`wr_addr;`
89			`output [7:0] rd_data;`
90
91			`ifdef OC8051_BIST
92			`input scanb_rst;`
93			`input scanb_clk;`
94			`input scanb_si;`
95			`output scanb_so;`
96			`input scanb_en;`
97			`endif
98
99
100			`ifdef OC8051_RAM_XILINX
101	20	dinesha	`xilinx_ram_dp u_ram(`
102	2	dinesha	`// read port`
103			`.CLKA(clk),`
104	25	dinesha	`.RSTA(resetn),`
105	2	dinesha	`.ENA(rd_en),`
106			`.ADDRA(rd_addr),`
107			`.DIA(8'h00),`
108			`.WEA(1'b0),`
109			`.DOA(rd_data),`
110
111			`// write port`
112			`.CLKB(clk),`
113	25	dinesha	`.RSTB(resetn),`
114	2	dinesha	`.ENB(wr_en),`
115			`.ADDRB(wr_addr),`
116			`.DIB(wr_data),`
117			`.WEB(wr),`
118			`.DOB()`
119			`);`
120
121			`defparam`
122			`xilinx_ram.dwidth = 8,`
123			`xilinx_ram.awidth = 8;`
124
125			`elsif OC8051_RAM_VIRTUALSILICON
126
127			`elsif OC8051_RAM_ACTEL
128
129	20	dinesha	`oc8051_actel_ram_256x8 u_ram(`
130	2	dinesha	`.RWCLK ( clk ),`
131	25	dinesha	`.RESET ( resetn ),`
132	2	dinesha	`.REN ( rd_en ),`
133			`.RADDR ( rd_addr ),`
134			`.RD ( rd_data ),`
135
136			`.WEN ( wr ),`
137			`.WADDR ( wr_addr ),`
138			`.WD ( wr_data )`
139			`);`
140
141
142			`elsif OC8051_RAM_GENERIC
143
144	20	dinesha	`generic_dpram #(8, 8) u_ram(`
145	2	dinesha	`.rclk ( clk ),`
146	25	dinesha	`.rresetn( resetn ),`
147	2	dinesha	`.rce ( rd_en ),`
148			`.oe ( 1'b1 ),`
149			`.raddr ( rd_addr ),`
150			`.do ( rd_data ),`
151
152			`.wclk ( clk ),`
153	25	dinesha	`.wresetn ( resetn ),`
154	2	dinesha	`.wce ( wr_en ),`
155			`.we ( wr ),`
156			`.waddr ( wr_addr ),`
157			`.di ( wr_data )`
158			`);`
159
160			`else
161
162			`reg [7:0] rd_data;`
163			`//`
164			`// buffer`
165			`reg [7:0] buff [0:256];`
166
167
168			`//`
169			`// writing to ram`
170			`always @(posedge clk)`
171			`begin`
172			`if (wr)`
173	36	dinesha	`buff[wr_addr] <= wr_data;`
174	2	dinesha	`end`
175
176			`//`
177			`// reading from ram`
178	25	dinesha	`always @(posedge clk or negedge resetn)`
179	2	dinesha	`begin`
180	25	dinesha	`if (resetn == 1'b0)`
181	36	dinesha	`rd_data <= 8'h0;`
182	2	dinesha	`else if ((wr_addr==rd_addr) & wr & rd_en)`
183	36	dinesha	`rd_data <= wr_data;`
184	2	dinesha	`else if (rd_en)`
185	36	dinesha	`rd_data <= buff[rd_addr];`
186	2	dinesha	`end`
187			`endif //OC8051_RAM_XILINX
188
189			`endmodule`

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[/] [oms8051mini/] [trunk/] [rtl/] [8051/] [oc8051_ram_256x8_two_bist.v] - Blame information for rev 36