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[/] [oms8051mini/] [trunk/] [rtl/] [8051/] [oc8051_ram_64x32_dual_bist.v] - Blame information for rev 2

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 cache ram                                              ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/oms8051mini/                 ////
////                                                              ////
////  Description                                                 ////
////   64x31 dual port ram                                        ////
////                                                              ////
////  To Do:                                                      ////
////   nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
//
 
 
`include "top_defines.v"
 
//
// duble port ram
//
module oc8051_ram_64x32_dual_bist (
                     clk,
                     rst,
 
                     adr0,
                     dat0_o,
                     en0,
 
                     adr1,
                     dat1_i,
                     dat1_o,
                     en1,
                     wr1
`ifdef OC8051_BIST
         ,
         scanb_rst,
         scanb_clk,
         scanb_si,
         scanb_so,
         scanb_en
`endif
                     );
 
parameter ADR_WIDTH = 6;
 
input         clk,
              wr1,
              rst,
              en0,
              en1;
input  [7:0]  dat1_i;
input  [ADR_WIDTH-1:0]  adr0;
input  [ADR_WIDTH-1:0]  adr1;
 
output [31:0]  dat0_o;
output [31:0]  dat1_o;
 
reg    [7:0]  rd_data;
 
 
`ifdef OC8051_BIST
input   scanb_rst;
input   scanb_clk;
input   scanb_si;
output  scanb_so;
input   scanb_en;
`endif
 
 
`ifdef OC8051_RAM_XILINX
  xilinx_ram_dp xilinx_ram(
        // read port
        .CLKA(clk),
        .RSTA(rst),
        .ENA(en0),
        .ADDRA(adr0),
        .DIA(32'h00),
        .WEA(1'b0),
        .DOA(dat0_o),
 
        // write port
        .CLKB(clk),
        .RSTB(rst),
        .ENB(en1),
        .ADDRB(adr1),
        .DIB(dat1_i),
        .WEB(wr1),
        .DOB(dat1_o)
  );
 
  defparam
        xilinx_ram.dwidth = 32,
        xilinx_ram.awidth = ADR_WIDTH;
 
`else
 
  `ifdef OC8051_RAM_VIRTUALSILICON
 
  `else
 
    `ifdef OC8051_RAM_GENERIC
 
      generic_dpram #(ADR_WIDTH, 32) oc8051_ram1(
        .rclk  ( clk            ),
        .rrst  ( rst            ),
        .rce   ( en0            ),
        .oe    ( 1'b1           ),
        .raddr ( adr0           ),
        .do    ( dat0_o         ),
 
        .wclk  ( clk            ),
        .wrst  ( rst            ),
        .wce   ( en1            ),
        .we    ( wr1            ),
        .waddr ( adr1           ),
        .di    ( dat1_i         )
      );
 
    `else
 
      reg [31:0] dat1_o;
      reg [31:0] dat0_o;
      //
      // buffer
      reg    [31:0]  buff [0:(1<<ADR_WIDTH) -1];
 
      always @(posedge clk or posedge rst)
      begin
        if (rst)
          dat1_o     <= #1 32'h0;
        else if (wr1) begin
          buff[adr1] <= #1 dat1_i;
          dat1_o    <= #1 dat1_i;
        end else
          dat1_o <= #1 buff[adr1];
      end
 
      always @(posedge clk or posedge rst)
      begin
        if (rst)
          dat0_o <= #1 32'h0;
        else if ((adr0==adr1) & wr1)
          dat0_o <= #1 dat1_i;
        else
          dat0_o <= #1 buff[adr0];
      end
 
    `endif  //OC8051_RAM_GENERIC
  `endif    //OC8051_RAM_VIRTUALSILICON  
`endif      //OC8051_RAM_XILINX
 
endmodule

Line No.	Rev	Author	Line
1	2	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 cache ram ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/oms8051mini/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// 64x31 dual port ram ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16			`//// - Dinesh Annayya, dinesha@opencores.org ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48			`//`
49			`//`
50
51
52			`include "top_defines.v"
53
54			`//`
55			`// duble port ram`
56			`//`
57			`module oc8051_ram_64x32_dual_bist (`
58			`clk,`
59			`rst,`
60
61			`adr0,`
62			`dat0_o,`
63			`en0,`
64
65			`adr1,`
66			`dat1_i,`
67			`dat1_o,`
68			`en1,`
69			`wr1`
70			`ifdef OC8051_BIST
71			`,`
72			`scanb_rst,`
73			`scanb_clk,`
74			`scanb_si,`
75			`scanb_so,`
76			`scanb_en`
77			`endif
78			`);`
79
80			`parameter ADR_WIDTH = 6;`
81
82			`input clk,`
83			`wr1,`
84			`rst,`
85			`en0,`
86			`en1;`
87			`input [7:0] dat1_i;`
88			`input [ADR_WIDTH-1:0] adr0;`
89			`input [ADR_WIDTH-1:0] adr1;`
90
91			`output [31:0] dat0_o;`
92			`output [31:0] dat1_o;`
93
94			`reg [7:0] rd_data;`
95
96
97			`ifdef OC8051_BIST
98			`input scanb_rst;`
99			`input scanb_clk;`
100			`input scanb_si;`
101			`output scanb_so;`
102			`input scanb_en;`
103			`endif
104
105
106			`ifdef OC8051_RAM_XILINX
107			`xilinx_ram_dp xilinx_ram(`
108			`// read port`
109			`.CLKA(clk),`
110			`.RSTA(rst),`
111			`.ENA(en0),`
112			`.ADDRA(adr0),`
113			`.DIA(32'h00),`
114			`.WEA(1'b0),`
115			`.DOA(dat0_o),`
116
117			`// write port`
118			`.CLKB(clk),`
119			`.RSTB(rst),`
120			`.ENB(en1),`
121			`.ADDRB(adr1),`
122			`.DIB(dat1_i),`
123			`.WEB(wr1),`
124			`.DOB(dat1_o)`
125			`);`
126
127			`defparam`
128			`xilinx_ram.dwidth = 32,`
129			`xilinx_ram.awidth = ADR_WIDTH;`
130
131			`else
132
133			`ifdef OC8051_RAM_VIRTUALSILICON
134
135			`else
136
137			`ifdef OC8051_RAM_GENERIC
138
139			`generic_dpram #(ADR_WIDTH, 32) oc8051_ram1(`
140			`.rclk ( clk ),`
141			`.rrst ( rst ),`
142			`.rce ( en0 ),`
143			`.oe ( 1'b1 ),`
144			`.raddr ( adr0 ),`
145			`.do ( dat0_o ),`
146
147			`.wclk ( clk ),`
148			`.wrst ( rst ),`
149			`.wce ( en1 ),`
150			`.we ( wr1 ),`
151			`.waddr ( adr1 ),`
152			`.di ( dat1_i )`
153			`);`
154
155			`else
156
157			`reg [31:0] dat1_o;`
158			`reg [31:0] dat0_o;`
159			`//`
160			`// buffer`
161			`reg [31:0] buff [0:(1<<ADR_WIDTH) -1];`
162
163			`always @(posedge clk or posedge rst)`
164			`begin`
165			`if (rst)`
166			`dat1_o <= #1 32'h0;`
167			`else if (wr1) begin`
168			`buff[adr1] <= #1 dat1_i;`
169			`dat1_o <= #1 dat1_i;`
170			`end else`
171			`dat1_o <= #1 buff[adr1];`
172			`end`
173
174			`always @(posedge clk or posedge rst)`
175			`begin`
176			`if (rst)`
177			`dat0_o <= #1 32'h0;`
178			`else if ((adr0==adr1) & wr1)`
179			`dat0_o <= #1 dat1_i;`
180			`else`
181			`dat0_o <= #1 buff[adr0];`
182			`end`
183
184			`endif //OC8051_RAM_GENERIC
185			`endif //OC8051_RAM_VIRTUALSILICON
186			`endif //OC8051_RAM_XILINX
187
188			`endmodule`

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[/] [oms8051mini/] [trunk/] [rtl/] [8051/] [oc8051_ram_64x32_dual_bist.v] - Blame information for rev 2