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[/] [oms8051mini/] [trunk/] [rtl/] [8051/] [oc8051_sfr.v] - Blame information for rev 25

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 cores sfr top level module                             ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/oms8051mini/                 ////
////                                                              ////
////  Description                                                 ////
////   special function registers for oc8051                      ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////   v0.0 - Dinesh A, 5th Jan 2017
////        1. Active edge of reset changed from High to Low
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.14  2003/05/07 12:39:20  simont
// fix bug in case of sequence of inc dptr instrucitons.
//
// Revision 1.13  2003/05/05 15:46:37  simont
// add aditional alu destination to solve critical path.
//
// Revision 1.12  2003/04/29 11:24:31  simont
// fix bug in case execution of two data dependent instructions.
//
// Revision 1.11  2003/04/25 17:15:51  simont
// change branch instruction execution (reduse needed clock periods).
//
// Revision 1.10  2003/04/10 12:43:19  simont
// defines for pherypherals added
//
// Revision 1.9  2003/04/09 16:24:03  simont
// change wr_sft to 2 bit wire.
//
// Revision 1.8  2003/04/09 15:49:42  simont
// Register oc8051_sfr dato output, add signal wait_data.
//
// Revision 1.7  2003/04/07 14:58:02  simont
// change sfr's interface.
//
// Revision 1.6  2003/04/07 13:29:16  simont
// change uart to meet timing.
//
// Revision 1.5  2003/04/04 10:35:07  simont
// signal prsc_ow added.
//
// Revision 1.4  2003/03/28 17:45:57  simont
// change module name.
//
// Revision 1.3  2003/01/21 13:51:30  simont
// add include oc8051_defines.v
//
// Revision 1.2  2003/01/13 14:14:41  simont
// replace some modules
//
// Revision 1.1  2002/11/05 17:22:27  simont
// initial import
//
//
 
 
`include "top_defines.v"
 
 
module oc8051_sfr (resetn, clk,
       adr0, adr1, dat0,
       dat1, dat2, bit_in,
       des_acc,
       we, wr_bit,
       bit_out,
       wr_sfr, acc,
       ram_wr_sel, ram_rd_sel,
       sp, sp_w,
       bank_sel,
       desAc, desOv,
       srcAc, cy,
       psw_set, rmw,
       comp_sel,
       comp_wait,
 
`ifdef OC8051_PORTS
 
  `ifdef OC8051_PORT0
       p0_out,
       p0_in,
  `endif
 
  `ifdef OC8051_PORT1
       p1_out,
       p1_in,
  `endif
 
  `ifdef OC8051_PORT2
       p2_out,
       p2_in,
  `endif
 
  `ifdef OC8051_PORT3
       p3_out,
       p3_in,
  `endif
 
`endif
 
 
  `ifdef OC8051_UART
       rxd, txd,
  `endif
 
       int_ack, intr,
       int0, int1,
       int_src,
       reti,
 
  `ifdef OC8051_TC01
       t0, t1,
  `endif
 
  `ifdef OC8051_TC2
       t2, t2ex,
  `endif
 
       dptr_hi, dptr_lo,
       wait_data);
 
 
input       resetn,     // reset - pin
            clk,        // clock - pin
            we,         // write enable
            bit_in,
            desAc,
            desOv,
            rmw;
input       int_ack,
            int0,
            int1,
            reti,
            wr_bit;
input [1:0] psw_set,
            wr_sfr,
            comp_sel;
input [2:0] ram_rd_sel,
            ram_wr_sel;
input [7:0] adr0,        //address 0 input
            adr1,       //address 1 input
            des_acc,
            dat1,       //data 1 input (des1)
            dat2;       //data 2 input (des2)
 
output       bit_out,
             intr,
             srcAc,
             cy,
             wait_data,
             comp_wait;
output [1:0] bank_sel;
output [7:0] dat0,       //data output
             int_src,
             dptr_hi,
             dptr_lo,
             acc;
output [7:0] sp,
             sp_w;
 
// ports
`ifdef OC8051_PORTS
 
`ifdef OC8051_PORT0
input  [7:0] p0_in;
output [7:0] p0_out;
wire   [7:0] p0_data;
`endif
 
`ifdef OC8051_PORT1
input  [7:0] p1_in;
output [7:0] p1_out;
wire   [7:0] p1_data;
`endif
 
`ifdef OC8051_PORT2
input  [7:0] p2_in;
output [7:0] p2_out;
wire   [7:0] p2_data;
`endif
 
`ifdef OC8051_PORT3
input  [7:0] p3_in;
output [7:0] p3_out;
wire   [7:0] p3_data;
`endif
 
`endif
 
 
// serial interface
`ifdef OC8051_UART
input        rxd;
output       txd;
`endif
 
// timer/counter 0,1
`ifdef OC8051_TC01
input        t0, t1;
`endif
 
// timer/counter 2
`ifdef OC8051_TC2
input        t2, t2ex;
`endif
 
reg        bit_out,
           wait_data;
reg [7:0]  dat0,
           adr0_r;
 
reg        wr_bit_r;
reg [2:0]  ram_wr_sel_r;
 
 
wire       p,
           uart_int,
           tf0,
           tf1,
           tr0,
           tr1,
           rclk,
           tclk,
           brate2,
           tc2_int;
 
 
wire [7:0] b_reg,
           psw,
 
`ifdef OC8051_TC2
  // t/c 2
           t2con,
           tl2,
           th2,
           rcap2l,
           rcap2h,
`endif
 
`ifdef OC8051_TC01
  // t/c 0,1
           tmod,
           tl0,
           th0,
           tl1,
           th1,
`endif
 
  // serial interface
`ifdef OC8051_UART
           scon,
           pcon,
           sbuf,
`endif
 
  //interrupt control
           ie,
           tcon,
           ip;
 
 
reg        pres_ow;
reg [3:0]  prescaler;
 
 
assign cy = psw[7];
assign srcAc = psw [6];
 
 
 
//
// accumulator
// ACC
oc8051_acc oc8051_acc1(.clk(clk),
                       .resetn(resetn),
                       .bit_in(bit_in),
                       .data_in(des_acc),
                       .data2_in(dat2),
                       .wr(we),
                       .wr_bit(wr_bit_r),
                       .wr_sfr(wr_sfr),
                       .wr_addr(adr1),
                       .data_out(acc),
                       .p(p));
 
 
//
// b register
// B
oc8051_b_register oc8051_b_register (.clk(clk),
                                     .resetn(resetn),
                                     .bit_in(bit_in),
                                     .data_in(des_acc),
                                     .wr(we),
                                     .wr_bit(wr_bit_r),
                                     .wr_addr(adr1),
                                     .data_out(b_reg));
 
//
//stack pointer
// SP
oc8051_sp oc8051_sp1(.clk(clk),
                     .resetn(resetn),
                     .ram_rd_sel(ram_rd_sel),
                     .ram_wr_sel(ram_wr_sel),
                     .wr_addr(adr1),
                     .wr(we),
                     .wr_bit(wr_bit_r),
                     .data_in(dat1),
                     .sp_out(sp),
                     .sp_w(sp_w));
 
//
//data pointer
// DPTR, DPH, DPL
oc8051_dptr oc8051_dptr1(.clk(clk),
                         .resetn(resetn),
                         .addr(adr1),
                         .data_in(des_acc),
                         .data2_in(dat2),
                         .wr(we),
                         .wr_bit(wr_bit_r),
                         .data_hi(dptr_hi),
                         .data_lo(dptr_lo),
                         .wr_sfr(wr_sfr));
 
 
//
//program status word
// PSW
oc8051_psw oc8051_psw1 (.clk(clk),
                        .resetn(resetn),
                        .wr_addr(adr1),
                        .data_in(dat1),
                        .wr(we),
                        .wr_bit(wr_bit_r),
                        .data_out(psw),
                        .p(p),
                        .cy_in(bit_in),
                        .ac_in(desAc),
                        .ov_in(desOv),
                        .set(psw_set),
                        .bank_sel(bank_sel));
 
//
// ports
// P0, P1, P2, P3
`ifdef OC8051_PORTS
  oc8051_ports oc8051_ports1(.clk(clk),
                           .resetn(resetn),
                           .bit_in(bit_in),
                           .data_in(dat1),
                           .wr(we),
                           .wr_bit(wr_bit_r),
                           .wr_addr(adr1),
 
                `ifdef OC8051_PORT0
                           .p0_out(p0_out),
                           .p0_in(p0_in),
                           .p0_data(p0_data),
                `endif
 
                `ifdef OC8051_PORT1
                           .p1_out(p1_out),
                           .p1_in(p1_in),
                           .p1_data(p1_data),
                `endif
 
                `ifdef OC8051_PORT2
                           .p2_out(p2_out),
                           .p2_in(p2_in),
                           .p2_data(p2_data),
                `endif
 
                `ifdef OC8051_PORT3
                           .p3_out(p3_out),
                           .p3_in(p3_in),
                           .p3_data(p3_data),
                `endif
 
                           .rmw(rmw));
`endif
 
//
// serial interface
// SCON, SBUF
`ifdef OC8051_UART
  oc8051_uart oc8051_uatr1 (.clk(clk),
                            .resetn(resetn),
                            .bit_in(bit_in),
                            .data_in(dat1),
                            .wr(we),
                            .wr_bit(wr_bit_r),
                            .wr_addr(adr1),
                            .rxd(rxd),
                            .txd(txd),
                // interrupt
                            .intr(uart_int),
                // baud rate sources
                            .brate2(brate2),
                            .t1_ow(tf1),
                            .pres_ow(pres_ow),
                            .rclk(rclk),
                            .tclk(tclk),
                //registers
                            .scon(scon),
                            .pcon(pcon),
                            .sbuf(sbuf));
`else
  assign uart_int = 1'b0;
`endif
 
//
// interrupt control
// IP, IE, TCON
oc8051_int oc8051_int1 (.clk(clk),
                        .resetn(resetn),
                        .wr_addr(adr1),
                        .bit_in(bit_in),
                        .ack(int_ack),
                        .data_in(dat1),
                        .wr(we),
                        .wr_bit(wr_bit_r),
                        .tf0(tf0),
                        .tf1(tf1),
                        .t2_int(tc2_int),
                        .tr0(tr0),
                        .tr1(tr1),
                        .ie0(int0),
                        .ie1(int1),
                        .uart_int(uart_int),
                        .reti(reti),
                        .intr(intr),
                        .int_vec(int_src),
                        .ie(ie),
                        .tcon(tcon),
                        .ip(ip));
 
 
//
// timer/counter control
// TH0, TH1, TL0, TH1, TMOD
`ifdef OC8051_TC01
  oc8051_tc oc8051_tc1(.clk(clk),
                       .resetn(resetn),
                       .wr_addr(adr1),
                       .data_in(dat1),
                       .wr(we),
                       .wr_bit(wr_bit_r),
                       .ie0(int0),
                       .ie1(int1),
                       .tr0(tr0),
                       .tr1(tr1),
                       .t0(t0),
                       .t1(t1),
                       .tf0(tf0),
                       .tf1(tf1),
                       .pres_ow(pres_ow),
                       .tmod(tmod),
                       .tl0(tl0),
                       .th0(th0),
                       .tl1(tl1),
                       .th1(th1));
`else
  assign tf0 = 1'b0;
  assign tf1 = 1'b0;
`endif
 
//
// timer/counter 2
// TH2, TL2, RCAPL2L, RCAPL2H, T2CON
`ifdef OC8051_TC2
  oc8051_tc2 oc8051_tc21(.clk(clk),
                         .resetn(resetn),
                         .wr_addr(adr1),
                         .data_in(dat1),
                         .wr(we),
                         .wr_bit(wr_bit_r),
                         .bit_in(bit_in),
                         .t2(t2),
                         .t2ex(t2ex),
                         .rclk(rclk),
                         .tclk(tclk),
                         .brate2(brate2),
                         .tc2_int(tc2_int),
                         .pres_ow(pres_ow),
                         .t2con(t2con),
                         .tl2(tl2),
                         .th2(th2),
                         .rcap2l(rcap2l),
                         .rcap2h(rcap2h));
`else
  assign tc2_int = 1'b0;
  assign rclk    = 1'b0;
  assign tclk    = 1'b0;
  assign brate2  = 1'b0;
`endif
 
 
 
always @(posedge clk or negedge resetn)
  if (resetn == 1'b0) begin
    adr0_r <= #1 8'h00;
    ram_wr_sel_r <= #1 3'b000;
    wr_bit_r <= #1 1'b0;
//    wait_data <= #1 1'b0;
  end else begin
    adr0_r <= #1 adr0;
    ram_wr_sel_r <= #1 ram_wr_sel;
    wr_bit_r <= #1 wr_bit;
  end
 
assign comp_wait = !(
                    ((comp_sel==`OC8051_CSS_AZ) &
                       ((wr_sfr==`OC8051_WRS_ACC1) |
                        (wr_sfr==`OC8051_WRS_ACC2) |
                        ((adr1==`OC8051_SFR_ACC) & we & !wr_bit_r) |
                        ((adr1[7:3]==`OC8051_SFR_B_ACC) & we & wr_bit_r))) |
                    ((comp_sel==`OC8051_CSS_CY) &
                       ((|psw_set) |
                        ((adr1==`OC8051_SFR_PSW) & we & !wr_bit_r) |
                        ((adr1[7:3]==`OC8051_SFR_B_PSW) & we & wr_bit_r))) |
                    ((comp_sel==`OC8051_CSS_BIT) &
                       ((adr1[7:3]==adr0[7:3]) & (~&adr1[2:0]) &  we & !wr_bit_r) |
                       ((adr1==adr0) & adr1[7] & we & !wr_bit_r)));
 
 
 
//
//set output in case of address (byte)
always @(posedge clk or negedge resetn)
begin
  if (resetn == 1'b0) begin
    dat0 <= #1 8'h00;
    wait_data <= #1 1'b0;
  end else if ((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) begin                          //write and read same address
    dat0 <= #1 des_acc;
    wait_data <= #1 1'b0;
  end else if (
      (
        ((wr_sfr==`OC8051_WRS_ACC1) & (adr0==`OC8051_SFR_ACC)) |        //write to acc
//        ((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) |  //write to dpl
        (adr1[7] & (adr1==adr0) & we & !wr_bit_r) |                     //write and read same address
        (adr1[7] & (adr1[7:3]==adr0[7:3]) & (~&adr0[2:0]) &  we & wr_bit_r) //write bit addressable to read address
      ) & !wait_data) begin
    wait_data <= #1 1'b1;
 
  end else if ((
      ((|psw_set) & (adr0==`OC8051_SFR_PSW)) |
      ((wr_sfr==`OC8051_WRS_ACC2) & (adr0==`OC8051_SFR_ACC)) |  //write to acc
      ((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_HI))        //write to dph
      ) & !wait_data) begin
    wait_data <= #1 1'b1;
 
  end else begin
    case (adr0) /* synopsys full_case parallel_case */
      `OC8051_SFR_ACC:          dat0 <= #1 acc;
      `OC8051_SFR_PSW:          dat0 <= #1 psw;
 
`ifdef OC8051_PORTS
  `ifdef OC8051_PORT0
      `OC8051_SFR_P0:           dat0 <= #1 p0_data;
  `endif
 
  `ifdef OC8051_PORT1
      `OC8051_SFR_P1:           dat0 <= #1 p1_data;
  `endif
 
  `ifdef OC8051_PORT2
      `OC8051_SFR_P2:           dat0 <= #1 p2_data;
  `endif
 
  `ifdef OC8051_PORT3
      `OC8051_SFR_P3:           dat0 <= #1 p3_data;
  `endif
`endif
 
      `OC8051_SFR_SP:           dat0 <= #1 sp;
      `OC8051_SFR_B:            dat0 <= #1 b_reg;
      `OC8051_SFR_DPTR_HI:      dat0 <= #1 dptr_hi;
      `OC8051_SFR_DPTR_LO:      dat0 <= #1 dptr_lo;
 
`ifdef OC8051_UART
      `OC8051_SFR_SCON:         dat0 <= #1 scon;
      `OC8051_SFR_SBUF:         dat0 <= #1 sbuf;
      `OC8051_SFR_PCON:         dat0 <= #1 pcon;
`endif
 
`ifdef OC8051_TC01
      `OC8051_SFR_TH0:          dat0 <= #1 th0;
      `OC8051_SFR_TH1:          dat0 <= #1 th1;
      `OC8051_SFR_TL0:          dat0 <= #1 tl0;
      `OC8051_SFR_TL1:          dat0 <= #1 tl1;
      `OC8051_SFR_TMOD:         dat0 <= #1 tmod;
`endif
 
      `OC8051_SFR_IP:           dat0 <= #1 ip;
      `OC8051_SFR_IE:           dat0 <= #1 ie;
      `OC8051_SFR_TCON:         dat0 <= #1 tcon;
 
`ifdef OC8051_TC2
      `OC8051_SFR_RCAP2H:       dat0 <= #1 rcap2h;
      `OC8051_SFR_RCAP2L:       dat0 <= #1 rcap2l;
      `OC8051_SFR_TH2:          dat0 <= #1 th2;
      `OC8051_SFR_TL2:          dat0 <= #1 tl2;
      `OC8051_SFR_T2CON:        dat0 <= #1 t2con;
`endif
 
//      default:                        dat0 <= #1 8'h00;
    endcase
    wait_data <= #1 1'b0;
  end
end
 
 
//
//set output in case of address (bit)
 
always @(posedge clk or negedge resetn)
begin
  if (resetn == 1'b0)
    bit_out <= #1 1'h0;
  else if (
          ((adr1[7:3]==adr0[7:3]) & (~&adr1[2:0]) &  we & !wr_bit_r) |
          ((wr_sfr==`OC8051_WRS_ACC1) & (adr0[7:3]==`OC8051_SFR_B_ACC))         //write to acc
          )
 
    bit_out <= #1 dat1[adr0[2:0]];
  else if ((adr1==adr0) & we & wr_bit_r)
    bit_out <= #1 bit_in;
  else
    case (adr0[7:3]) /* synopsys full_case parallel_case */
      `OC8051_SFR_B_ACC:   bit_out <= #1 acc[adr0[2:0]];
      `OC8051_SFR_B_PSW:   bit_out <= #1 psw[adr0[2:0]];
 
`ifdef OC8051_PORTS
  `ifdef OC8051_PORT0
      `OC8051_SFR_B_P0:    bit_out <= #1 p0_data[adr0[2:0]];
  `endif
 
  `ifdef OC8051_PORT1
      `OC8051_SFR_B_P1:    bit_out <= #1 p1_data[adr0[2:0]];
  `endif
 
  `ifdef OC8051_PORT2
      `OC8051_SFR_B_P2:    bit_out <= #1 p2_data[adr0[2:0]];
  `endif
 
  `ifdef OC8051_PORT3
      `OC8051_SFR_B_P3:    bit_out <= #1 p3_data[adr0[2:0]];
  `endif
`endif
 
      `OC8051_SFR_B_B:     bit_out <= #1 b_reg[adr0[2:0]];
      `OC8051_SFR_B_IP:    bit_out <= #1 ip[adr0[2:0]];
      `OC8051_SFR_B_IE:    bit_out <= #1 ie[adr0[2:0]];
      `OC8051_SFR_B_TCON:  bit_out <= #1 tcon[adr0[2:0]];
 
`ifdef OC8051_UART
      `OC8051_SFR_B_SCON:  bit_out <= #1 scon[adr0[2:0]];
`endif
 
`ifdef OC8051_TC2
      `OC8051_SFR_B_T2CON: bit_out <= #1 t2con[adr0[2:0]];
`endif
 
//      default:             bit_out <= #1 1'b0;
    endcase
end
 
always @(posedge clk or negedge resetn)
begin
  if (resetn == 1'b0) begin
    prescaler <= #1 4'h0;
    pres_ow <= #1 1'b0;
  end else if (prescaler==4'b1011) begin
    prescaler <= #1 4'h0;
    pres_ow <= #1 1'b1;
  end else begin
    prescaler <= #1 prescaler + 4'h1;
    pres_ow <= #1 1'b0;
  end
end
 
endmodule

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[/] [oms8051mini/] [trunk/] [rtl/] [8051/] [oc8051_sfr.v] - Blame information for rev 25

Line No.	Rev	Author	Line
1	2	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 cores sfr top level module ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/oms8051mini/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// special function registers for oc8051 ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16			`//// - Dinesh Annayya, dinesha@opencores.org ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19	25	dinesha	`//// v0.0 - Dinesh A, 5th Jan 2017`
20			`//// 1. Active edge of reset changed from High to Low`
21			`//////////////////////////////////////////////////////////////////////`
22	2	dinesha	`//// ////`
23			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
24			`//// ////`
25			`//// This source file may be used and distributed without ////`
26			`//// restriction provided that this copyright statement is not ////`
27			`//// removed from the file and that any derivative work contains ////`
28			`//// the original copyright notice and the associated disclaimer. ////`
29			`//// ////`
30			`//// This source file is free software; you can redistribute it ////`
31			`//// and/or modify it under the terms of the GNU Lesser General ////`
32			`//// Public License as published by the Free Software Foundation; ////`
33			`//// either version 2.1 of the License, or (at your option) any ////`
34			`//// later version. ////`
35			`//// ////`
36			`//// This source is distributed in the hope that it will be ////`
37			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
38			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
39			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
40			`//// details. ////`
41			`//// ////`
42			`//// You should have received a copy of the GNU Lesser General ////`
43			`//// Public License along with this source; if not, download it ////`
44			`//// from http://www.opencores.org/lgpl.shtml ////`
45			`//// ////`
46			`//////////////////////////////////////////////////////////////////////`
47			`//`
48			`// CVS Revision History`
49			`//`
50			`// $Log: not supported by cvs2svn $`
51			`// Revision 1.14 2003/05/07 12:39:20 simont`
52			`// fix bug in case of sequence of inc dptr instrucitons.`
53			`//`
54			`// Revision 1.13 2003/05/05 15:46:37 simont`
55			`// add aditional alu destination to solve critical path.`
56			`//`
57			`// Revision 1.12 2003/04/29 11:24:31 simont`
58			`// fix bug in case execution of two data dependent instructions.`
59			`//`
60			`// Revision 1.11 2003/04/25 17:15:51 simont`
61			`// change branch instruction execution (reduse needed clock periods).`
62			`//`
63			`// Revision 1.10 2003/04/10 12:43:19 simont`
64			`// defines for pherypherals added`
65			`//`
66			`// Revision 1.9 2003/04/09 16:24:03 simont`
67			`// change wr_sft to 2 bit wire.`
68			`//`
69			`// Revision 1.8 2003/04/09 15:49:42 simont`
70			`// Register oc8051_sfr dato output, add signal wait_data.`
71			`//`
72			`// Revision 1.7 2003/04/07 14:58:02 simont`
73			`// change sfr's interface.`
74			`//`
75			`// Revision 1.6 2003/04/07 13:29:16 simont`
76			`// change uart to meet timing.`
77			`//`
78			`// Revision 1.5 2003/04/04 10:35:07 simont`
79			`// signal prsc_ow added.`
80			`//`
81			`// Revision 1.4 2003/03/28 17:45:57 simont`
82			`// change module name.`
83			`//`
84			`// Revision 1.3 2003/01/21 13:51:30 simont`
85			`// add include oc8051_defines.v`
86			`//`
87			`// Revision 1.2 2003/01/13 14:14:41 simont`
88			`// replace some modules`
89			`//`
90			`// Revision 1.1 2002/11/05 17:22:27 simont`
91			`// initial import`
92			`//`
93			`//`
94
95
96			`include "top_defines.v"
97
98
99	25	dinesha	`module oc8051_sfr (resetn, clk,`
100	2	dinesha	`adr0, adr1, dat0,`
101			`dat1, dat2, bit_in,`
102			`des_acc,`
103			`we, wr_bit,`
104			`bit_out,`
105			`wr_sfr, acc,`
106			`ram_wr_sel, ram_rd_sel,`
107			`sp, sp_w,`
108			`bank_sel,`
109			`desAc, desOv,`
110			`srcAc, cy,`
111			`psw_set, rmw,`
112			`comp_sel,`
113			`comp_wait,`
114
115			`ifdef OC8051_PORTS
116
117			`ifdef OC8051_PORT0
118			`p0_out,`
119			`p0_in,`
120			`endif
121
122			`ifdef OC8051_PORT1
123			`p1_out,`
124			`p1_in,`
125			`endif
126
127			`ifdef OC8051_PORT2
128			`p2_out,`
129			`p2_in,`
130			`endif
131
132			`ifdef OC8051_PORT3
133			`p3_out,`
134			`p3_in,`
135			`endif
136
137			`endif
138
139
140			`ifdef OC8051_UART
141			`rxd, txd,`
142			`endif
143
144			`int_ack, intr,`
145			`int0, int1,`
146			`int_src,`
147			`reti,`
148
149			`ifdef OC8051_TC01
150			`t0, t1,`
151			`endif
152
153			`ifdef OC8051_TC2
154			`t2, t2ex,`
155			`endif
156
157			`dptr_hi, dptr_lo,`
158			`wait_data);`
159
160
161	25	dinesha	`input resetn, // reset - pin`
162	2	dinesha	`clk, // clock - pin`
163			`we, // write enable`
164			`bit_in,`
165			`desAc,`
166			`desOv,`
167			`rmw;`
168			`input int_ack,`
169			`int0,`
170			`int1,`
171			`reti,`
172			`wr_bit;`
173			`input [1:0] psw_set,`
174			`wr_sfr,`
175			`comp_sel;`
176			`input [2:0] ram_rd_sel,`
177			`ram_wr_sel;`
178			`input [7:0] adr0, //address 0 input`
179			`adr1, //address 1 input`
180			`des_acc,`
181			`dat1, //data 1 input (des1)`
182			`dat2; //data 2 input (des2)`
183
184			`output bit_out,`
185			`intr,`
186			`srcAc,`
187			`cy,`
188			`wait_data,`
189			`comp_wait;`
190			`output [1:0] bank_sel;`
191			`output [7:0] dat0, //data output`
192			`int_src,`
193			`dptr_hi,`
194			`dptr_lo,`
195			`acc;`
196			`output [7:0] sp,`
197			`sp_w;`
198
199			`// ports`
200			`ifdef OC8051_PORTS
201
202			`ifdef OC8051_PORT0
203			`input [7:0] p0_in;`
204			`output [7:0] p0_out;`
205			`wire [7:0] p0_data;`
206			`endif
207
208			`ifdef OC8051_PORT1
209			`input [7:0] p1_in;`
210			`output [7:0] p1_out;`
211			`wire [7:0] p1_data;`
212			`endif
213
214			`ifdef OC8051_PORT2
215			`input [7:0] p2_in;`
216			`output [7:0] p2_out;`
217			`wire [7:0] p2_data;`
218			`endif
219
220			`ifdef OC8051_PORT3
221			`input [7:0] p3_in;`
222			`output [7:0] p3_out;`
223			`wire [7:0] p3_data;`
224			`endif
225
226			`endif
227
228
229			`// serial interface`
230			`ifdef OC8051_UART
231			`input rxd;`
232			`output txd;`
233			`endif
234
235			`// timer/counter 0,1`
236			`ifdef OC8051_TC01
237			`input t0, t1;`
238			`endif
239
240			`// timer/counter 2`
241			`ifdef OC8051_TC2
242			`input t2, t2ex;`
243			`endif
244
245			`reg bit_out,`
246			`wait_data;`
247			`reg [7:0] dat0,`
248			`adr0_r;`
249
250			`reg wr_bit_r;`
251			`reg [2:0] ram_wr_sel_r;`
252
253
254			`wire p,`
255			`uart_int,`
256			`tf0,`
257			`tf1,`
258			`tr0,`
259			`tr1,`
260			`rclk,`
261			`tclk,`
262			`brate2,`
263			`tc2_int;`
264
265
266			`wire [7:0] b_reg,`
267			`psw,`
268
269			`ifdef OC8051_TC2
270			`// t/c 2`
271			`t2con,`
272			`tl2,`
273			`th2,`
274			`rcap2l,`
275			`rcap2h,`
276			`endif
277
278			`ifdef OC8051_TC01
279			`// t/c 0,1`
280			`tmod,`
281			`tl0,`
282			`th0,`
283			`tl1,`
284			`th1,`
285			`endif
286
287			`// serial interface`
288			`ifdef OC8051_UART
289			`scon,`
290			`pcon,`
291			`sbuf,`
292			`endif
293
294			`//interrupt control`
295			`ie,`
296			`tcon,`
297			`ip;`
298
299
300			`reg pres_ow;`
301			`reg [3:0] prescaler;`
302
303
304			`assign cy = psw[7];`
305			`assign srcAc = psw [6];`
306
307
308
309			`//`
310			`// accumulator`
311			`// ACC`
312			`oc8051_acc oc8051_acc1(.clk(clk),`
313	25	dinesha	`.resetn(resetn),`
314	2	dinesha	`.bit_in(bit_in),`
315			`.data_in(des_acc),`
316			`.data2_in(dat2),`
317			`.wr(we),`
318			`.wr_bit(wr_bit_r),`
319			`.wr_sfr(wr_sfr),`
320			`.wr_addr(adr1),`
321			`.data_out(acc),`
322			`.p(p));`
323
324
325			`//`
326			`// b register`
327			`// B`
328			`oc8051_b_register oc8051_b_register (.clk(clk),`
329	25	dinesha	`.resetn(resetn),`
330	2	dinesha	`.bit_in(bit_in),`
331			`.data_in(des_acc),`
332			`.wr(we),`
333			`.wr_bit(wr_bit_r),`
334			`.wr_addr(adr1),`
335			`.data_out(b_reg));`
336
337			`//`
338			`//stack pointer`
339			`// SP`
340			`oc8051_sp oc8051_sp1(.clk(clk),`
341	25	dinesha	`.resetn(resetn),`
342	2	dinesha	`.ram_rd_sel(ram_rd_sel),`
343			`.ram_wr_sel(ram_wr_sel),`
344			`.wr_addr(adr1),`
345			`.wr(we),`
346			`.wr_bit(wr_bit_r),`
347			`.data_in(dat1),`
348			`.sp_out(sp),`
349			`.sp_w(sp_w));`
350
351			`//`
352			`//data pointer`
353			`// DPTR, DPH, DPL`
354			`oc8051_dptr oc8051_dptr1(.clk(clk),`
355	25	dinesha	`.resetn(resetn),`
356	2	dinesha	`.addr(adr1),`
357			`.data_in(des_acc),`
358			`.data2_in(dat2),`
359			`.wr(we),`
360			`.wr_bit(wr_bit_r),`
361			`.data_hi(dptr_hi),`
362			`.data_lo(dptr_lo),`
363			`.wr_sfr(wr_sfr));`
364
365
366			`//`
367			`//program status word`
368			`// PSW`
369			`oc8051_psw oc8051_psw1 (.clk(clk),`
370	25	dinesha	`.resetn(resetn),`
371	2	dinesha	`.wr_addr(adr1),`
372			`.data_in(dat1),`
373			`.wr(we),`
374			`.wr_bit(wr_bit_r),`
375			`.data_out(psw),`
376			`.p(p),`
377			`.cy_in(bit_in),`
378			`.ac_in(desAc),`
379			`.ov_in(desOv),`
380			`.set(psw_set),`
381			`.bank_sel(bank_sel));`
382
383			`//`
384			`// ports`
385			`// P0, P1, P2, P3`
386			`ifdef OC8051_PORTS
387			`oc8051_ports oc8051_ports1(.clk(clk),`
388	25	dinesha	`.resetn(resetn),`
389	2	dinesha	`.bit_in(bit_in),`
390			`.data_in(dat1),`
391			`.wr(we),`
392			`.wr_bit(wr_bit_r),`
393			`.wr_addr(adr1),`
394
395			`ifdef OC8051_PORT0
396			`.p0_out(p0_out),`
397			`.p0_in(p0_in),`
398			`.p0_data(p0_data),`
399			`endif
400
401			`ifdef OC8051_PORT1
402			`.p1_out(p1_out),`
403			`.p1_in(p1_in),`
404			`.p1_data(p1_data),`
405			`endif
406
407			`ifdef OC8051_PORT2
408			`.p2_out(p2_out),`
409			`.p2_in(p2_in),`
410			`.p2_data(p2_data),`
411			`endif
412
413			`ifdef OC8051_PORT3
414			`.p3_out(p3_out),`
415			`.p3_in(p3_in),`
416			`.p3_data(p3_data),`
417			`endif
418
419			`.rmw(rmw));`
420			`endif
421
422			`//`
423			`// serial interface`
424			`// SCON, SBUF`
425			`ifdef OC8051_UART
426			`oc8051_uart oc8051_uatr1 (.clk(clk),`
427	25	dinesha	`.resetn(resetn),`
428	2	dinesha	`.bit_in(bit_in),`
429			`.data_in(dat1),`
430			`.wr(we),`
431			`.wr_bit(wr_bit_r),`
432			`.wr_addr(adr1),`
433			`.rxd(rxd),`
434			`.txd(txd),`
435			`// interrupt`
436			`.intr(uart_int),`
437			`// baud rate sources`
438			`.brate2(brate2),`
439			`.t1_ow(tf1),`
440			`.pres_ow(pres_ow),`
441			`.rclk(rclk),`
442			`.tclk(tclk),`
443			`//registers`
444			`.scon(scon),`
445			`.pcon(pcon),`
446			`.sbuf(sbuf));`
447			`else
448			`assign uart_int = 1'b0;`
449			`endif
450
451			`//`
452			`// interrupt control`
453			`// IP, IE, TCON`
454			`oc8051_int oc8051_int1 (.clk(clk),`
455	25	dinesha	`.resetn(resetn),`
456	2	dinesha	`.wr_addr(adr1),`
457			`.bit_in(bit_in),`
458			`.ack(int_ack),`
459			`.data_in(dat1),`
460			`.wr(we),`
461			`.wr_bit(wr_bit_r),`
462			`.tf0(tf0),`
463			`.tf1(tf1),`
464			`.t2_int(tc2_int),`
465			`.tr0(tr0),`
466			`.tr1(tr1),`
467			`.ie0(int0),`
468			`.ie1(int1),`
469			`.uart_int(uart_int),`
470			`.reti(reti),`
471			`.intr(intr),`
472			`.int_vec(int_src),`
473			`.ie(ie),`
474			`.tcon(tcon),`
475			`.ip(ip));`
476
477
478			`//`
479			`// timer/counter control`
480			`// TH0, TH1, TL0, TH1, TMOD`
481			`ifdef OC8051_TC01
482			`oc8051_tc oc8051_tc1(.clk(clk),`
483	25	dinesha	`.resetn(resetn),`
484	2	dinesha	`.wr_addr(adr1),`
485			`.data_in(dat1),`
486			`.wr(we),`
487			`.wr_bit(wr_bit_r),`
488			`.ie0(int0),`
489			`.ie1(int1),`
490			`.tr0(tr0),`
491			`.tr1(tr1),`
492			`.t0(t0),`
493			`.t1(t1),`
494			`.tf0(tf0),`
495			`.tf1(tf1),`
496			`.pres_ow(pres_ow),`
497			`.tmod(tmod),`
498			`.tl0(tl0),`
499			`.th0(th0),`
500			`.tl1(tl1),`
501			`.th1(th1));`
502			`else
503			`assign tf0 = 1'b0;`
504			`assign tf1 = 1'b0;`
505			`endif
506
507			`//`
508			`// timer/counter 2`
509			`// TH2, TL2, RCAPL2L, RCAPL2H, T2CON`
510			`ifdef OC8051_TC2
511			`oc8051_tc2 oc8051_tc21(.clk(clk),`
512	25	dinesha	`.resetn(resetn),`
513	2	dinesha	`.wr_addr(adr1),`
514			`.data_in(dat1),`
515			`.wr(we),`
516			`.wr_bit(wr_bit_r),`
517			`.bit_in(bit_in),`
518			`.t2(t2),`
519			`.t2ex(t2ex),`
520			`.rclk(rclk),`
521			`.tclk(tclk),`
522			`.brate2(brate2),`
523			`.tc2_int(tc2_int),`
524			`.pres_ow(pres_ow),`
525			`.t2con(t2con),`
526			`.tl2(tl2),`
527			`.th2(th2),`
528			`.rcap2l(rcap2l),`
529			`.rcap2h(rcap2h));`
530			`else
531			`assign tc2_int = 1'b0;`
532			`assign rclk = 1'b0;`
533			`assign tclk = 1'b0;`
534			`assign brate2 = 1'b0;`
535			`endif
536
537
538
539	25	dinesha	`always @(posedge clk or negedge resetn)`
540			`if (resetn == 1'b0) begin`
541	2	dinesha	`adr0_r <= #1 8'h00;`
542			`ram_wr_sel_r <= #1 3'b000;`
543			`wr_bit_r <= #1 1'b0;`
544			`// wait_data <= #1 1'b0;`
545			`end else begin`
546			`adr0_r <= #1 adr0;`
547			`ram_wr_sel_r <= #1 ram_wr_sel;`
548			`wr_bit_r <= #1 wr_bit;`
549			`end`
550
551			`assign comp_wait = !(`
552			((comp_sel==`OC8051_CSS_AZ) &
553			((wr_sfr==`OC8051_WRS_ACC1) \|
554			(wr_sfr==`OC8051_WRS_ACC2) \|
555			((adr1==`OC8051_SFR_ACC) & we & !wr_bit_r) \|
556			((adr1[7:3]==`OC8051_SFR_B_ACC) & we & wr_bit_r))) \|
557			((comp_sel==`OC8051_CSS_CY) &
558			`((\|psw_set) \|`
559			((adr1==`OC8051_SFR_PSW) & we & !wr_bit_r) \|
560			((adr1[7:3]==`OC8051_SFR_B_PSW) & we & wr_bit_r))) \|
561			((comp_sel==`OC8051_CSS_BIT) &
562			`((adr1[7:3]==adr0[7:3]) & (~&adr1[2:0]) & we & !wr_bit_r) \|`
563			`((adr1==adr0) & adr1[7] & we & !wr_bit_r)));`
564
565
566
567			`//`
568			`//set output in case of address (byte)`
569	25	dinesha	`always @(posedge clk or negedge resetn)`
570	2	dinesha	`begin`
571	25	dinesha	`if (resetn == 1'b0) begin`
572	2	dinesha	`dat0 <= #1 8'h00;`
573			`wait_data <= #1 1'b0;`
574			end else if ((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) begin //write and read same address
575			`dat0 <= #1 des_acc;`
576			`wait_data <= #1 1'b0;`
577			`end else if (`
578			`(`
579			((wr_sfr==`OC8051_WRS_ACC1) & (adr0==`OC8051_SFR_ACC)) \| //write to acc
580			// ((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) \| //write to dpl
581			`(adr1[7] & (adr1==adr0) & we & !wr_bit_r) \| //write and read same address`
582			`(adr1[7] & (adr1[7:3]==adr0[7:3]) & (~&adr0[2:0]) & we & wr_bit_r) //write bit addressable to read address`
583			`) & !wait_data) begin`
584			`wait_data <= #1 1'b1;`
585
586			`end else if ((`
587			((\|psw_set) & (adr0==`OC8051_SFR_PSW)) \|
588			((wr_sfr==`OC8051_WRS_ACC2) & (adr0==`OC8051_SFR_ACC)) \| //write to acc
589			((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_HI)) //write to dph
590			`) & !wait_data) begin`
591			`wait_data <= #1 1'b1;`
592
593			`end else begin`
594			`case (adr0) /* synopsys full_case parallel_case */`
595			`OC8051_SFR_ACC: dat0 <= #1 acc;
596			`OC8051_SFR_PSW: dat0 <= #1 psw;
597
598			`ifdef OC8051_PORTS
599			`ifdef OC8051_PORT0
600			`OC8051_SFR_P0: dat0 <= #1 p0_data;
601			`endif
602
603			`ifdef OC8051_PORT1
604			`OC8051_SFR_P1: dat0 <= #1 p1_data;
605			`endif
606
607			`ifdef OC8051_PORT2
608			`OC8051_SFR_P2: dat0 <= #1 p2_data;
609			`endif
610
611			`ifdef OC8051_PORT3
612			`OC8051_SFR_P3: dat0 <= #1 p3_data;
613			`endif
614			`endif
615
616			`OC8051_SFR_SP: dat0 <= #1 sp;
617			`OC8051_SFR_B: dat0 <= #1 b_reg;
618			`OC8051_SFR_DPTR_HI: dat0 <= #1 dptr_hi;
619			`OC8051_SFR_DPTR_LO: dat0 <= #1 dptr_lo;
620
621			`ifdef OC8051_UART
622			`OC8051_SFR_SCON: dat0 <= #1 scon;
623			`OC8051_SFR_SBUF: dat0 <= #1 sbuf;
624			`OC8051_SFR_PCON: dat0 <= #1 pcon;
625			`endif
626
627			`ifdef OC8051_TC01
628			`OC8051_SFR_TH0: dat0 <= #1 th0;
629			`OC8051_SFR_TH1: dat0 <= #1 th1;
630			`OC8051_SFR_TL0: dat0 <= #1 tl0;
631			`OC8051_SFR_TL1: dat0 <= #1 tl1;
632			`OC8051_SFR_TMOD: dat0 <= #1 tmod;
633			`endif
634
635			`OC8051_SFR_IP: dat0 <= #1 ip;
636			`OC8051_SFR_IE: dat0 <= #1 ie;
637			`OC8051_SFR_TCON: dat0 <= #1 tcon;
638
639			`ifdef OC8051_TC2
640			`OC8051_SFR_RCAP2H: dat0 <= #1 rcap2h;
641			`OC8051_SFR_RCAP2L: dat0 <= #1 rcap2l;
642			`OC8051_SFR_TH2: dat0 <= #1 th2;
643			`OC8051_SFR_TL2: dat0 <= #1 tl2;
644			`OC8051_SFR_T2CON: dat0 <= #1 t2con;
645			`endif
646
647			`// default: dat0 <= #1 8'h00;`
648			`endcase`
649			`wait_data <= #1 1'b0;`
650			`end`
651			`end`
652
653
654			`//`
655			`//set output in case of address (bit)`
656
657	25	dinesha	`always @(posedge clk or negedge resetn)`
658	2	dinesha	`begin`
659	25	dinesha	`if (resetn == 1'b0)`
660	2	dinesha	`bit_out <= #1 1'h0;`
661			`else if (`
662			`((adr1[7:3]==adr0[7:3]) & (~&adr1[2:0]) & we & !wr_bit_r) \|`
663			((wr_sfr==`OC8051_WRS_ACC1) & (adr0[7:3]==`OC8051_SFR_B_ACC)) //write to acc
664			`)`
665
666			`bit_out <= #1 dat1[adr0[2:0]];`
667			`else if ((adr1==adr0) & we & wr_bit_r)`
668			`bit_out <= #1 bit_in;`
669			`else`
670			`case (adr0[7:3]) /* synopsys full_case parallel_case */`
671			`OC8051_SFR_B_ACC: bit_out <= #1 acc[adr0[2:0]];
672			`OC8051_SFR_B_PSW: bit_out <= #1 psw[adr0[2:0]];
673
674			`ifdef OC8051_PORTS
675			`ifdef OC8051_PORT0
676			`OC8051_SFR_B_P0: bit_out <= #1 p0_data[adr0[2:0]];
677			`endif
678
679			`ifdef OC8051_PORT1
680			`OC8051_SFR_B_P1: bit_out <= #1 p1_data[adr0[2:0]];
681			`endif
682
683			`ifdef OC8051_PORT2
684			`OC8051_SFR_B_P2: bit_out <= #1 p2_data[adr0[2:0]];
685			`endif
686
687			`ifdef OC8051_PORT3
688			`OC8051_SFR_B_P3: bit_out <= #1 p3_data[adr0[2:0]];
689			`endif
690			`endif
691
692			`OC8051_SFR_B_B: bit_out <= #1 b_reg[adr0[2:0]];
693			`OC8051_SFR_B_IP: bit_out <= #1 ip[adr0[2:0]];
694			`OC8051_SFR_B_IE: bit_out <= #1 ie[adr0[2:0]];
695			`OC8051_SFR_B_TCON: bit_out <= #1 tcon[adr0[2:0]];
696
697			`ifdef OC8051_UART
698			`OC8051_SFR_B_SCON: bit_out <= #1 scon[adr0[2:0]];
699			`endif
700
701			`ifdef OC8051_TC2
702			`OC8051_SFR_B_T2CON: bit_out <= #1 t2con[adr0[2:0]];
703			`endif
704
705			`// default: bit_out <= #1 1'b0;`
706			`endcase`
707			`end`
708
709	25	dinesha	`always @(posedge clk or negedge resetn)`
710	2	dinesha	`begin`
711	25	dinesha	`if (resetn == 1'b0) begin`
712	2	dinesha	`prescaler <= #1 4'h0;`
713			`pres_ow <= #1 1'b0;`
714			`end else if (prescaler==4'b1011) begin`
715			`prescaler <= #1 4'h0;`
716			`pres_ow <= #1 1'b1;`
717			`end else begin`
718			`prescaler <= #1 prescaler + 4'h1;`
719			`pres_ow <= #1 1'b0;`
720			`end`
721			`end`
722
723			`endmodule`