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[/] [oms8051mini/] [trunk/] [rtl/] [8051/] [oc8051_sfr.v] - Blame information for rev 36

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 cores sfr top level module                             ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/oms8051mini/                 ////
////                                                              ////
////  Description                                                 ////
////   special function registers for oc8051                      ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////   v0.0 - Dinesh A, 5th Jan 2017
////        1. Active edge of reset changed from High to Low
////   v0.1 - Dinesh A, 19th Jan 2017
////        1. Lint Warning fixes
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.14  2003/05/07 12:39:20  simont
// fix bug in case of sequence of inc dptr instrucitons.
//
// Revision 1.13  2003/05/05 15:46:37  simont
// add aditional alu destination to solve critical path.
//
// Revision 1.12  2003/04/29 11:24:31  simont
// fix bug in case execution of two data dependent instructions.
//
// Revision 1.11  2003/04/25 17:15:51  simont
// change branch instruction execution (reduse needed clock periods).
//
// Revision 1.10  2003/04/10 12:43:19  simont
// defines for pherypherals added
//
// Revision 1.9  2003/04/09 16:24:03  simont
// change wr_sft to 2 bit wire.
//
// Revision 1.8  2003/04/09 15:49:42  simont
// Register oc8051_sfr dato output, add signal wait_data.
//
// Revision 1.7  2003/04/07 14:58:02  simont
// change sfr's interface.
//
// Revision 1.6  2003/04/07 13:29:16  simont
// change uart to meet timing.
//
// Revision 1.5  2003/04/04 10:35:07  simont
// signal prsc_ow added.
//
// Revision 1.4  2003/03/28 17:45:57  simont
// change module name.
//
// Revision 1.3  2003/01/21 13:51:30  simont
// add include oc8051_defines.v
//
// Revision 1.2  2003/01/13 14:14:41  simont
// replace some modules
//
// Revision 1.1  2002/11/05 17:22:27  simont
// initial import
//
//
 
 
`include "top_defines.v"
 
 
module oc8051_sfr (resetn, clk,
       adr0, adr1, dat0,
       dat1, dat2, bit_in,
       des_acc,
       we, wr_bit,
       bit_out,
       wr_sfr, acc,
       ram_wr_sel, ram_rd_sel,
       sp, sp_w,
       bank_sel,
       desAc, desOv,
       srcAc, cy,
       psw_set, rmw,
       comp_sel,
       comp_wait,
 
`ifdef OC8051_PORTS
 
  `ifdef OC8051_PORT0
       p0_out,
       p0_in,
  `endif
 
  `ifdef OC8051_PORT1
       p1_out,
       p1_in,
  `endif
 
  `ifdef OC8051_PORT2
       p2_out,
       p2_in,
  `endif
 
  `ifdef OC8051_PORT3
       p3_out,
       p3_in,
  `endif
 
`endif
 
 
  `ifdef OC8051_UART
       rxd, txd,
  `endif
 
       int_ack, intr,
       int0, int1,
       int_src,
       reti,
 
  `ifdef OC8051_TC01
       t0, t1,
  `endif
 
  `ifdef OC8051_TC2
       t2, t2ex,
  `endif
 
       dptr_hi, dptr_lo,
       wait_data);
 
 
input       resetn,     // reset - pin
            clk,        // clock - pin
            we,         // write enable
            bit_in,
            desAc,
            desOv,
            rmw;
input       int_ack,
            int0,
            int1,
            reti,
            wr_bit;
input [1:0] psw_set,
            wr_sfr,
            comp_sel;
input [2:0] ram_rd_sel,
            ram_wr_sel;
input [7:0] adr0,        //address 0 input
            adr1,       //address 1 input
            des_acc,
            dat1,       //data 1 input (des1)
            dat2;       //data 2 input (des2)
 
output       bit_out,
             intr,
             srcAc,
             cy,
             wait_data,
             comp_wait;
output [1:0] bank_sel;
output [7:0] dat0,       //data output
             int_src,
             dptr_hi,
             dptr_lo,
             acc;
output [7:0] sp,
             sp_w;
 
// ports
`ifdef OC8051_PORTS
 
`ifdef OC8051_PORT0
input  [7:0] p0_in;
output [7:0] p0_out;
wire   [7:0] p0_data;
`endif
 
`ifdef OC8051_PORT1
input  [7:0] p1_in;
output [7:0] p1_out;
wire   [7:0] p1_data;
`endif
 
`ifdef OC8051_PORT2
input  [7:0] p2_in;
output [7:0] p2_out;
wire   [7:0] p2_data;
`endif
 
`ifdef OC8051_PORT3
input  [7:0] p3_in;
output [7:0] p3_out;
wire   [7:0] p3_data;
`endif
 
`endif
 
 
// serial interface
`ifdef OC8051_UART
input        rxd;
output       txd;
`endif
 
// timer/counter 0,1
`ifdef OC8051_TC01
input        t0, t1;
`endif
 
// timer/counter 2
`ifdef OC8051_TC2
input        t2, t2ex;
`endif
 
reg        bit_out,
           wait_data;
reg [7:0]  dat0,
           adr0_r;
 
reg        wr_bit_r;
reg [2:0]  ram_wr_sel_r;
 
 
wire       p,
           uart_int,
           tf0,
           tf1,
           tr0,
           tr1,
           rclk,
           tclk,
           brate2,
           tc2_int;
 
 
wire [7:0] b_reg,
           psw,
 
`ifdef OC8051_TC2
  // t/c 2
           t2con,
           tl2,
           th2,
           rcap2l,
           rcap2h,
`endif
 
`ifdef OC8051_TC01
  // t/c 0,1
           tmod,
           tl0,
           th0,
           tl1,
           th1,
`endif
 
  // serial interface
`ifdef OC8051_UART
           scon,
           pcon,
           sbuf,
`endif
 
  //interrupt control
           ie,
           tcon,
           ip;
 
 
reg        pres_ow;
reg [3:0]  prescaler;
 
 
assign cy = psw[7];
assign srcAc = psw [6];
 
 
 
//
// accumulator
// ACC
oc8051_acc oc8051_acc1(.clk(clk),
                       .resetn(resetn),
                       .bit_in(bit_in),
                       .data_in(des_acc),
                       .data2_in(dat2),
                       .wr(we),
                       .wr_bit(wr_bit_r),
                       .wr_sfr(wr_sfr),
                       .wr_addr(adr1),
                       .data_out(acc),
                       .p(p));
 
 
//
// b register
// B
oc8051_b_register oc8051_b_register (.clk(clk),
                                     .resetn(resetn),
                                     .bit_in(bit_in),
                                     .data_in(des_acc),
                                     .wr(we),
                                     .wr_bit(wr_bit_r),
                                     .wr_addr(adr1),
                                     .data_out(b_reg));
 
//
//stack pointer
// SP
oc8051_sp oc8051_sp1(.clk(clk),
                     .resetn(resetn),
                     .ram_rd_sel(ram_rd_sel),
                     .ram_wr_sel(ram_wr_sel),
                     .wr_addr(adr1),
                     .wr(we),
                     .wr_bit(wr_bit_r),
                     .data_in(dat1),
                     .sp_out(sp),
                     .sp_w(sp_w));
 
//
//data pointer
// DPTR, DPH, DPL
oc8051_dptr oc8051_dptr1(.clk(clk),
                         .resetn(resetn),
                         .addr(adr1),
                         .data_in(des_acc),
                         .data2_in(dat2),
                         .wr(we),
                         .wr_bit(wr_bit_r),
                         .data_hi(dptr_hi),
                         .data_lo(dptr_lo),
                         .wr_sfr(wr_sfr));
 
 
//
//program status word
// PSW
oc8051_psw oc8051_psw1 (.clk(clk),
                        .resetn(resetn),
                        .wr_addr(adr1),
                        .data_in(dat1),
                        .wr(we),
                        .wr_bit(wr_bit_r),
                        .data_out(psw),
                        .p(p),
                        .cy_in(bit_in),
                        .ac_in(desAc),
                        .ov_in(desOv),
                        .set(psw_set),
                        .bank_sel(bank_sel));
 
//
// ports
// P0, P1, P2, P3
`ifdef OC8051_PORTS
  oc8051_ports oc8051_ports1(.clk(clk),
                           .resetn(resetn),
                           .bit_in(bit_in),
                           .data_in(dat1),
                           .wr(we),
                           .wr_bit(wr_bit_r),
                           .wr_addr(adr1),
 
                `ifdef OC8051_PORT0
                           .p0_out(p0_out),
                           .p0_in(p0_in),
                           .p0_data(p0_data),
                `endif
 
                `ifdef OC8051_PORT1
                           .p1_out(p1_out),
                           .p1_in(p1_in),
                           .p1_data(p1_data),
                `endif
 
                `ifdef OC8051_PORT2
                           .p2_out(p2_out),
                           .p2_in(p2_in),
                           .p2_data(p2_data),
                `endif
 
                `ifdef OC8051_PORT3
                           .p3_out(p3_out),
                           .p3_in(p3_in),
                           .p3_data(p3_data),
                `endif
 
                           .rmw(rmw));
`endif
 
//
// serial interface
// SCON, SBUF
`ifdef OC8051_UART
  oc8051_uart oc8051_uatr1 (.clk(clk),
                            .resetn(resetn),
                            .bit_in(bit_in),
                            .data_in(dat1),
                            .wr(we),
                            .wr_bit(wr_bit_r),
                            .wr_addr(adr1),
                            .rxd(rxd),
                            .txd(txd),
                // interrupt
                            .intr(uart_int),
                // baud rate sources
                            .brate2(brate2),
                            .t1_ow(tf1),
                            .pres_ow(pres_ow),
                            .rclk(rclk),
                            .tclk(tclk),
                //registers
                            .scon(scon),
                            .pcon(pcon),
                            .sbuf(sbuf));
`else
  assign uart_int = 1'b0;
`endif
 
//
// interrupt control
// IP, IE, TCON
oc8051_int oc8051_int1 (.clk(clk),
                        .resetn(resetn),
                        .wr_addr(adr1),
                        .bit_in(bit_in),
                        .ack(int_ack),
                        .data_in(dat1),
                        .wr(we),
                        .wr_bit(wr_bit_r),
                        .tf0(tf0),
                        .tf1(tf1),
                        .t2_int(tc2_int),
                        .tr0(tr0),
                        .tr1(tr1),
                        .ie0(int0),
                        .ie1(int1),
                        .uart_int(uart_int),
                        .reti(reti),
                        .intr(intr),
                        .int_vec(int_src),
                        .ie(ie),
                        .tcon(tcon),
                        .ip(ip));
 
 
//
// timer/counter control
// TH0, TH1, TL0, TH1, TMOD
`ifdef OC8051_TC01
  oc8051_tc oc8051_tc1(.clk(clk),
                       .resetn(resetn),
                       .wr_addr(adr1),
                       .data_in(dat1),
                       .wr(we),
                       .wr_bit(wr_bit_r),
                       .ie0(int0),
                       .ie1(int1),
                       .tr0(tr0),
                       .tr1(tr1),
                       .t0(t0),
                       .t1(t1),
                       .tf0(tf0),
                       .tf1(tf1),
                       .pres_ow(pres_ow),
                       .tmod(tmod),
                       .tl0(tl0),
                       .th0(th0),
                       .tl1(tl1),
                       .th1(th1));
`else
  assign tf0 = 1'b0;
  assign tf1 = 1'b0;
`endif
 
//
// timer/counter 2
// TH2, TL2, RCAPL2L, RCAPL2H, T2CON
`ifdef OC8051_TC2
  oc8051_tc2 oc8051_tc21(.clk(clk),
                         .resetn(resetn),
                         .wr_addr(adr1),
                         .data_in(dat1),
                         .wr(we),
                         .wr_bit(wr_bit_r),
                         .bit_in(bit_in),
                         .t2(t2),
                         .t2ex(t2ex),
                         .rclk(rclk),
                         .tclk(tclk),
                         .brate2(brate2),
                         .tc2_int(tc2_int),
                         .pres_ow(pres_ow),
                         .t2con(t2con),
                         .tl2(tl2),
                         .th2(th2),
                         .rcap2l(rcap2l),
                         .rcap2h(rcap2h));
`else
  assign tc2_int = 1'b0;
  assign rclk    = 1'b0;
  assign tclk    = 1'b0;
  assign brate2  = 1'b0;
`endif
 
 
 
always @(posedge clk or negedge resetn)
  if (resetn == 1'b0) begin
    adr0_r <= 8'h00;
    ram_wr_sel_r <= 3'b000;
    wr_bit_r <= 1'b0;
//    wait_data <= 1'b0;
  end else begin
    adr0_r <= adr0;
    ram_wr_sel_r <= ram_wr_sel;
    wr_bit_r <= wr_bit;
  end
 
assign comp_wait = !(
                    ((comp_sel==`OC8051_CSS_AZ) &
                       ((wr_sfr==`OC8051_WRS_ACC1) |
                        (wr_sfr==`OC8051_WRS_ACC2) |
                        ((adr1==`OC8051_SFR_ACC) & we & !wr_bit_r) |
                        ((adr1[7:3]==`OC8051_SFR_B_ACC) & we & wr_bit_r))) |
                    ((comp_sel==`OC8051_CSS_CY) &
                       ((|psw_set) |
                        ((adr1==`OC8051_SFR_PSW) & we & !wr_bit_r) |
                        ((adr1[7:3]==`OC8051_SFR_B_PSW) & we & wr_bit_r))) |
                    ((comp_sel==`OC8051_CSS_BIT) &
                       ((adr1[7:3]==adr0[7:3]) & (~&adr1[2:0]) &  we & !wr_bit_r) |
                       ((adr1==adr0) & adr1[7] & we & !wr_bit_r)));
 
 
 
//
//set output in case of address (byte)
always @(posedge clk or negedge resetn)
begin
  if (resetn == 1'b0) begin
    dat0 <= 8'h00;
    wait_data <= 1'b0;
  end else if ((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) begin                          //write and read same address
    dat0 <= des_acc;
    wait_data <= 1'b0;
  end else if (
      (
        ((wr_sfr==`OC8051_WRS_ACC1) & (adr0==`OC8051_SFR_ACC)) |        //write to acc
//        ((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) |  //write to dpl
        (adr1[7] & (adr1==adr0) & we & !wr_bit_r) |                     //write and read same address
        (adr1[7] & (adr1[7:3]==adr0[7:3]) & (~&adr0[2:0]) &  we & wr_bit_r) //write bit addressable to read address
      ) & !wait_data) begin
    wait_data <= 1'b1;
 
  end else if ((
      ((|psw_set) & (adr0==`OC8051_SFR_PSW)) |
      ((wr_sfr==`OC8051_WRS_ACC2) & (adr0==`OC8051_SFR_ACC)) |  //write to acc
      ((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_HI))        //write to dph
      ) & !wait_data) begin
    wait_data <= 1'b1;
 
  end else begin
    case (adr0) /* synopsys full_case parallel_case */
      `OC8051_SFR_ACC:          dat0 <= acc;
      `OC8051_SFR_PSW:          dat0 <= psw;
 
`ifdef OC8051_PORTS
  `ifdef OC8051_PORT0
      `OC8051_SFR_P0:           dat0 <= p0_data;
  `endif
 
  `ifdef OC8051_PORT1
      `OC8051_SFR_P1:           dat0 <= p1_data;
  `endif
 
  `ifdef OC8051_PORT2
      `OC8051_SFR_P2:           dat0 <= p2_data;
  `endif
 
  `ifdef OC8051_PORT3
      `OC8051_SFR_P3:           dat0 <= p3_data;
  `endif
`endif
 
      `OC8051_SFR_SP:           dat0 <= sp;
      `OC8051_SFR_B:            dat0 <= b_reg;
      `OC8051_SFR_DPTR_HI:      dat0 <= dptr_hi;
      `OC8051_SFR_DPTR_LO:      dat0 <= dptr_lo;
 
`ifdef OC8051_UART
      `OC8051_SFR_SCON:         dat0 <= scon;
      `OC8051_SFR_SBUF:         dat0 <= sbuf;
      `OC8051_SFR_PCON:         dat0 <= pcon;
`endif
 
`ifdef OC8051_TC01
      `OC8051_SFR_TH0:          dat0 <= th0;
      `OC8051_SFR_TH1:          dat0 <= th1;
      `OC8051_SFR_TL0:          dat0 <= tl0;
      `OC8051_SFR_TL1:          dat0 <= tl1;
      `OC8051_SFR_TMOD:         dat0 <= tmod;
`endif
 
      `OC8051_SFR_IP:           dat0 <= ip;
      `OC8051_SFR_IE:           dat0 <= ie;
      `OC8051_SFR_TCON:         dat0 <= tcon;
 
`ifdef OC8051_TC2
      `OC8051_SFR_RCAP2H:       dat0 <= rcap2h;
      `OC8051_SFR_RCAP2L:       dat0 <= rcap2l;
      `OC8051_SFR_TH2:          dat0 <= th2;
      `OC8051_SFR_TL2:          dat0 <= tl2;
      `OC8051_SFR_T2CON:        dat0 <= t2con;
`endif
 
      default:                  dat0 <= 8'h00;
    endcase
    wait_data <= 1'b0;
  end
end
 
 
//
//set output in case of address (bit)
 
always @(posedge clk or negedge resetn)
begin
  if (resetn == 1'b0)
    bit_out <= 1'h0;
  else if (
          ((adr1[7:3]==adr0[7:3]) & (~&adr1[2:0]) &  we & !wr_bit_r) |
          ((wr_sfr==`OC8051_WRS_ACC1) & (adr0[7:3]==`OC8051_SFR_B_ACC))         //write to acc
          )
 
    bit_out <= dat1[adr0[2:0]];
  else if ((adr1==adr0) & we & wr_bit_r)
    bit_out <= bit_in;
  else
    case (adr0[7:3]) /* synopsys full_case parallel_case */
      `OC8051_SFR_B_ACC:   bit_out <= acc[adr0[2:0]];
      `OC8051_SFR_B_PSW:   bit_out <= psw[adr0[2:0]];
 
`ifdef OC8051_PORTS
  `ifdef OC8051_PORT0
      `OC8051_SFR_B_P0:    bit_out <= p0_data[adr0[2:0]];
  `endif
 
  `ifdef OC8051_PORT1
      `OC8051_SFR_B_P1:    bit_out <= p1_data[adr0[2:0]];
  `endif
 
  `ifdef OC8051_PORT2
      `OC8051_SFR_B_P2:    bit_out <= p2_data[adr0[2:0]];
  `endif
 
  `ifdef OC8051_PORT3
      `OC8051_SFR_B_P3:    bit_out <= p3_data[adr0[2:0]];
  `endif
`endif
 
      `OC8051_SFR_B_B:     bit_out <= b_reg[adr0[2:0]];
      `OC8051_SFR_B_IP:    bit_out <= ip[adr0[2:0]];
      `OC8051_SFR_B_IE:    bit_out <= ie[adr0[2:0]];
      `OC8051_SFR_B_TCON:  bit_out <= tcon[adr0[2:0]];
 
`ifdef OC8051_UART
      `OC8051_SFR_B_SCON:  bit_out <= scon[adr0[2:0]];
`endif
 
`ifdef OC8051_TC2
      `OC8051_SFR_B_T2CON: bit_out <= t2con[adr0[2:0]];
`endif
 
      default:             bit_out <= 1'b0;
    endcase
end
 
always @(posedge clk or negedge resetn)
begin
  if (resetn == 1'b0) begin
    prescaler <= 4'h0;
    pres_ow <= 1'b0;
  end else if (prescaler==4'b1011) begin
    prescaler <= 4'h0;
    pres_ow <= 1'b1;
  end else begin
    prescaler <= prescaler + 4'h1;
    pres_ow <= 1'b0;
  end
end
 
endmodule

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[/] [oms8051mini/] [trunk/] [rtl/] [8051/] [oc8051_sfr.v] - Blame information for rev 36

Line No.	Rev	Author	Line
1	2	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 cores sfr top level module ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/oms8051mini/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// special function registers for oc8051 ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16			`//// - Dinesh Annayya, dinesha@opencores.org ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19	25	dinesha	`//// v0.0 - Dinesh A, 5th Jan 2017`
20			`//// 1. Active edge of reset changed from High to Low`
21	36	dinesha	`//// v0.1 - Dinesh A, 19th Jan 2017`
22			`//// 1. Lint Warning fixes`
23	25	dinesha	`//////////////////////////////////////////////////////////////////////`
24	2	dinesha	`//// ////`
25			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
26			`//// ////`
27			`//// This source file may be used and distributed without ////`
28			`//// restriction provided that this copyright statement is not ////`
29			`//// removed from the file and that any derivative work contains ////`
30			`//// the original copyright notice and the associated disclaimer. ////`
31			`//// ////`
32			`//// This source file is free software; you can redistribute it ////`
33			`//// and/or modify it under the terms of the GNU Lesser General ////`
34			`//// Public License as published by the Free Software Foundation; ////`
35			`//// either version 2.1 of the License, or (at your option) any ////`
36			`//// later version. ////`
37			`//// ////`
38			`//// This source is distributed in the hope that it will be ////`
39			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
40			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
41			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
42			`//// details. ////`
43			`//// ////`
44			`//// You should have received a copy of the GNU Lesser General ////`
45			`//// Public License along with this source; if not, download it ////`
46			`//// from http://www.opencores.org/lgpl.shtml ////`
47			`//// ////`
48			`//////////////////////////////////////////////////////////////////////`
49			`//`
50			`// CVS Revision History`
51			`//`
52			`// $Log: not supported by cvs2svn $`
53			`// Revision 1.14 2003/05/07 12:39:20 simont`
54			`// fix bug in case of sequence of inc dptr instrucitons.`
55			`//`
56			`// Revision 1.13 2003/05/05 15:46:37 simont`
57			`// add aditional alu destination to solve critical path.`
58			`//`
59			`// Revision 1.12 2003/04/29 11:24:31 simont`
60			`// fix bug in case execution of two data dependent instructions.`
61			`//`
62			`// Revision 1.11 2003/04/25 17:15:51 simont`
63			`// change branch instruction execution (reduse needed clock periods).`
64			`//`
65			`// Revision 1.10 2003/04/10 12:43:19 simont`
66			`// defines for pherypherals added`
67			`//`
68			`// Revision 1.9 2003/04/09 16:24:03 simont`
69			`// change wr_sft to 2 bit wire.`
70			`//`
71			`// Revision 1.8 2003/04/09 15:49:42 simont`
72			`// Register oc8051_sfr dato output, add signal wait_data.`
73			`//`
74			`// Revision 1.7 2003/04/07 14:58:02 simont`
75			`// change sfr's interface.`
76			`//`
77			`// Revision 1.6 2003/04/07 13:29:16 simont`
78			`// change uart to meet timing.`
79			`//`
80			`// Revision 1.5 2003/04/04 10:35:07 simont`
81			`// signal prsc_ow added.`
82			`//`
83			`// Revision 1.4 2003/03/28 17:45:57 simont`
84			`// change module name.`
85			`//`
86			`// Revision 1.3 2003/01/21 13:51:30 simont`
87			`// add include oc8051_defines.v`
88			`//`
89			`// Revision 1.2 2003/01/13 14:14:41 simont`
90			`// replace some modules`
91			`//`
92			`// Revision 1.1 2002/11/05 17:22:27 simont`
93			`// initial import`
94			`//`
95			`//`
96
97
98			`include "top_defines.v"
99
100
101	25	dinesha	`module oc8051_sfr (resetn, clk,`
102	2	dinesha	`adr0, adr1, dat0,`
103			`dat1, dat2, bit_in,`
104			`des_acc,`
105			`we, wr_bit,`
106			`bit_out,`
107			`wr_sfr, acc,`
108			`ram_wr_sel, ram_rd_sel,`
109			`sp, sp_w,`
110			`bank_sel,`
111			`desAc, desOv,`
112			`srcAc, cy,`
113			`psw_set, rmw,`
114			`comp_sel,`
115			`comp_wait,`
116
117			`ifdef OC8051_PORTS
118
119			`ifdef OC8051_PORT0
120			`p0_out,`
121			`p0_in,`
122			`endif
123
124			`ifdef OC8051_PORT1
125			`p1_out,`
126			`p1_in,`
127			`endif
128
129			`ifdef OC8051_PORT2
130			`p2_out,`
131			`p2_in,`
132			`endif
133
134			`ifdef OC8051_PORT3
135			`p3_out,`
136			`p3_in,`
137			`endif
138
139			`endif
140
141
142			`ifdef OC8051_UART
143			`rxd, txd,`
144			`endif
145
146			`int_ack, intr,`
147			`int0, int1,`
148			`int_src,`
149			`reti,`
150
151			`ifdef OC8051_TC01
152			`t0, t1,`
153			`endif
154
155			`ifdef OC8051_TC2
156			`t2, t2ex,`
157			`endif
158
159			`dptr_hi, dptr_lo,`
160			`wait_data);`
161
162
163	25	dinesha	`input resetn, // reset - pin`
164	2	dinesha	`clk, // clock - pin`
165			`we, // write enable`
166			`bit_in,`
167			`desAc,`
168			`desOv,`
169			`rmw;`
170			`input int_ack,`
171			`int0,`
172			`int1,`
173			`reti,`
174			`wr_bit;`
175			`input [1:0] psw_set,`
176			`wr_sfr,`
177			`comp_sel;`
178			`input [2:0] ram_rd_sel,`
179			`ram_wr_sel;`
180			`input [7:0] adr0, //address 0 input`
181			`adr1, //address 1 input`
182			`des_acc,`
183			`dat1, //data 1 input (des1)`
184			`dat2; //data 2 input (des2)`
185
186			`output bit_out,`
187			`intr,`
188			`srcAc,`
189			`cy,`
190			`wait_data,`
191			`comp_wait;`
192			`output [1:0] bank_sel;`
193			`output [7:0] dat0, //data output`
194			`int_src,`
195			`dptr_hi,`
196			`dptr_lo,`
197			`acc;`
198			`output [7:0] sp,`
199			`sp_w;`
200
201			`// ports`
202			`ifdef OC8051_PORTS
203
204			`ifdef OC8051_PORT0
205			`input [7:0] p0_in;`
206			`output [7:0] p0_out;`
207			`wire [7:0] p0_data;`
208			`endif
209
210			`ifdef OC8051_PORT1
211			`input [7:0] p1_in;`
212			`output [7:0] p1_out;`
213			`wire [7:0] p1_data;`
214			`endif
215
216			`ifdef OC8051_PORT2
217			`input [7:0] p2_in;`
218			`output [7:0] p2_out;`
219			`wire [7:0] p2_data;`
220			`endif
221
222			`ifdef OC8051_PORT3
223			`input [7:0] p3_in;`
224			`output [7:0] p3_out;`
225			`wire [7:0] p3_data;`
226			`endif
227
228			`endif
229
230
231			`// serial interface`
232			`ifdef OC8051_UART
233			`input rxd;`
234			`output txd;`
235			`endif
236
237			`// timer/counter 0,1`
238			`ifdef OC8051_TC01
239			`input t0, t1;`
240			`endif
241
242			`// timer/counter 2`
243			`ifdef OC8051_TC2
244			`input t2, t2ex;`
245			`endif
246
247			`reg bit_out,`
248			`wait_data;`
249			`reg [7:0] dat0,`
250			`adr0_r;`
251
252			`reg wr_bit_r;`
253			`reg [2:0] ram_wr_sel_r;`
254
255
256			`wire p,`
257			`uart_int,`
258			`tf0,`
259			`tf1,`
260			`tr0,`
261			`tr1,`
262			`rclk,`
263			`tclk,`
264			`brate2,`
265			`tc2_int;`
266
267
268			`wire [7:0] b_reg,`
269			`psw,`
270
271			`ifdef OC8051_TC2
272			`// t/c 2`
273			`t2con,`
274			`tl2,`
275			`th2,`
276			`rcap2l,`
277			`rcap2h,`
278			`endif
279
280			`ifdef OC8051_TC01
281			`// t/c 0,1`
282			`tmod,`
283			`tl0,`
284			`th0,`
285			`tl1,`
286			`th1,`
287			`endif
288
289			`// serial interface`
290			`ifdef OC8051_UART
291			`scon,`
292			`pcon,`
293			`sbuf,`
294			`endif
295
296			`//interrupt control`
297			`ie,`
298			`tcon,`
299			`ip;`
300
301
302			`reg pres_ow;`
303			`reg [3:0] prescaler;`
304
305
306			`assign cy = psw[7];`
307			`assign srcAc = psw [6];`
308
309
310
311			`//`
312			`// accumulator`
313			`// ACC`
314			`oc8051_acc oc8051_acc1(.clk(clk),`
315	25	dinesha	`.resetn(resetn),`
316	2	dinesha	`.bit_in(bit_in),`
317			`.data_in(des_acc),`
318			`.data2_in(dat2),`
319			`.wr(we),`
320			`.wr_bit(wr_bit_r),`
321			`.wr_sfr(wr_sfr),`
322			`.wr_addr(adr1),`
323			`.data_out(acc),`
324			`.p(p));`
325
326
327			`//`
328			`// b register`
329			`// B`
330			`oc8051_b_register oc8051_b_register (.clk(clk),`
331	25	dinesha	`.resetn(resetn),`
332	2	dinesha	`.bit_in(bit_in),`
333			`.data_in(des_acc),`
334			`.wr(we),`
335			`.wr_bit(wr_bit_r),`
336			`.wr_addr(adr1),`
337			`.data_out(b_reg));`
338
339			`//`
340			`//stack pointer`
341			`// SP`
342			`oc8051_sp oc8051_sp1(.clk(clk),`
343	25	dinesha	`.resetn(resetn),`
344	2	dinesha	`.ram_rd_sel(ram_rd_sel),`
345			`.ram_wr_sel(ram_wr_sel),`
346			`.wr_addr(adr1),`
347			`.wr(we),`
348			`.wr_bit(wr_bit_r),`
349			`.data_in(dat1),`
350			`.sp_out(sp),`
351			`.sp_w(sp_w));`
352
353			`//`
354			`//data pointer`
355			`// DPTR, DPH, DPL`
356			`oc8051_dptr oc8051_dptr1(.clk(clk),`
357	25	dinesha	`.resetn(resetn),`
358	2	dinesha	`.addr(adr1),`
359			`.data_in(des_acc),`
360			`.data2_in(dat2),`
361			`.wr(we),`
362			`.wr_bit(wr_bit_r),`
363			`.data_hi(dptr_hi),`
364			`.data_lo(dptr_lo),`
365			`.wr_sfr(wr_sfr));`
366
367
368			`//`
369			`//program status word`
370			`// PSW`
371			`oc8051_psw oc8051_psw1 (.clk(clk),`
372	25	dinesha	`.resetn(resetn),`
373	2	dinesha	`.wr_addr(adr1),`
374			`.data_in(dat1),`
375			`.wr(we),`
376			`.wr_bit(wr_bit_r),`
377			`.data_out(psw),`
378			`.p(p),`
379			`.cy_in(bit_in),`
380			`.ac_in(desAc),`
381			`.ov_in(desOv),`
382			`.set(psw_set),`
383			`.bank_sel(bank_sel));`
384
385			`//`
386			`// ports`
387			`// P0, P1, P2, P3`
388			`ifdef OC8051_PORTS
389			`oc8051_ports oc8051_ports1(.clk(clk),`
390	25	dinesha	`.resetn(resetn),`
391	2	dinesha	`.bit_in(bit_in),`
392			`.data_in(dat1),`
393			`.wr(we),`
394			`.wr_bit(wr_bit_r),`
395			`.wr_addr(adr1),`
396
397			`ifdef OC8051_PORT0
398			`.p0_out(p0_out),`
399			`.p0_in(p0_in),`
400			`.p0_data(p0_data),`
401			`endif
402
403			`ifdef OC8051_PORT1
404			`.p1_out(p1_out),`
405			`.p1_in(p1_in),`
406			`.p1_data(p1_data),`
407			`endif
408
409			`ifdef OC8051_PORT2
410			`.p2_out(p2_out),`
411			`.p2_in(p2_in),`
412			`.p2_data(p2_data),`
413			`endif
414
415			`ifdef OC8051_PORT3
416			`.p3_out(p3_out),`
417			`.p3_in(p3_in),`
418			`.p3_data(p3_data),`
419			`endif
420
421			`.rmw(rmw));`
422			`endif
423
424			`//`
425			`// serial interface`
426			`// SCON, SBUF`
427			`ifdef OC8051_UART
428			`oc8051_uart oc8051_uatr1 (.clk(clk),`
429	25	dinesha	`.resetn(resetn),`
430	2	dinesha	`.bit_in(bit_in),`
431			`.data_in(dat1),`
432			`.wr(we),`
433			`.wr_bit(wr_bit_r),`
434			`.wr_addr(adr1),`
435			`.rxd(rxd),`
436			`.txd(txd),`
437			`// interrupt`
438			`.intr(uart_int),`
439			`// baud rate sources`
440			`.brate2(brate2),`
441			`.t1_ow(tf1),`
442			`.pres_ow(pres_ow),`
443			`.rclk(rclk),`
444			`.tclk(tclk),`
445			`//registers`
446			`.scon(scon),`
447			`.pcon(pcon),`
448			`.sbuf(sbuf));`
449			`else
450			`assign uart_int = 1'b0;`
451			`endif
452
453			`//`
454			`// interrupt control`
455			`// IP, IE, TCON`
456			`oc8051_int oc8051_int1 (.clk(clk),`
457	25	dinesha	`.resetn(resetn),`
458	2	dinesha	`.wr_addr(adr1),`
459			`.bit_in(bit_in),`
460			`.ack(int_ack),`
461			`.data_in(dat1),`
462			`.wr(we),`
463			`.wr_bit(wr_bit_r),`
464			`.tf0(tf0),`
465			`.tf1(tf1),`
466			`.t2_int(tc2_int),`
467			`.tr0(tr0),`
468			`.tr1(tr1),`
469			`.ie0(int0),`
470			`.ie1(int1),`
471			`.uart_int(uart_int),`
472			`.reti(reti),`
473			`.intr(intr),`
474			`.int_vec(int_src),`
475			`.ie(ie),`
476			`.tcon(tcon),`
477			`.ip(ip));`
478
479
480			`//`
481			`// timer/counter control`
482			`// TH0, TH1, TL0, TH1, TMOD`
483			`ifdef OC8051_TC01
484			`oc8051_tc oc8051_tc1(.clk(clk),`
485	25	dinesha	`.resetn(resetn),`
486	2	dinesha	`.wr_addr(adr1),`
487			`.data_in(dat1),`
488			`.wr(we),`
489			`.wr_bit(wr_bit_r),`
490			`.ie0(int0),`
491			`.ie1(int1),`
492			`.tr0(tr0),`
493			`.tr1(tr1),`
494			`.t0(t0),`
495			`.t1(t1),`
496			`.tf0(tf0),`
497			`.tf1(tf1),`
498			`.pres_ow(pres_ow),`
499			`.tmod(tmod),`
500			`.tl0(tl0),`
501			`.th0(th0),`
502			`.tl1(tl1),`
503			`.th1(th1));`
504			`else
505			`assign tf0 = 1'b0;`
506			`assign tf1 = 1'b0;`
507			`endif
508
509			`//`
510			`// timer/counter 2`
511			`// TH2, TL2, RCAPL2L, RCAPL2H, T2CON`
512			`ifdef OC8051_TC2
513			`oc8051_tc2 oc8051_tc21(.clk(clk),`
514	25	dinesha	`.resetn(resetn),`
515	2	dinesha	`.wr_addr(adr1),`
516			`.data_in(dat1),`
517			`.wr(we),`
518			`.wr_bit(wr_bit_r),`
519			`.bit_in(bit_in),`
520			`.t2(t2),`
521			`.t2ex(t2ex),`
522			`.rclk(rclk),`
523			`.tclk(tclk),`
524			`.brate2(brate2),`
525			`.tc2_int(tc2_int),`
526			`.pres_ow(pres_ow),`
527			`.t2con(t2con),`
528			`.tl2(tl2),`
529			`.th2(th2),`
530			`.rcap2l(rcap2l),`
531			`.rcap2h(rcap2h));`
532			`else
533			`assign tc2_int = 1'b0;`
534			`assign rclk = 1'b0;`
535			`assign tclk = 1'b0;`
536			`assign brate2 = 1'b0;`
537			`endif
538
539
540
541	25	dinesha	`always @(posedge clk or negedge resetn)`
542			`if (resetn == 1'b0) begin`
543	36	dinesha	`adr0_r <= 8'h00;`
544			`ram_wr_sel_r <= 3'b000;`
545			`wr_bit_r <= 1'b0;`
546			`// wait_data <= 1'b0;`
547	2	dinesha	`end else begin`
548	36	dinesha	`adr0_r <= adr0;`
549			`ram_wr_sel_r <= ram_wr_sel;`
550			`wr_bit_r <= wr_bit;`
551	2	dinesha	`end`
552
553			`assign comp_wait = !(`
554			((comp_sel==`OC8051_CSS_AZ) &
555			((wr_sfr==`OC8051_WRS_ACC1) \|
556			(wr_sfr==`OC8051_WRS_ACC2) \|
557			((adr1==`OC8051_SFR_ACC) & we & !wr_bit_r) \|
558			((adr1[7:3]==`OC8051_SFR_B_ACC) & we & wr_bit_r))) \|
559			((comp_sel==`OC8051_CSS_CY) &
560			`((\|psw_set) \|`
561			((adr1==`OC8051_SFR_PSW) & we & !wr_bit_r) \|
562			((adr1[7:3]==`OC8051_SFR_B_PSW) & we & wr_bit_r))) \|
563			((comp_sel==`OC8051_CSS_BIT) &
564			`((adr1[7:3]==adr0[7:3]) & (~&adr1[2:0]) & we & !wr_bit_r) \|`
565			`((adr1==adr0) & adr1[7] & we & !wr_bit_r)));`
566
567
568
569			`//`
570			`//set output in case of address (byte)`
571	25	dinesha	`always @(posedge clk or negedge resetn)`
572	2	dinesha	`begin`
573	25	dinesha	`if (resetn == 1'b0) begin`
574	36	dinesha	`dat0 <= 8'h00;`
575			`wait_data <= 1'b0;`
576	2	dinesha	end else if ((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) begin //write and read same address
577	36	dinesha	`dat0 <= des_acc;`
578			`wait_data <= 1'b0;`
579	2	dinesha	`end else if (`
580			`(`
581			((wr_sfr==`OC8051_WRS_ACC1) & (adr0==`OC8051_SFR_ACC)) \| //write to acc
582			// ((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) \| //write to dpl
583			`(adr1[7] & (adr1==adr0) & we & !wr_bit_r) \| //write and read same address`
584			`(adr1[7] & (adr1[7:3]==adr0[7:3]) & (~&adr0[2:0]) & we & wr_bit_r) //write bit addressable to read address`
585			`) & !wait_data) begin`
586	36	dinesha	`wait_data <= 1'b1;`
587	2	dinesha
588			`end else if ((`
589			((\|psw_set) & (adr0==`OC8051_SFR_PSW)) \|
590			((wr_sfr==`OC8051_WRS_ACC2) & (adr0==`OC8051_SFR_ACC)) \| //write to acc
591			((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_HI)) //write to dph
592			`) & !wait_data) begin`
593	36	dinesha	`wait_data <= 1'b1;`
594	2	dinesha
595			`end else begin`
596			`case (adr0) /* synopsys full_case parallel_case */`
597	36	dinesha	`OC8051_SFR_ACC: dat0 <= acc;
598			`OC8051_SFR_PSW: dat0 <= psw;
599	2	dinesha
600			`ifdef OC8051_PORTS
601			`ifdef OC8051_PORT0
602	36	dinesha	`OC8051_SFR_P0: dat0 <= p0_data;
603	2	dinesha	`endif
604
605			`ifdef OC8051_PORT1
606	36	dinesha	`OC8051_SFR_P1: dat0 <= p1_data;
607	2	dinesha	`endif
608
609			`ifdef OC8051_PORT2
610	36	dinesha	`OC8051_SFR_P2: dat0 <= p2_data;
611	2	dinesha	`endif
612
613			`ifdef OC8051_PORT3
614	36	dinesha	`OC8051_SFR_P3: dat0 <= p3_data;
615	2	dinesha	`endif
616			`endif
617
618	36	dinesha	`OC8051_SFR_SP: dat0 <= sp;
619			`OC8051_SFR_B: dat0 <= b_reg;
620			`OC8051_SFR_DPTR_HI: dat0 <= dptr_hi;
621			`OC8051_SFR_DPTR_LO: dat0 <= dptr_lo;
622	2	dinesha
623			`ifdef OC8051_UART
624	36	dinesha	`OC8051_SFR_SCON: dat0 <= scon;
625			`OC8051_SFR_SBUF: dat0 <= sbuf;
626			`OC8051_SFR_PCON: dat0 <= pcon;
627	2	dinesha	`endif
628
629			`ifdef OC8051_TC01
630	36	dinesha	`OC8051_SFR_TH0: dat0 <= th0;
631			`OC8051_SFR_TH1: dat0 <= th1;
632			`OC8051_SFR_TL0: dat0 <= tl0;
633			`OC8051_SFR_TL1: dat0 <= tl1;
634			`OC8051_SFR_TMOD: dat0 <= tmod;
635	2	dinesha	`endif
636
637	36	dinesha	`OC8051_SFR_IP: dat0 <= ip;
638			`OC8051_SFR_IE: dat0 <= ie;
639			`OC8051_SFR_TCON: dat0 <= tcon;
640	2	dinesha
641			`ifdef OC8051_TC2
642	36	dinesha	`OC8051_SFR_RCAP2H: dat0 <= rcap2h;
643			`OC8051_SFR_RCAP2L: dat0 <= rcap2l;
644			`OC8051_SFR_TH2: dat0 <= th2;
645			`OC8051_SFR_TL2: dat0 <= tl2;
646			`OC8051_SFR_T2CON: dat0 <= t2con;
647	2	dinesha	`endif
648
649	36	dinesha	`default: dat0 <= 8'h00;`
650	2	dinesha	`endcase`
651	36	dinesha	`wait_data <= 1'b0;`
652	2	dinesha	`end`
653			`end`
654
655
656			`//`
657			`//set output in case of address (bit)`
658
659	25	dinesha	`always @(posedge clk or negedge resetn)`
660	2	dinesha	`begin`
661	25	dinesha	`if (resetn == 1'b0)`
662	36	dinesha	`bit_out <= 1'h0;`
663	2	dinesha	`else if (`
664			`((adr1[7:3]==adr0[7:3]) & (~&adr1[2:0]) & we & !wr_bit_r) \|`
665			((wr_sfr==`OC8051_WRS_ACC1) & (adr0[7:3]==`OC8051_SFR_B_ACC)) //write to acc
666			`)`
667
668	36	dinesha	`bit_out <= dat1[adr0[2:0]];`
669	2	dinesha	`else if ((adr1==adr0) & we & wr_bit_r)`
670	36	dinesha	`bit_out <= bit_in;`
671	2	dinesha	`else`
672			`case (adr0[7:3]) /* synopsys full_case parallel_case */`
673	36	dinesha	`OC8051_SFR_B_ACC: bit_out <= acc[adr0[2:0]];
674			`OC8051_SFR_B_PSW: bit_out <= psw[adr0[2:0]];
675	2	dinesha
676			`ifdef OC8051_PORTS
677			`ifdef OC8051_PORT0
678	36	dinesha	`OC8051_SFR_B_P0: bit_out <= p0_data[adr0[2:0]];
679	2	dinesha	`endif
680
681			`ifdef OC8051_PORT1
682	36	dinesha	`OC8051_SFR_B_P1: bit_out <= p1_data[adr0[2:0]];
683	2	dinesha	`endif
684
685			`ifdef OC8051_PORT2
686	36	dinesha	`OC8051_SFR_B_P2: bit_out <= p2_data[adr0[2:0]];
687	2	dinesha	`endif
688
689			`ifdef OC8051_PORT3
690	36	dinesha	`OC8051_SFR_B_P3: bit_out <= p3_data[adr0[2:0]];
691	2	dinesha	`endif
692			`endif
693
694	36	dinesha	`OC8051_SFR_B_B: bit_out <= b_reg[adr0[2:0]];
695			`OC8051_SFR_B_IP: bit_out <= ip[adr0[2:0]];
696			`OC8051_SFR_B_IE: bit_out <= ie[adr0[2:0]];
697			`OC8051_SFR_B_TCON: bit_out <= tcon[adr0[2:0]];
698	2	dinesha
699			`ifdef OC8051_UART
700	36	dinesha	`OC8051_SFR_B_SCON: bit_out <= scon[adr0[2:0]];
701	2	dinesha	`endif
702
703			`ifdef OC8051_TC2
704	36	dinesha	`OC8051_SFR_B_T2CON: bit_out <= t2con[adr0[2:0]];
705	2	dinesha	`endif
706
707	36	dinesha	`default: bit_out <= 1'b0;`
708	2	dinesha	`endcase`
709			`end`
710
711	25	dinesha	`always @(posedge clk or negedge resetn)`
712	2	dinesha	`begin`
713	25	dinesha	`if (resetn == 1'b0) begin`
714	36	dinesha	`prescaler <= 4'h0;`
715			`pres_ow <= 1'b0;`
716	2	dinesha	`end else if (prescaler==4'b1011) begin`
717	36	dinesha	`prescaler <= 4'h0;`
718			`pres_ow <= 1'b1;`
719	2	dinesha	`end else begin`
720	36	dinesha	`prescaler <= prescaler + 4'h1;`
721			`pres_ow <= 1'b0;`
722	2	dinesha	`end`
723			`end`
724
725			`endmodule`