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[/] [oms8051mini/] [trunk/] [rtl/] [8051/] [oc8051_tc.v] - Blame information for rev 2

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 cores timer/counter control                            ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/oms8051mini/                 ////
////                                                              ////
////  Description                                                 ////
////   timers and counters handling for 8051 core                 ////
////                                                              ////
////  To Do:                                                      ////
////   Nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8  2003/04/10 12:43:19  simont
// defines for pherypherals added
//
// Revision 1.7  2003/04/07 14:58:02  simont
// change sfr's interface.
//
// Revision 1.6  2003/04/04 10:34:13  simont
// change timers to meet timing specifications (add divider with 12)
//
// Revision 1.5  2003/01/13 14:14:41  simont
// replace some modules
//
// Revision 1.4  2002/09/30 17:33:59  simont
// prepared header
//
//
 
`include "top_defines.v"
 
 
 
module oc8051_tc (clk, rst,
            data_in,
            wr_addr,
            wr, wr_bit,
            ie0, ie1,
            tr0, tr1,
            t0, t1,
            tf0, tf1,
            pres_ow,
//registers
            tmod, tl0, th0, tl1, th1);
 
input [7:0]  wr_addr,
             data_in;
input        clk,
             rst,
             wr,
             wr_bit,
             ie0,
             ie1,
             tr0,
             tr1,
             t0,
             t1,
             pres_ow;
output [7:0] tmod,
             tl0,
             th0,
             tl1,
             th1;
output       tf0,
             tf1;
 
 
reg [7:0] tmod, tl0, th0, tl1, th1;
reg tf0, tf1_0, tf1_1, t0_buff, t1_buff;
 
wire tc0_add, tc1_add;
 
assign tc0_add = (tr0 & (!tmod[3] | !ie0) & ((!tmod[2] & pres_ow) | (tmod[2] & !t0 & t0_buff)));
assign tc1_add = (tr1 & (!tmod[7] | !ie1) & ((!tmod[6] & pres_ow) | (tmod[6] & !t1 & t1_buff)));
assign tf1= tf1_0 | tf1_1;
 
//
// read or write from one of the addresses in tmod
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   tmod <=#1 `OC8051_RST_TMOD;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TMOD))
    tmod <= #1 data_in;
end
 
//
// TIMER COUNTER 0
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   tl0 <=#1 `OC8051_RST_TL0;
   th0 <=#1 `OC8051_RST_TH0;
   tf0 <= #1 1'b0;
   tf1_0 <= #1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL0)) begin
   tl0 <= #1 data_in;
   tf0 <= #1 1'b0;
   tf1_0 <= #1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH0)) begin
   th0 <= #1 data_in;
   tf0 <= #1 1'b0;
   tf1_0 <= #1 1'b0;
 end else begin
     case (tmod[1:0]) /* synopsys full_case parallel_case */
      `OC8051_MODE0: begin                       // mode 0
        tf1_0 <= #1 1'b0;
        if (tc0_add)
          {tf0, th0,tl0[4:0]} <= #1 {1'b0, th0, tl0[4:0]}+ 1'b1;
      end
      `OC8051_MODE1: begin                       // mode 1
        tf1_0 <= #1 1'b0;
        if (tc0_add)
          {tf0, th0,tl0} <= #1 {1'b0, th0, tl0}+ 1'b1;
      end
 
      `OC8051_MODE2: begin                       // mode 2
        tf1_0 <= #1 1'b0;
        if (tc0_add) begin
          if (tl0 == 8'b1111_1111) begin
            tf0 <=#1 1'b1;
            tl0 <=#1 th0;
           end
          else begin
            tl0 <=#1 tl0 + 8'h1;
            tf0 <= #1 1'b0;
          end
        end
      end
      `OC8051_MODE3: begin                       // mode 3
 
         if (tc0_add)
           {tf0, tl0} <= #1 {1'b0, tl0} +1'b1;
 
         if (tr1 & pres_ow)
           {tf1_0, th0} <= #1 {1'b0, th0} +1'b1;
 
      end
/*      default:begin
        tf0 <= #1 1'b0;
        tf1_0 <= #1 1'b0;
      end*/
    endcase
 end
end
 
//
// TIMER COUNTER 1
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   tl1 <=#1 `OC8051_RST_TL1;
   th1 <=#1 `OC8051_RST_TH1;
   tf1_1 <= #1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL1)) begin
   tl1 <= #1 data_in;
   tf1_1 <= #1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH1)) begin
   th1 <= #1 data_in;
   tf1_1 <= #1 1'b0;
 end else begin
     case (tmod[5:4]) /* synopsys full_case parallel_case */
      `OC8051_MODE0: begin                       // mode 0
        if (tc1_add)
          {tf1_1, th1,tl1[4:0]} <= #1 {1'b0, th1, tl1[4:0]}+ 1'b1;
      end
      `OC8051_MODE1: begin                       // mode 1
        if (tc1_add)
          {tf1_1, th1,tl1} <= #1 {1'b0, th1, tl1}+ 1'b1;
      end
 
      `OC8051_MODE2: begin                       // mode 2
        if (tc1_add) begin
          if (tl1 == 8'b1111_1111) begin
            tf1_1 <=#1 1'b1;
            tl1 <=#1 th1;
           end
          else begin
            tl1 <=#1 tl1 + 8'h1;
            tf1_1 <= #1 1'b0;
          end
        end
      end
/*      default:begin
        tf1_1 <= #1 1'b0;
      end*/
    endcase
 end
end
 
 
always @(posedge clk or posedge rst)
  if (rst) begin
    t0_buff <= #1 1'b0;
    t1_buff <= #1 1'b0;
  end else begin
    t0_buff <= #1 t0;
    t1_buff <= #1 t1;
  end
endmodule

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[/] [oms8051mini/] [trunk/] [rtl/] [8051/] [oc8051_tc.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 cores timer/counter control ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/oms8051mini/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// timers and counters handling for 8051 core ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// Nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16			`//// - Dinesh Annayya, dinesha@opencores.org ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48			`// Revision 1.8 2003/04/10 12:43:19 simont`
49			`// defines for pherypherals added`
50			`//`
51			`// Revision 1.7 2003/04/07 14:58:02 simont`
52			`// change sfr's interface.`
53			`//`
54			`// Revision 1.6 2003/04/04 10:34:13 simont`
55			`// change timers to meet timing specifications (add divider with 12)`
56			`//`
57			`// Revision 1.5 2003/01/13 14:14:41 simont`
58			`// replace some modules`
59			`//`
60			`// Revision 1.4 2002/09/30 17:33:59 simont`
61			`// prepared header`
62			`//`
63			`//`
64
65			`include "top_defines.v"
66
67
68
69			`module oc8051_tc (clk, rst,`
70			`data_in,`
71			`wr_addr,`
72			`wr, wr_bit,`
73			`ie0, ie1,`
74			`tr0, tr1,`
75			`t0, t1,`
76			`tf0, tf1,`
77			`pres_ow,`
78			`//registers`
79			`tmod, tl0, th0, tl1, th1);`
80
81			`input [7:0] wr_addr,`
82			`data_in;`
83			`input clk,`
84			`rst,`
85			`wr,`
86			`wr_bit,`
87			`ie0,`
88			`ie1,`
89			`tr0,`
90			`tr1,`
91			`t0,`
92			`t1,`
93			`pres_ow;`
94			`output [7:0] tmod,`
95			`tl0,`
96			`th0,`
97			`tl1,`
98			`th1;`
99			`output tf0,`
100			`tf1;`
101
102
103			`reg [7:0] tmod, tl0, th0, tl1, th1;`
104			`reg tf0, tf1_0, tf1_1, t0_buff, t1_buff;`
105
106			`wire tc0_add, tc1_add;`
107
108			`assign tc0_add = (tr0 & (!tmod[3] \| !ie0) & ((!tmod[2] & pres_ow) \| (tmod[2] & !t0 & t0_buff)));`
109			`assign tc1_add = (tr1 & (!tmod[7] \| !ie1) & ((!tmod[6] & pres_ow) \| (tmod[6] & !t1 & t1_buff)));`
110			`assign tf1= tf1_0 \| tf1_1;`
111
112			`//`
113			`// read or write from one of the addresses in tmod`
114			`//`
115			`always @(posedge clk or posedge rst)`
116			`begin`
117			`if (rst) begin`
118			tmod <=#1 `OC8051_RST_TMOD;
119			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TMOD))
120			`tmod <= #1 data_in;`
121			`end`
122
123			`//`
124			`// TIMER COUNTER 0`
125			`//`
126			`always @(posedge clk or posedge rst)`
127			`begin`
128			`if (rst) begin`
129			tl0 <=#1 `OC8051_RST_TL0;
130			th0 <=#1 `OC8051_RST_TH0;
131			`tf0 <= #1 1'b0;`
132			`tf1_0 <= #1 1'b0;`
133			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL0)) begin
134			`tl0 <= #1 data_in;`
135			`tf0 <= #1 1'b0;`
136			`tf1_0 <= #1 1'b0;`
137			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH0)) begin
138			`th0 <= #1 data_in;`
139			`tf0 <= #1 1'b0;`
140			`tf1_0 <= #1 1'b0;`
141			`end else begin`
142			`case (tmod[1:0]) /* synopsys full_case parallel_case */`
143			`OC8051_MODE0: begin // mode 0
144			`tf1_0 <= #1 1'b0;`
145			`if (tc0_add)`
146			`{tf0, th0,tl0[4:0]} <= #1 {1'b0, th0, tl0[4:0]}+ 1'b1;`
147			`end`
148			`OC8051_MODE1: begin // mode 1
149			`tf1_0 <= #1 1'b0;`
150			`if (tc0_add)`
151			`{tf0, th0,tl0} <= #1 {1'b0, th0, tl0}+ 1'b1;`
152			`end`
153
154			`OC8051_MODE2: begin // mode 2
155			`tf1_0 <= #1 1'b0;`
156			`if (tc0_add) begin`
157			`if (tl0 == 8'b1111_1111) begin`
158			`tf0 <=#1 1'b1;`
159			`tl0 <=#1 th0;`
160			`end`
161			`else begin`
162			`tl0 <=#1 tl0 + 8'h1;`
163			`tf0 <= #1 1'b0;`
164			`end`
165			`end`
166			`end`
167			`OC8051_MODE3: begin // mode 3
168
169			`if (tc0_add)`
170			`{tf0, tl0} <= #1 {1'b0, tl0} +1'b1;`
171
172			`if (tr1 & pres_ow)`
173			`{tf1_0, th0} <= #1 {1'b0, th0} +1'b1;`
174
175			`end`
176			`/* default:begin`
177			`tf0 <= #1 1'b0;`
178			`tf1_0 <= #1 1'b0;`
179			`end*/`
180			`endcase`
181			`end`
182			`end`
183
184			`//`
185			`// TIMER COUNTER 1`
186			`//`
187			`always @(posedge clk or posedge rst)`
188			`begin`
189			`if (rst) begin`
190			tl1 <=#1 `OC8051_RST_TL1;
191			th1 <=#1 `OC8051_RST_TH1;
192			`tf1_1 <= #1 1'b0;`
193			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL1)) begin
194			`tl1 <= #1 data_in;`
195			`tf1_1 <= #1 1'b0;`
196			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH1)) begin
197			`th1 <= #1 data_in;`
198			`tf1_1 <= #1 1'b0;`
199			`end else begin`
200			`case (tmod[5:4]) /* synopsys full_case parallel_case */`
201			`OC8051_MODE0: begin // mode 0
202			`if (tc1_add)`
203			`{tf1_1, th1,tl1[4:0]} <= #1 {1'b0, th1, tl1[4:0]}+ 1'b1;`
204			`end`
205			`OC8051_MODE1: begin // mode 1
206			`if (tc1_add)`
207			`{tf1_1, th1,tl1} <= #1 {1'b0, th1, tl1}+ 1'b1;`
208			`end`
209
210			`OC8051_MODE2: begin // mode 2
211			`if (tc1_add) begin`
212			`if (tl1 == 8'b1111_1111) begin`
213			`tf1_1 <=#1 1'b1;`
214			`tl1 <=#1 th1;`
215			`end`
216			`else begin`
217			`tl1 <=#1 tl1 + 8'h1;`
218			`tf1_1 <= #1 1'b0;`
219			`end`
220			`end`
221			`end`
222			`/* default:begin`
223			`tf1_1 <= #1 1'b0;`
224			`end*/`
225			`endcase`
226			`end`
227			`end`
228
229
230			`always @(posedge clk or posedge rst)`
231			`if (rst) begin`
232			`t0_buff <= #1 1'b0;`
233			`t1_buff <= #1 1'b0;`
234			`end else begin`
235			`t0_buff <= #1 t0;`
236			`t1_buff <= #1 t1;`
237			`end`
238			`endmodule`