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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 cores timer/counter control                            ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/oms8051mini/                 ////
////                                                              ////
////  Description                                                 ////
////   timers and counters handling for 8051 core                 ////
////                                                              ////
////  To Do:                                                      ////
////   Nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////   v0.0 - Dinesh A, 5th Jan 2017
////        1. Active edge of reset changed from High to Low
////   v0.1 - Dinesh A, 19th Jan 2017
////        1. Lint Warning fixes
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8  2003/04/10 12:43:19  simont
// defines for pherypherals added
//
// Revision 1.7  2003/04/07 14:58:02  simont
// change sfr's interface.
//
// Revision 1.6  2003/04/04 10:34:13  simont
// change timers to meet timing specifications (add divider with 12)
//
// Revision 1.5  2003/01/13 14:14:41  simont
// replace some modules
//
// Revision 1.4  2002/09/30 17:33:59  simont
// prepared header
//
//
 
`include "top_defines.v"
 
 
 
module oc8051_tc (clk, resetn,
            data_in,
            wr_addr,
            wr, wr_bit,
            ie0, ie1,
            tr0, tr1,
            t0, t1,
            tf0, tf1,
            pres_ow,
//registers
            tmod, tl0, th0, tl1, th1);
 
input [7:0]  wr_addr,
             data_in;
input        clk,
             resetn,
             wr,
             wr_bit,
             ie0,
             ie1,
             tr0,
             tr1,
             t0,
             t1,
             pres_ow;
output [7:0] tmod,
             tl0,
             th0,
             tl1,
             th1;
output       tf0,
             tf1;
 
 
reg [7:0] tmod, tl0, th0, tl1, th1;
reg tf0, tf1_0, tf1_1, t0_buff, t1_buff;
 
wire tc0_add, tc1_add;
 
assign tc0_add = (tr0 & (!tmod[3] | !ie0) & ((!tmod[2] & pres_ow) | (tmod[2] & !t0 & t0_buff)));
assign tc1_add = (tr1 & (!tmod[7] | !ie1) & ((!tmod[6] & pres_ow) | (tmod[6] & !t1 & t1_buff)));
assign tf1= tf1_0 | tf1_1;
 
//
// read or write from one of the addresses in tmod
//
always @(posedge clk or negedge resetn)
begin
 if (resetn == 1'b0) begin
   tmod <=`OC8051_RST_TMOD;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TMOD))
    tmod <= data_in;
end
 
//
// TIMER COUNTER 0
//
always @(posedge clk or negedge resetn)
begin
 if (resetn == 1'b0) begin
   tl0 <=`OC8051_RST_TL0;
   th0 <=`OC8051_RST_TH0;
   tf0 <= 1'b0;
   tf1_0 <= 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL0)) begin
   tl0 <= data_in;
   tf0 <= 1'b0;
   tf1_0 <= 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH0)) begin
   th0 <= data_in;
   tf0 <= 1'b0;
   tf1_0 <= 1'b0;
 end else begin
     case (tmod[1:0]) /* synopsys full_case parallel_case */
      `OC8051_MODE0: begin                       // mode 0
        tf1_0 <= 1'b0;
        if (tc0_add)
          {tf0, th0,tl0[4:0]} <= {1'b0, th0, tl0[4:0]}+ 1'b1;
      end
      `OC8051_MODE1: begin                       // mode 1
        tf1_0 <= 1'b0;
        if (tc0_add)
          {tf0, th0,tl0} <= {1'b0, th0, tl0}+ 1'b1;
      end
 
      `OC8051_MODE2: begin                       // mode 2
        tf1_0 <= 1'b0;
        if (tc0_add) begin
          if (tl0 == 8'b1111_1111) begin
            tf0 <=1'b1;
            tl0 <=th0;
           end
          else begin
            tl0 <=tl0 + 8'h1;
            tf0 <= 1'b0;
          end
        end
      end
      `OC8051_MODE3: begin                       // mode 3
 
         if (tc0_add)
           {tf0, tl0} <= {1'b0, tl0} +1'b1;
 
         if (tr1 & pres_ow)
           {tf1_0, th0} <= {1'b0, th0} +1'b1;
 
      end
/*      default:begin
        tf0 <= 1'b0;
        tf1_0 <= 1'b0;
      end*/
    endcase
 end
end
 
//
// TIMER COUNTER 1
//
always @(posedge clk or negedge resetn)
begin
 if (resetn == 1'b0) begin
   tl1 <=`OC8051_RST_TL1;
   th1 <=`OC8051_RST_TH1;
   tf1_1 <= 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL1)) begin
   tl1 <= data_in;
   tf1_1 <= 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH1)) begin
   th1 <= data_in;
   tf1_1 <= 1'b0;
 end else begin
     case (tmod[5:4]) /* synopsys full_case parallel_case */
      `OC8051_MODE0: begin                       // mode 0
        if (tc1_add)
          {tf1_1, th1,tl1[4:0]} <= {1'b0, th1, tl1[4:0]}+ 1'b1;
      end
      `OC8051_MODE1: begin                       // mode 1
        if (tc1_add)
          {tf1_1, th1,tl1} <= {1'b0, th1, tl1}+ 1'b1;
      end
 
      `OC8051_MODE2: begin                       // mode 2
        if (tc1_add) begin
          if (tl1 == 8'b1111_1111) begin
            tf1_1 <=1'b1;
            tl1 <=th1;
           end
          else begin
            tl1 <=tl1 + 8'h1;
            tf1_1 <= 1'b0;
          end
        end
      end
      default:begin
        tf1_1 <= 1'b0;
      end
    endcase
 end
end
 
 
always @(posedge clk or negedge resetn)
  if (resetn == 1'b0) begin
    t0_buff <= 1'b0;
    t1_buff <= 1'b0;
  end else begin
    t0_buff <= t0;
    t1_buff <= t1;
  end
endmodule

Line No.	Rev	Author	Line
1	2	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 cores timer/counter control ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/oms8051mini/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// timers and counters handling for 8051 core ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// Nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16			`//// - Dinesh Annayya, dinesha@opencores.org ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19	25	dinesha	`//// v0.0 - Dinesh A, 5th Jan 2017`
20			`//// 1. Active edge of reset changed from High to Low`
21	36	dinesha	`//// v0.1 - Dinesh A, 19th Jan 2017`
22			`//// 1. Lint Warning fixes`
23	25	dinesha	`//////////////////////////////////////////////////////////////////////`
24	2	dinesha	`//// ////`
25			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
26			`//// ////`
27			`//// This source file may be used and distributed without ////`
28			`//// restriction provided that this copyright statement is not ////`
29			`//// removed from the file and that any derivative work contains ////`
30			`//// the original copyright notice and the associated disclaimer. ////`
31			`//// ////`
32			`//// This source file is free software; you can redistribute it ////`
33			`//// and/or modify it under the terms of the GNU Lesser General ////`
34			`//// Public License as published by the Free Software Foundation; ////`
35			`//// either version 2.1 of the License, or (at your option) any ////`
36			`//// later version. ////`
37			`//// ////`
38			`//// This source is distributed in the hope that it will be ////`
39			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
40			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
41			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
42			`//// details. ////`
43			`//// ////`
44			`//// You should have received a copy of the GNU Lesser General ////`
45			`//// Public License along with this source; if not, download it ////`
46			`//// from http://www.opencores.org/lgpl.shtml ////`
47			`//// ////`
48			`//////////////////////////////////////////////////////////////////////`
49			`//`
50			`// CVS Revision History`
51			`//`
52			`// $Log: not supported by cvs2svn $`
53			`// Revision 1.8 2003/04/10 12:43:19 simont`
54			`// defines for pherypherals added`
55			`//`
56			`// Revision 1.7 2003/04/07 14:58:02 simont`
57			`// change sfr's interface.`
58			`//`
59			`// Revision 1.6 2003/04/04 10:34:13 simont`
60			`// change timers to meet timing specifications (add divider with 12)`
61			`//`
62			`// Revision 1.5 2003/01/13 14:14:41 simont`
63			`// replace some modules`
64			`//`
65			`// Revision 1.4 2002/09/30 17:33:59 simont`
66			`// prepared header`
67			`//`
68			`//`
69
70			`include "top_defines.v"
71
72
73
74	25	dinesha	`module oc8051_tc (clk, resetn,`
75	2	dinesha	`data_in,`
76			`wr_addr,`
77			`wr, wr_bit,`
78			`ie0, ie1,`
79			`tr0, tr1,`
80			`t0, t1,`
81			`tf0, tf1,`
82			`pres_ow,`
83			`//registers`
84			`tmod, tl0, th0, tl1, th1);`
85
86			`input [7:0] wr_addr,`
87			`data_in;`
88			`input clk,`
89	25	dinesha	`resetn,`
90	2	dinesha	`wr,`
91			`wr_bit,`
92			`ie0,`
93			`ie1,`
94			`tr0,`
95			`tr1,`
96			`t0,`
97			`t1,`
98			`pres_ow;`
99			`output [7:0] tmod,`
100			`tl0,`
101			`th0,`
102			`tl1,`
103			`th1;`
104			`output tf0,`
105			`tf1;`
106
107
108			`reg [7:0] tmod, tl0, th0, tl1, th1;`
109			`reg tf0, tf1_0, tf1_1, t0_buff, t1_buff;`
110
111			`wire tc0_add, tc1_add;`
112
113			`assign tc0_add = (tr0 & (!tmod[3] \| !ie0) & ((!tmod[2] & pres_ow) \| (tmod[2] & !t0 & t0_buff)));`
114			`assign tc1_add = (tr1 & (!tmod[7] \| !ie1) & ((!tmod[6] & pres_ow) \| (tmod[6] & !t1 & t1_buff)));`
115			`assign tf1= tf1_0 \| tf1_1;`
116
117			`//`
118			`// read or write from one of the addresses in tmod`
119			`//`
120	25	dinesha	`always @(posedge clk or negedge resetn)`
121	2	dinesha	`begin`
122	25	dinesha	`if (resetn == 1'b0) begin`
123	36	dinesha	tmod <=`OC8051_RST_TMOD;
124	2	dinesha	end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TMOD))
125	36	dinesha	`tmod <= data_in;`
126	2	dinesha	`end`
127
128			`//`
129			`// TIMER COUNTER 0`
130			`//`
131	25	dinesha	`always @(posedge clk or negedge resetn)`
132	2	dinesha	`begin`
133	25	dinesha	`if (resetn == 1'b0) begin`
134	36	dinesha	tl0 <=`OC8051_RST_TL0;
135			th0 <=`OC8051_RST_TH0;
136			`tf0 <= 1'b0;`
137			`tf1_0 <= 1'b0;`
138	2	dinesha	end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL0)) begin
139	36	dinesha	`tl0 <= data_in;`
140			`tf0 <= 1'b0;`
141			`tf1_0 <= 1'b0;`
142	2	dinesha	end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH0)) begin
143	36	dinesha	`th0 <= data_in;`
144			`tf0 <= 1'b0;`
145			`tf1_0 <= 1'b0;`
146	2	dinesha	`end else begin`
147			`case (tmod[1:0]) /* synopsys full_case parallel_case */`
148			`OC8051_MODE0: begin // mode 0
149	36	dinesha	`tf1_0 <= 1'b0;`
150	2	dinesha	`if (tc0_add)`
151	36	dinesha	`{tf0, th0,tl0[4:0]} <= {1'b0, th0, tl0[4:0]}+ 1'b1;`
152	2	dinesha	`end`
153			`OC8051_MODE1: begin // mode 1
154	36	dinesha	`tf1_0 <= 1'b0;`
155	2	dinesha	`if (tc0_add)`
156	36	dinesha	`{tf0, th0,tl0} <= {1'b0, th0, tl0}+ 1'b1;`
157	2	dinesha	`end`
158
159			`OC8051_MODE2: begin // mode 2
160	36	dinesha	`tf1_0 <= 1'b0;`
161	2	dinesha	`if (tc0_add) begin`
162			`if (tl0 == 8'b1111_1111) begin`
163	36	dinesha	`tf0 <=1'b1;`
164			`tl0 <=th0;`
165	2	dinesha	`end`
166			`else begin`
167	36	dinesha	`tl0 <=tl0 + 8'h1;`
168			`tf0 <= 1'b0;`
169	2	dinesha	`end`
170			`end`
171			`end`
172			`OC8051_MODE3: begin // mode 3
173
174			`if (tc0_add)`
175	36	dinesha	`{tf0, tl0} <= {1'b0, tl0} +1'b1;`
176	2	dinesha
177			`if (tr1 & pres_ow)`
178	36	dinesha	`{tf1_0, th0} <= {1'b0, th0} +1'b1;`
179	2	dinesha
180			`end`
181			`/* default:begin`
182	36	dinesha	`tf0 <= 1'b0;`
183			`tf1_0 <= 1'b0;`
184	2	dinesha	`end*/`
185			`endcase`
186			`end`
187			`end`
188
189			`//`
190			`// TIMER COUNTER 1`
191			`//`
192	25	dinesha	`always @(posedge clk or negedge resetn)`
193	2	dinesha	`begin`
194	25	dinesha	`if (resetn == 1'b0) begin`
195	36	dinesha	tl1 <=`OC8051_RST_TL1;
196			th1 <=`OC8051_RST_TH1;
197			`tf1_1 <= 1'b0;`
198	2	dinesha	end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL1)) begin
199	36	dinesha	`tl1 <= data_in;`
200			`tf1_1 <= 1'b0;`
201	2	dinesha	end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH1)) begin
202	36	dinesha	`th1 <= data_in;`
203			`tf1_1 <= 1'b0;`
204	2	dinesha	`end else begin`
205			`case (tmod[5:4]) /* synopsys full_case parallel_case */`
206			`OC8051_MODE0: begin // mode 0
207			`if (tc1_add)`
208	36	dinesha	`{tf1_1, th1,tl1[4:0]} <= {1'b0, th1, tl1[4:0]}+ 1'b1;`
209	2	dinesha	`end`
210			`OC8051_MODE1: begin // mode 1
211			`if (tc1_add)`
212	36	dinesha	`{tf1_1, th1,tl1} <= {1'b0, th1, tl1}+ 1'b1;`
213	2	dinesha	`end`
214
215			`OC8051_MODE2: begin // mode 2
216			`if (tc1_add) begin`
217			`if (tl1 == 8'b1111_1111) begin`
218	36	dinesha	`tf1_1 <=1'b1;`
219			`tl1 <=th1;`
220	2	dinesha	`end`
221			`else begin`
222	36	dinesha	`tl1 <=tl1 + 8'h1;`
223			`tf1_1 <= 1'b0;`
224	2	dinesha	`end`
225			`end`
226			`end`
227	36	dinesha	`default:begin`
228			`tf1_1 <= 1'b0;`
229			`end`
230	2	dinesha	`endcase`
231			`end`
232			`end`
233
234
235	25	dinesha	`always @(posedge clk or negedge resetn)`
236			`if (resetn == 1'b0) begin`
237	36	dinesha	`t0_buff <= 1'b0;`
238			`t1_buff <= 1'b0;`
239	2	dinesha	`end else begin`
240	36	dinesha	`t0_buff <= t0;`
241			`t1_buff <= t1;`
242	2	dinesha	`end`
243			`endmodule`

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[/] [oms8051mini/] [trunk/] [rtl/] [8051/] [oc8051_tc.v] - Blame information for rev 36