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[/] [oms8051mini/] [trunk/] [rtl/] [core/] [digital_core.v] - Blame information for rev 10

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OMS 8051 Dgital core Module                                 ////
////                                                              ////
////  This file is part of the OMS 8051 cores project             ////
////  http://www.opencores.org/cores/oms8051mini/                 ////
////                                                              ////
////  Description                                                 ////
////  OMS 8051 definitions.                                       ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
////  Revision : Nov 26, 2016                                     //// 
////                                                              ////
//////////////////////////////////////////////////////////////////////
//     v0.0 - Dinesh A, 26th Nov 2016
//          1. MAC related logic are remved
//     v0.1 - Dinesh A, 1st Dec 2016
//          1. RAM and ROM are internally connected to interconnect
//          2. Memory Map Change
//          3. Remove the External ROM Option & Enabled Internal ROM
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
`include "top_defines.v"
module digital_core  (
 
             reset_n                ,
             scan_mode              ,
             scan_enable             ,
             fastsim_mode           ,
             mastermode             ,
             xtal_clk               ,
             clkout                 ,
             reset_out_n            ,
             ea_in                  ,
 
        // Reg Bus Interface Signal
             ext_reg_cs             ,
             ext_reg_tid            ,
             ext_reg_wr             ,
             ext_reg_addr           ,
             ext_reg_wdata          ,
             ext_reg_be             ,
 
            // Outputs
             ext_reg_rdata          ,
             ext_reg_ack            ,
 
 
 
       // UART Line Interface
             si                     ,
             so                     ,
 
 
             spi_sck                ,
             spi_so                 ,
             spi_si                 ,
             spi_cs_n
 
 
 
 
 
        );
 
 
//----------------------------------------
// Global Clock Defination
//----------------------------------------
input            reset_n               ; // Active Low Reset           
input            scan_mode             ; // scan mode
input            scan_enable           ; // scan enable
input            fastsim_mode          ; // Fast Sim Mode
input            mastermode            ; // 1 : Risc master mode
input            ea_in                  ; // input for external access (ea signal)
                                          // ea=0 program is in external rom
                                          // ea=1 program is in internal rom
 
input            xtal_clk              ; // xtal clock 25Mhz
output           clkout                ; // clock output
output           reset_out_n           ; // clock output
 
//---------------------------------
// Reg Bus Interface Signal
//---------------------------------
input            ext_reg_cs            ;
input            ext_reg_wr            ;
input [3:0]      ext_reg_tid           ;
input [14:0]     ext_reg_addr          ;
input [31:0]     ext_reg_wdata         ;
input [3:0]      ext_reg_be            ;
 
// Outputs
output [31:0]    ext_reg_rdata         ;
output           ext_reg_ack           ;
 
 
 
//----------------------------------------
// UART Line Interface
//----------------------------------------
input            si                     ; // serial in
output           so                     ; // serial out
 
//----------------------------------------
// SPI Line Interface
//----------------------------------------
 
output           spi_sck                ; // clock
output           spi_so                 ; // data out
input            spi_si                 ; // data in
output  [3:0]    spi_cs_n               ; // chip select
 
 
//----------------------------------------
// 8051 core RAM related signals
//---------------------------------------
wire [15:0]      wb_xram_adr            ; // data-ram address
wire             wb_xram_ack            ; // data-ram acknowlage
wire             wb_xram_err            ; // data-ram error
wire             wb_xram_wr             ; // data-ram error
wire [3:0]       wb_xram_be             ; // Byte enable
wire [31:0]      wb_xram_rdata          ; // ram data input
wire [31:0]      wb_xram_wdata          ; // ram data input
 
wire             wb_xram_stb            ; // data-ram strobe
wire             wb_xram_cyc            ; // data-ram cycle
 
 
//---------------------------------------------
// 8051 Instruction ROM interface
//---------------------------------------------
wire    [15:0]   wbi_risc_adr;
wire    [31:0]   wbi_risc_rdata;
 
 
//-----------------------------
// wire Decleration
//-----------------------------
wire             gen_resetn             ;
 
 
//---------------------------------------------
// 8051 Instruction RAM interface
//---------------------------------------------
wire    [15:0]   wbd_risc_adr           ;
wire    [7:0]    wbd_risc_rdata         ;
wire    [7:0]    wbd_risc_wdata         ;
 
 
wire    [14:0]   reg_uart_addr          ;
wire    [31:0]   reg_uart_wdata         ;
wire    [3:0]    reg_uart_be            ;
wire    [31:0]   reg_uart_rdata         ;
wire             reg_uart_ack           ;
 
wire    [14:0]   reg_spi_addr           ;
wire    [31:0]   reg_spi_wdata          ;
wire    [3:0]    reg_spi_be             ;
wire    [31:0]   reg_spi_rdata          ;
wire             reg_spi_ack            ;
 
wire    [3:0]    wb_xrom_be            ;
 
wire    [7:0]    p0              ;
wire    [7:0]    p1              ;
wire    [7:0]    p2              ;
wire    [7:0]    p3              ;
 
 
wire [31:0] reg_rdata = (reg_uart_ack) ? reg_uart_rdata :
                        (reg_spi_ack)  ? reg_spi_rdata : 'h0;
 
wire reg_ack = reg_uart_ack | reg_spi_ack;
 
 
assign reset_out_n = gen_resetn;
 
 
assign wb_xram_adr[15]    = 0;
assign wb_xram_adr[1:0]   = 2'b00;
 
assign reg_uart_addr[1:0] = 2'b0;
assign reg_spi_addr[1:0] = 2'b0;
//-------------------------------------------
// clock-gen  instantiation
//-------------------------------------------
clkgen u_clkgen (
               . reset_n                (reset_n               ),
               . fastsim_mode           (fastsim_mode          ),
               . mastermode             (mastermode            ),
               . xtal_clk               (xtal_clk              ),
               . clkout                 (clkout                ),
               . gen_resetn             (gen_resetn            ),
               . risc_reset             (risc_reset            ),
               . app_clk                (app_clk               ),
               . uart_ref_clk           (uart_clk_16x          )
 
              );
 
 
 
wire [31:0] wb_master2_rdata;
 
wire [3:0] wb_master2_be = (wbd_risc_adr[1:0] == 2'b00) ? 4'b0001:
                           (wbd_risc_adr[1:0] == 2'b01) ? 4'b0010:
                           (wbd_risc_adr[1:0] == 2'b10) ? 4'b0100: 4'b1000;
 
assign     wbd_risc_rdata = (wbd_risc_adr[1:0] == 2'b00) ? wb_master2_rdata[7:0]:
                            (wbd_risc_adr[1:0] == 2'b01) ? wb_master2_rdata[15:8]:
                            (wbd_risc_adr[1:0] == 2'b10) ? wb_master2_rdata[23:16]:
                            wb_master2_rdata[31:24];
 
//------------------------------
// 8051 Data Memory Map
// 0x0000 to 0x7FFFF  - Data Memory
// 0x8000 to 0x8FFF   - SPI 
// 0x9000 to 0x9FFF   - UART
//--------------------------------------------------------------
// Target ID Mapping
// 4'b0010 -- UART
// 4'b0001 -- SPI core
// 4'b0000 -- External RAM
//--------------------------------------------------------------
// 
wire [3:0] wbd_tar_id     = (wbd_risc_adr[15]    == 1'b0 ) ? 4'b0000 :
                            (wbd_risc_adr[15:12] == 4'b1000 ) ? 4'b0001 :
                            (wbd_risc_adr[15:12] == 4'b1001 ) ? 4'b0010 : 4'b0000;
 
wb_crossbar #(.WB_MASTER(3),
              .WB_SLAVE(3),
              .D_WD(32),
              .BE_WD(4),
              .ADR_WD(13),
              .TAR_WD(4))
              u_wb_crossbar (
 
              .rst_n                    (gen_resetn           ),
              .clk                      (app_clk              ),
 
 
    // Master Interface Signal
              .wbd_taddr_master         ({4'b0000,
                                          wbd_tar_id,
                                          ext_reg_tid }),
 
              .wbd_din_master           ({32'h0 ,
                                          {wbd_risc_wdata[7:0],
                                          wbd_risc_wdata[7:0],
                                          wbd_risc_wdata[7:0],
                                          wbd_risc_wdata[7:0]},
                                          ext_reg_wdata }
                                         ),
 
              .wbd_dout_master          ({wbi_risc_rdata,
                                          wb_master2_rdata,
                                          ext_reg_rdata}),
 
              .wbd_adr_master           ({wbi_risc_adr[12:0],
                                          wbd_risc_adr[14:2],
                                          ext_reg_addr[14:2]}),
 
              .wbd_be_master            ({4'b1111,
                                          wb_master2_be,
                                          ext_reg_be }
                                           ),
 
              .wbd_we_master            ({1'b0,wbd_risc_we,ext_reg_wr }   ),
 
              .wbd_ack_master           ({wbi_risc_ack,
                                          wbd_risc_ack,
                                          ext_reg_ack } ),
 
              .wbd_stb_master           ({1'b0,
                                          wbd_risc_stb,
                                          ext_reg_cs} ),
 
              .wbd_cyc_master           ({1'b0,
                                          wbd_risc_stb|wbd_risc_ack,
                                          ext_reg_cs|ext_reg_ack }),
 
              .wbd_err_master           (),
              .wbd_rty_master           (),
 
    // Slave Interface Signal
              .wbd_din_slave            ({reg_uart_wdata,
                                          reg_spi_wdata,
                                          wb_xram_wdata
                                          }),
 
              .wbd_dout_slave           ({reg_uart_rdata,
                                          reg_spi_rdata,
                                          {wb_xram_rdata}
                                         }),
 
              .wbd_adr_slave            ({reg_uart_addr[14:2],
                                          reg_spi_addr[14:2],
                                          wb_xram_adr[14:2]}
                                        ),
 
              .wbd_be_slave             ({reg_uart_be,
                                          reg_spi_be,
                                          wb_xram_be }
                                        ),
 
              .wbd_we_slave             ({reg_uart_wr,
                                          reg_spi_wr,
                                          wb_xram_wr
                                          }),
 
              .wbd_ack_slave            ({reg_uart_ack,
                                          reg_spi_ack,
                                          wb_xram_ack
                                         }),
              .wbd_stb_slave            ({reg_uart_cs,
                                          reg_spi_cs,
                                          wb_xram_stb
                                         }),
 
              .wbd_cyc_slave            (),
              .wbd_err_slave            (),
              .wbd_rty_slave            ()
         );
 
 
 
//-------------------------------------
// UART core instantiation
//-------------------------------------
 
uart_core  u_uart_core
 
     (
          . app_reset_n                 (gen_resetn            ),
          . app_clk                     (app_clk               ),
 
 
        // Reg Bus Interface Signal
          . reg_cs                      (reg_uart_cs           ),
          . reg_wr                      (reg_uart_wr           ),
          . reg_addr                    (reg_uart_addr[5:2]    ),
          . reg_wdata                   (reg_uart_wdata        ),
          . reg_be                      (reg_uart_be           ),
 
            // Outputs
          . reg_rdata                   (reg_uart_rdata        ),
          . reg_ack                     (reg_uart_ack          ),
 
 
 
       // Line Interface
          . si                          (si                    ),
          . so                          (so                    )
 
     );
 
 
//--------------------------------
// SPI core instantiation
//--------------------------------
 
 
spi_core u_spi_core (
 
          . clk                         (app_clk               ),
          . reset_n                     (gen_resetn            ),
 
        // Reg Bus Interface Signal
          . reg_cs                      (reg_spi_cs            ),
          . reg_wr                      (reg_spi_wr            ),
          . reg_addr                    (reg_spi_addr[5:2]     ),
          . reg_wdata                   (reg_spi_wdata         ),
          . reg_be                      (reg_spi_be            ),
 
            // Outputs
          . reg_rdata                   (reg_spi_rdata         ),
          . reg_ack                     (reg_spi_ack           ),
 
 
          . sck                         (spi_sck               ),
          . so                          (spi_so                ),
          . si                          (spi_si                ),
          . cs_n                        (spi_cs_n              )
 
           );
 
 
 
oc8051_top u_8051_core (
          . wb_rst_i                    (risc_reset            ),
          . wb_clk_i                    (app_clk               ),
 
//interface to instruction rom
          . wbi_adr_o                   (wbi_risc_adr          ),
          . wbi_dat_i                   (wbi_risc_rdata        ),
          . wbi_stb_o                   (wbi_risc_stb          ),
          . wbi_ack_i                   (wbi_risc_ack          ),
          . wbi_cyc_o                   (wbi_risc_cyc          ),
          . wbi_err_i                   (wbi_risc_err          ),
 
//interface to data ram
          . wbd_dat_i                   (wbd_risc_rdata        ),
          . wbd_dat_o                   (wbd_risc_wdata        ),
          . wbd_adr_o                   (wbd_risc_adr          ),
          . wbd_we_o                    (wbd_risc_we           ),
          . wbd_ack_i                   (wbd_risc_ack          ),
          . wbd_stb_o                   (wbd_risc_stb          ),
          . wbd_cyc_o                   (wbd_risc_cyc          ),
          . wbd_err_i                   (wbd_risc_err          ),
 
// interrupt interface
          . int0_i                      (                      ),
          . int1_i                      (                      ),
 
 
// port interface
  `ifdef OC8051_PORTS
        `ifdef OC8051_PORT0
          .p0_i                         ( p0                    ),
          .p0_o                         ( p0                    ),
        `endif
 
        `ifdef OC8051_PORT1
           .p1_i                        ( p1                    ),
           .p1_o                        ( p1                    ),
        `endif
 
        `ifdef OC8051_PORT2
           .p2_i                        ( p2                    ),
           .p2_o                        ( p2                    ),
        `endif
 
        `ifdef OC8051_PORT3
           .p3_i                        ( p3                    ),
           .p3_o                        ( p3                    ),
        `endif
  `endif
 
// serial interface
        `ifdef OC8051_UART
           .rxd_i                       (                      ),
           .txd_o                       (                      ),
        `endif
 
// counter interface
        `ifdef OC8051_TC01
           .t0_i                        (                      ),
           .t1_i                        (                      ),
        `endif
 
        `ifdef OC8051_TC2
           .t2_i                        (                      ),
           .t2ex_i                      (                      ),
        `endif
 
// BIST
`ifdef OC8051_BIST
            .scanb_rst                  (                      ),
            .scanb_clk                  (                      ),
            .scanb_si                   (                      ),
            .scanb_so                   (                      ),
            .scanb_en                   (                      ),
`endif
// external access (active low)
            .ea_in                      (ea_in                 )
         );
 
//
// external data ram
//
oc8051_xram oc8051_xram1 (
          .clk               (app_clk       ),
          .rst               (!reset_n      ),
          .wr                (wb_xram_wr    ),
          .be                (wb_xram_be    ),
          .addr              (wb_xram_adr   ),
          .data_in           (wb_xram_wdata ),
          .data_out          (wb_xram_rdata ),
          .ack               (wb_xram_ack   ),
          .stb               (wb_xram_stb   )
      );
 
 
defparam oc8051_xram1.DELAY = 2;
endmodule

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[/] [oms8051mini/] [trunk/] [rtl/] [core/] [digital_core.v] - Blame information for rev 10

Line No.	Rev	Author	Line
1	2	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OMS 8051 Dgital core Module ////`
4			`//// ////`
5			`//// This file is part of the OMS 8051 cores project ////`
6			`//// http://www.opencores.org/cores/oms8051mini/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// OMS 8051 definitions. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Dinesh Annayya, dinesha@opencores.org ////`
16			`//// ////`
17			`//// Revision : Nov 26, 2016 ////`
18			`//// ////`
19			`//////////////////////////////////////////////////////////////////////`
20	10	dinesha	`// v0.0 - Dinesh A, 26th Nov 2016`
21	2	dinesha	`// 1. MAC related logic are remved`
22	10	dinesha	`// v0.1 - Dinesh A, 1st Dec 2016`
23			`// 1. RAM and ROM are internally connected to interconnect`
24			`// 2. Memory Map Change`
25			`// 3. Remove the External ROM Option & Enabled Internal ROM`
26	2	dinesha	`//////////////////////////////////////////////////////////////////////`
27			`//// ////`
28			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
29			`//// ////`
30			`//// This source file may be used and distributed without ////`
31			`//// restriction provided that this copyright statement is not ////`
32			`//// removed from the file and that any derivative work contains ////`
33			`//// the original copyright notice and the associated disclaimer. ////`
34			`//// ////`
35			`//// This source file is free software; you can redistribute it ////`
36			`//// and/or modify it under the terms of the GNU Lesser General ////`
37			`//// Public License as published by the Free Software Foundation; ////`
38			`//// either version 2.1 of the License, or (at your option) any ////`
39			`//// later version. ////`
40			`//// ////`
41			`//// This source is distributed in the hope that it will be ////`
42			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
43			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
44			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
45			`//// details. ////`
46			`//// ////`
47			`//// You should have received a copy of the GNU Lesser General ////`
48			`//// Public License along with this source; if not, download it ////`
49			`//// from http://www.opencores.org/lgpl.shtml ////`
50			`//// ////`
51			`//////////////////////////////////////////////////////////////////////`
52
53			`include "top_defines.v"
54			`module digital_core (`
55
56			`reset_n ,`
57			`scan_mode ,`
58			`scan_enable ,`
59			`fastsim_mode ,`
60			`mastermode ,`
61			`xtal_clk ,`
62			`clkout ,`
63			`reset_out_n ,`
64	10	dinesha	`ea_in ,`
65	2	dinesha
66			`// Reg Bus Interface Signal`
67			`ext_reg_cs ,`
68			`ext_reg_tid ,`
69			`ext_reg_wr ,`
70			`ext_reg_addr ,`
71			`ext_reg_wdata ,`
72			`ext_reg_be ,`
73
74			`// Outputs`
75			`ext_reg_rdata ,`
76			`ext_reg_ack ,`
77
78
79
80			`// UART Line Interface`
81			`si ,`
82			`so ,`
83
84
85			`spi_sck ,`
86			`spi_so ,`
87			`spi_si ,`
88	10	dinesha	`spi_cs_n`
89	2	dinesha
90
91
92
93
94			`);`
95
96
97			`//----------------------------------------`
98			`// Global Clock Defination`
99			`//----------------------------------------`
100			`input reset_n ; // Active Low Reset`
101			`input scan_mode ; // scan mode`
102			`input scan_enable ; // scan enable`
103			`input fastsim_mode ; // Fast Sim Mode`
104			`input mastermode ; // 1 : Risc master mode`
105	10	dinesha	`input ea_in ; // input for external access (ea signal)`
106			`// ea=0 program is in external rom`
107			`// ea=1 program is in internal rom`
108	2	dinesha
109			`input xtal_clk ; // xtal clock 25Mhz`
110			`output clkout ; // clock output`
111			`output reset_out_n ; // clock output`
112
113			`//---------------------------------`
114			`// Reg Bus Interface Signal`
115			`//---------------------------------`
116			`input ext_reg_cs ;`
117			`input ext_reg_wr ;`
118			`input [3:0] ext_reg_tid ;`
119			`input [14:0] ext_reg_addr ;`
120			`input [31:0] ext_reg_wdata ;`
121			`input [3:0] ext_reg_be ;`
122
123			`// Outputs`
124			`output [31:0] ext_reg_rdata ;`
125			`output ext_reg_ack ;`
126
127
128
129			`//----------------------------------------`
130			`// UART Line Interface`
131			`//----------------------------------------`
132			`input si ; // serial in`
133			`output so ; // serial out`
134
135			`//----------------------------------------`
136			`// SPI Line Interface`
137			`//----------------------------------------`
138
139			`output spi_sck ; // clock`
140			`output spi_so ; // data out`
141			`input spi_si ; // data in`
142			`output [3:0] spi_cs_n ; // chip select`
143
144
145			`//----------------------------------------`
146			`// 8051 core RAM related signals`
147			`//---------------------------------------`
148	10	dinesha	`wire [15:0] wb_xram_adr ; // data-ram address`
149			`wire wb_xram_ack ; // data-ram acknowlage`
150			`wire wb_xram_err ; // data-ram error`
151			`wire wb_xram_wr ; // data-ram error`
152			`wire [3:0] wb_xram_be ; // Byte enable`
153			`wire [31:0] wb_xram_rdata ; // ram data input`
154			`wire [31:0] wb_xram_wdata ; // ram data input`
155	2	dinesha
156	10	dinesha	`wire wb_xram_stb ; // data-ram strobe`
157			`wire wb_xram_cyc ; // data-ram cycle`
158	2	dinesha
159
160			`//---------------------------------------------`
161			`// 8051 Instruction ROM interface`
162			`//---------------------------------------------`
163			`wire [15:0] wbi_risc_adr;`
164			`wire [31:0] wbi_risc_rdata;`
165
166
167			`//-----------------------------`
168			`// wire Decleration`
169			`//-----------------------------`
170			`wire gen_resetn ;`
171
172
173			`//---------------------------------------------`
174			`// 8051 Instruction RAM interface`
175			`//---------------------------------------------`
176			`wire [15:0] wbd_risc_adr ;`
177			`wire [7:0] wbd_risc_rdata ;`
178			`wire [7:0] wbd_risc_wdata ;`
179
180
181			`wire [14:0] reg_uart_addr ;`
182			`wire [31:0] reg_uart_wdata ;`
183			`wire [3:0] reg_uart_be ;`
184			`wire [31:0] reg_uart_rdata ;`
185			`wire reg_uart_ack ;`
186
187			`wire [14:0] reg_spi_addr ;`
188			`wire [31:0] reg_spi_wdata ;`
189			`wire [3:0] reg_spi_be ;`
190			`wire [31:0] reg_spi_rdata ;`
191			`wire reg_spi_ack ;`
192
193			`wire [3:0] wb_xrom_be ;`
194
195			`wire [7:0] p0 ;`
196			`wire [7:0] p1 ;`
197			`wire [7:0] p2 ;`
198			`wire [7:0] p3 ;`
199
200
201			`wire [31:0] reg_rdata = (reg_uart_ack) ? reg_uart_rdata :`
202			`(reg_spi_ack) ? reg_spi_rdata : 'h0;`
203
204			`wire reg_ack = reg_uart_ack \| reg_spi_ack;`
205
206
207			`assign reset_out_n = gen_resetn;`
208
209
210			`assign wb_xram_adr[15] = 0;`
211			`assign wb_xram_adr[1:0] = 2'b00;`
212
213			`assign reg_uart_addr[1:0] = 2'b0;`
214			`assign reg_spi_addr[1:0] = 2'b0;`
215			`//-------------------------------------------`
216			`// clock-gen instantiation`
217			`//-------------------------------------------`
218			`clkgen u_clkgen (`
219			`. reset_n (reset_n ),`
220			`. fastsim_mode (fastsim_mode ),`
221			`. mastermode (mastermode ),`
222			`. xtal_clk (xtal_clk ),`
223			`. clkout (clkout ),`
224			`. gen_resetn (gen_resetn ),`
225			`. risc_reset (risc_reset ),`
226			`. app_clk (app_clk ),`
227			`. uart_ref_clk (uart_clk_16x )`
228
229			`);`
230
231
232
233			`wire [31:0] wb_master2_rdata;`
234
235			`wire [3:0] wb_master2_be = (wbd_risc_adr[1:0] == 2'b00) ? 4'b0001:`
236			`(wbd_risc_adr[1:0] == 2'b01) ? 4'b0010:`
237			`(wbd_risc_adr[1:0] == 2'b10) ? 4'b0100: 4'b1000;`
238
239			`assign wbd_risc_rdata = (wbd_risc_adr[1:0] == 2'b00) ? wb_master2_rdata[7:0]:`
240			`(wbd_risc_adr[1:0] == 2'b01) ? wb_master2_rdata[15:8]:`
241			`(wbd_risc_adr[1:0] == 2'b10) ? wb_master2_rdata[23:16]:`
242			`wb_master2_rdata[31:24];`
243
244			`//------------------------------`
245			`// 8051 Data Memory Map`
246			`// 0x0000 to 0x7FFFF - Data Memory`
247			`// 0x8000 to 0x8FFF - SPI`
248			`// 0x9000 to 0x9FFF - UART`
249			`//--------------------------------------------------------------`
250			`// Target ID Mapping`
251	10	dinesha	`// 4'b0010 -- UART`
252			`// 4'b0001 -- SPI core`
253			`// 4'b0000 -- External RAM`
254	2	dinesha	`//--------------------------------------------------------------`
255			`//`
256	10	dinesha	`wire [3:0] wbd_tar_id = (wbd_risc_adr[15] == 1'b0 ) ? 4'b0000 :`
257			`(wbd_risc_adr[15:12] == 4'b1000 ) ? 4'b0001 :`
258			`(wbd_risc_adr[15:12] == 4'b1001 ) ? 4'b0010 : 4'b0000;`
259	2	dinesha
260			`wb_crossbar #(.WB_MASTER(3),`
261	10	dinesha	`.WB_SLAVE(3),`
262	2	dinesha	`.D_WD(32),`
263			`.BE_WD(4),`
264			`.ADR_WD(13),`
265			`.TAR_WD(4))`
266			`u_wb_crossbar (`
267
268			`.rst_n (gen_resetn ),`
269			`.clk (app_clk ),`
270
271
272			`// Master Interface Signal`
273			`.wbd_taddr_master ({4'b0000,`
274			`wbd_tar_id,`
275			`ext_reg_tid }),`
276
277			`.wbd_din_master ({32'h0 ,`
278			`{wbd_risc_wdata[7:0],`
279			`wbd_risc_wdata[7:0],`
280			`wbd_risc_wdata[7:0],`
281			`wbd_risc_wdata[7:0]},`
282			`ext_reg_wdata }`
283			`),`
284
285			`.wbd_dout_master ({wbi_risc_rdata,`
286			`wb_master2_rdata,`
287			`ext_reg_rdata}),`
288
289			`.wbd_adr_master ({wbi_risc_adr[12:0],`
290			`wbd_risc_adr[14:2],`
291			`ext_reg_addr[14:2]}),`
292
293			`.wbd_be_master ({4'b1111,`
294			`wb_master2_be,`
295			`ext_reg_be }`
296			`),`
297
298			`.wbd_we_master ({1'b0,wbd_risc_we,ext_reg_wr } ),`
299
300			`.wbd_ack_master ({wbi_risc_ack,`
301			`wbd_risc_ack,`
302			`ext_reg_ack } ),`
303
304	10	dinesha	`.wbd_stb_master ({1'b0,`
305	2	dinesha	`wbd_risc_stb,`
306			`ext_reg_cs} ),`
307
308	10	dinesha	`.wbd_cyc_master ({1'b0,`
309	2	dinesha	`wbd_risc_stb\|wbd_risc_ack,`
310			`ext_reg_cs\|ext_reg_ack }),`
311
312			`.wbd_err_master (),`
313			`.wbd_rty_master (),`
314
315			`// Slave Interface Signal`
316			`.wbd_din_slave ({reg_uart_wdata,`
317			`reg_spi_wdata,`
318	10	dinesha	`wb_xram_wdata`
319	2	dinesha	`}),`
320
321			`.wbd_dout_slave ({reg_uart_rdata,`
322			`reg_spi_rdata,`
323	10	dinesha	`{wb_xram_rdata}`
324	2	dinesha	`}),`
325
326			`.wbd_adr_slave ({reg_uart_addr[14:2],`
327			`reg_spi_addr[14:2],`
328	10	dinesha	`wb_xram_adr[14:2]}`
329	2	dinesha	`),`
330
331			`.wbd_be_slave ({reg_uart_be,`
332			`reg_spi_be,`
333	10	dinesha	`wb_xram_be }`
334	2	dinesha	`),`
335
336			`.wbd_we_slave ({reg_uart_wr,`
337			`reg_spi_wr,`
338	10	dinesha	`wb_xram_wr`
339	2	dinesha	`}),`
340
341			`.wbd_ack_slave ({reg_uart_ack,`
342			`reg_spi_ack,`
343	10	dinesha	`wb_xram_ack`
344	2	dinesha	`}),`
345			`.wbd_stb_slave ({reg_uart_cs,`
346			`reg_spi_cs,`
347	10	dinesha	`wb_xram_stb`
348	2	dinesha	`}),`
349
350			`.wbd_cyc_slave (),`
351			`.wbd_err_slave (),`
352			`.wbd_rty_slave ()`
353			`);`
354
355
356
357			`//-------------------------------------`
358			`// UART core instantiation`
359			`//-------------------------------------`
360
361			`uart_core u_uart_core`
362
363			`(`
364			`. app_reset_n (gen_resetn ),`
365			`. app_clk (app_clk ),`
366
367
368			`// Reg Bus Interface Signal`
369			`. reg_cs (reg_uart_cs ),`
370			`. reg_wr (reg_uart_wr ),`
371			`. reg_addr (reg_uart_addr[5:2] ),`
372			`. reg_wdata (reg_uart_wdata ),`
373			`. reg_be (reg_uart_be ),`
374
375			`// Outputs`
376			`. reg_rdata (reg_uart_rdata ),`
377			`. reg_ack (reg_uart_ack ),`
378
379
380
381			`// Line Interface`
382			`. si (si ),`
383			`. so (so )`
384
385			`);`
386
387
388			`//--------------------------------`
389			`// SPI core instantiation`
390			`//--------------------------------`
391
392
393			`spi_core u_spi_core (`
394
395			`. clk (app_clk ),`
396			`. reset_n (gen_resetn ),`
397
398			`// Reg Bus Interface Signal`
399			`. reg_cs (reg_spi_cs ),`
400			`. reg_wr (reg_spi_wr ),`
401			`. reg_addr (reg_spi_addr[5:2] ),`
402			`. reg_wdata (reg_spi_wdata ),`
403			`. reg_be (reg_spi_be ),`
404
405			`// Outputs`
406			`. reg_rdata (reg_spi_rdata ),`
407			`. reg_ack (reg_spi_ack ),`
408
409
410			`. sck (spi_sck ),`
411			`. so (spi_so ),`
412			`. si (spi_si ),`
413			`. cs_n (spi_cs_n )`
414
415			`);`
416
417
418
419			`oc8051_top u_8051_core (`
420			`. wb_rst_i (risc_reset ),`
421			`. wb_clk_i (app_clk ),`
422
423			`//interface to instruction rom`
424			`. wbi_adr_o (wbi_risc_adr ),`
425			`. wbi_dat_i (wbi_risc_rdata ),`
426			`. wbi_stb_o (wbi_risc_stb ),`
427			`. wbi_ack_i (wbi_risc_ack ),`
428			`. wbi_cyc_o (wbi_risc_cyc ),`
429			`. wbi_err_i (wbi_risc_err ),`
430
431			`//interface to data ram`
432			`. wbd_dat_i (wbd_risc_rdata ),`
433			`. wbd_dat_o (wbd_risc_wdata ),`
434			`. wbd_adr_o (wbd_risc_adr ),`
435			`. wbd_we_o (wbd_risc_we ),`
436			`. wbd_ack_i (wbd_risc_ack ),`
437			`. wbd_stb_o (wbd_risc_stb ),`
438			`. wbd_cyc_o (wbd_risc_cyc ),`
439			`. wbd_err_i (wbd_risc_err ),`
440
441			`// interrupt interface`
442			`. int0_i ( ),`
443			`. int1_i ( ),`
444
445
446			`// port interface`
447			`ifdef OC8051_PORTS
448			`ifdef OC8051_PORT0
449			`.p0_i ( p0 ),`
450			`.p0_o ( p0 ),`
451			`endif
452
453			`ifdef OC8051_PORT1
454			`.p1_i ( p1 ),`
455			`.p1_o ( p1 ),`
456			`endif
457
458			`ifdef OC8051_PORT2
459			`.p2_i ( p2 ),`
460			`.p2_o ( p2 ),`
461			`endif
462
463			`ifdef OC8051_PORT3
464			`.p3_i ( p3 ),`
465			`.p3_o ( p3 ),`
466			`endif
467			`endif
468
469			`// serial interface`
470			`ifdef OC8051_UART
471			`.rxd_i ( ),`
472			`.txd_o ( ),`
473			`endif
474
475			`// counter interface`
476			`ifdef OC8051_TC01
477			`.t0_i ( ),`
478			`.t1_i ( ),`
479			`endif
480
481			`ifdef OC8051_TC2
482			`.t2_i ( ),`
483			`.t2ex_i ( ),`
484			`endif
485
486			`// BIST`
487			`ifdef OC8051_BIST
488			`.scanb_rst ( ),`
489			`.scanb_clk ( ),`
490			`.scanb_si ( ),`
491			`.scanb_so ( ),`
492			`.scanb_en ( ),`
493			`endif
494			`// external access (active low)`
495			`.ea_in (ea_in )`
496			`);`
497
498	10	dinesha	`//`
499			`// external data ram`
500			`//`
501			`oc8051_xram oc8051_xram1 (`
502			`.clk (app_clk ),`
503			`.rst (!reset_n ),`
504			`.wr (wb_xram_wr ),`
505			`.be (wb_xram_be ),`
506			`.addr (wb_xram_adr ),`
507			`.data_in (wb_xram_wdata ),`
508			`.data_out (wb_xram_rdata ),`
509			`.ack (wb_xram_ack ),`
510			`.stb (wb_xram_stb )`
511			`);`
512
513
514			`defparam oc8051_xram1.DELAY = 2;`
515	2	dinesha	`endmodule`