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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OMS 8051 Digital core Module                                ////
////                                                              ////
////  This file is part of the OMS 8051 cores project             ////
////  http://www.opencores.org/cores/oms8051mini/                 ////
////                                                              ////
////  Description                                                 ////
////  OMS 8051 definitions.                                       ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
////  Revision : Nov 26, 2016                                     //// 
////                                                              ////
//////////////////////////////////////////////////////////////////////
//     v0.0 - Dinesh A, 26th Nov 2016
//          1. MAC related logic are remved
//     v0.1 - Dinesh A, 1st Dec 2016
//          1. RAM and ROM are internally connected to interconnect
//          2. Memory Map Change
//          3. Remove the External ROM Option & Enabled Internal ROM
//     v0.2 - Dinesh A, 9st Dec 2016
//          1. Bus interface is changed from 32 bit to 8 bit
//     v0.3 - Dinesh A, 21 Dec 2016
//          1. Uart Message Handler is integrated 
//          2. Message handler is connected as Register Master to 
//             Inter-connect
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
`include "top_defines.v"
module digital_core  (
 
             reset_n                ,
             scan_mode              ,
             scan_enable             ,
             fastsim_mode           ,
             mastermode             ,
             xtal_clk               ,
             clkout                 ,
             reset_out_n            ,
             ea_in                  ,
 
        // Reg Bus Interface Signal
             ext_reg_cs             ,
             ext_reg_tid            ,
             ext_reg_wr             ,
             ext_reg_addr           ,
             ext_reg_wdata          ,
 
            // Outputs
             ext_reg_rdata          ,
             ext_reg_ack            ,
 
 
 
       // UART Line Interface
             uart0_txd              ,
             uart0_rxd              ,
 
             uart1_txd              ,
             uart1_rxd              ,
 
             spi_sck                ,
             spi_so                 ,
             spi_si                 ,
             spi_cs_n
 
 
 
 
 
        );
 
 
//----------------------------------------
// Global Clock Defination
//----------------------------------------
input            reset_n               ; // Active Low Reset           
input            scan_mode             ; // scan mode
input            scan_enable           ; // scan enable
input            fastsim_mode          ; // Fast Sim Mode
input            mastermode            ; // 1 : Risc master mode
input            ea_in                  ; // input for external access (ea signal)
                                          // ea=0 program is in external rom
                                          // ea=1 program is in internal rom
 
input            xtal_clk              ; // xtal clock 25Mhz
output           clkout                ; // clock output
output           reset_out_n           ; // clock output
 
//---------------------------------
// Reg Bus Interface Signal
//---------------------------------
input            ext_reg_cs            ;
input            ext_reg_wr            ;
input [3:0]      ext_reg_tid           ;
input [14:0]     ext_reg_addr          ;
input [7:0]      ext_reg_wdata         ;
 
// Outputs
output [7:0]     ext_reg_rdata         ;
output           ext_reg_ack           ;
 
 
 
//----------------------------------------
// UART Line Interface
//----------------------------------------
input            uart0_rxd             ; // serial in
output           uart0_txd             ; // serial out
 
input            uart1_rxd             ; // serial in
output           uart1_txd             ; // serial out
 
//----------------------------------------
// SPI Line Interface
//----------------------------------------
 
output           spi_sck                ; // clock
output           spi_so                 ; // data out
input            spi_si                 ; // data in
output  [3:0]    spi_cs_n               ; // chip select
 
 
//----------------------------------------
// 8051 core RAM related signals
//---------------------------------------
wire [15:0]      wb_xram_adr            ; // data-ram address
wire             wb_xram_ack            ; // data-ram acknowlage
wire             wb_xram_err            ; // data-ram error
wire             wb_xram_wr             ; // data-ram error
wire [7:0]       wb_xram_rdata          ; // ram data input
wire [7:0]       wb_xram_wdata          ; // ram data input
 
wire             wb_xram_stb            ; // data-ram strobe
wire             wb_xram_cyc            ; // data-ram cycle
 
 
//----------------------------------------
// Message Controller Reg Master
//---------------------------------------
wire             mh_reg_cs              ;
wire             mh_reg_wr              ;
wire  [3:0]      mh_reg_tid             ;
wire  [15:0]     mh_reg_addr            ;
wire  [7:0]      mh_reg_wdata           ;
 
// Outputs
wire  [7:0]      mh_reg_rdata           ;
wire             mh_reg_ack             ;
 
//-----------------------------
// wire Decleration
//-----------------------------
wire             gen_resetn             ;
 
 
//---------------------------------------------
// 8051 Instruction RAM interface
//---------------------------------------------
wire    [15:0]   wbd_risc_adr           ;
wire    [7:0]    wbd_risc_rdata         ;
wire    [7:0]    wbd_risc_wdata         ;
 
 
wire    [14:0]   reg_uart_addr          ;
wire    [7:0]    reg_uart_wdata         ;
wire    [7:0]    reg_uart_rdata         ;
wire             reg_uart_ack           ;
 
wire    [14:0]   reg_spi_addr           ;
wire    [7:0]    reg_spi_wdata          ;
wire    [7:0]    reg_spi_rdata          ;
wire             reg_spi_ack            ;
 
 
wire    [7:0]    p0              ;
wire    [7:0]    p1              ;
wire    [7:0]    p2              ;
wire    [7:0]    p3              ;
 
 
wire [7:0] reg_rdata = (reg_uart_ack) ? reg_uart_rdata :
                        (reg_spi_ack)  ? reg_spi_rdata : 'h0;
 
wire reg_ack = reg_uart_ack | reg_spi_ack;
 
 
assign reset_out_n = gen_resetn;
 
assign wb_xram_adr[15]    = 0;
 
//-------------------------------------------
// clock-gen  instantiation
//-------------------------------------------
clkgen u_clkgen (
               . reset_n                (reset_n               ),
               . fastsim_mode           (fastsim_mode          ),
               . mastermode             (mastermode            ),
               . xtal_clk               (xtal_clk              ),
               . clkout                 (clkout                ),
               . gen_resetn             (gen_resetn            ),
               . risc_resetn            (risc_resetn           ),
               . app_clk                (app_clk               ),
               . uart_ref_clk           (uart_clk_16x          )
 
              );
 
/************* Message Handler **********/
 
msg_handler_top u_msg_hand_top (
              . line_reset_n            (reset_n               ),
              . line_clk                (app_clk               ),
 
      // Towards Register Interface
              . reg_addr                (mh_reg_addr           ),
              . reg_wr                  (mh_reg_wr             ),
              . reg_wdata               (mh_reg_wdata          ),
              . reg_req                 (mh_reg_cs             ),
              . reg_ack                 (mh_reg_ack            ),
              . reg_rdata               (mh_reg_rdata          ),
 
       // Status information
              . frm_error               (                      ),
              . par_error               (                      ),
 
              . baud_clk_16x            (                      ),
 
       // Line Interface
              . rxd                     (uart0_rxd             ),
              . txd                     (uart0_txd             )
 
 
     );
 
 
 
/***************************************/
wire [7:0] wb_master2_rdata;
 
assign     wbd_risc_rdata = wb_master2_rdata[7:0];
 
//------------------------------
// 8051 Data Memory Map
// 0x0000 to 0x7FFFF  - Data Memory
// 0x8000 to 0x8FFF   - SPI 
// 0x9000 to 0x9FFF   - UART
//--------------------------------------------------------------
// Target ID Mapping
// 4'b0010 -- UART
// 4'b0001 -- SPI core
// 4'b0000 -- External RAM
//--------------------------------------------------------------
// 
wire [3:0] wbd_tar_id     = (wbd_risc_adr[15]    == 1'b0 ) ? 4'b0000 :
                            (wbd_risc_adr[15:12] == 4'b1000 ) ? 4'b0001 :
                            (wbd_risc_adr[15:12] == 4'b1001 ) ? 4'b0010 : 4'b0000;
 
wire [3:0] mh_tar_id     = (mh_reg_addr[15]    == 1'b0 ) ? 4'b0000 :
                           (mh_reg_addr[15:12] == 4'b1000 ) ? 4'b0001 :
                           (mh_reg_addr[15:12] == 4'b1001 ) ? 4'b0010 : 4'b0000;
 
wb_crossbar #(.WB_MASTER(3),
              .WB_SLAVE(3),
              .D_WD(8),
              .BE_WD(1),
              .ADR_WD(15),
              .TAR_WD(4))
              u_wb_crossbar (
 
              .rst_n                    (gen_resetn           ),
              .clk                      (app_clk              ),
 
 
    // Master Interface Signal
              .wbd_taddr_master         ({mh_tar_id,
                                          wbd_tar_id,
                                          ext_reg_tid }),
 
              .wbd_din_master           ({mh_reg_wdata,
                                          wbd_risc_wdata[7:0],
                                          ext_reg_wdata }
                                         ),
 
              .wbd_dout_master          ({mh_reg_rdata,
                                          wb_master2_rdata,
                                          ext_reg_rdata}),
 
              .wbd_adr_master           ({mh_reg_addr[14:0],
                                          wbd_risc_adr[14:0],
                                          ext_reg_addr[14:0]}),
 
              .wbd_be_master            ({1'b1,1'b1,1'b1}),
 
              .wbd_we_master            ({mh_reg_wr,
                                          wbd_risc_we,
                                          ext_reg_wr }   ),
 
              .wbd_ack_master           ({mh_reg_ack,
                                          wbd_risc_ack,
                                          ext_reg_ack } ),
 
              .wbd_stb_master           ({mh_reg_cs,
                                          wbd_risc_stb,
                                          ext_reg_cs} ),
 
              .wbd_cyc_master           ({mh_reg_cs| mh_reg_ack,
                                          wbd_risc_stb|wbd_risc_ack,
                                          ext_reg_cs|ext_reg_ack }),
 
              .wbd_err_master           (),
              .wbd_rty_master           (),
 
    // Slave Interface Signal
              .wbd_din_slave            ({reg_uart_wdata,
                                          reg_spi_wdata,
                                          wb_xram_wdata
                                          }),
 
              .wbd_dout_slave           ({reg_uart_rdata,
                                          reg_spi_rdata,
                                          wb_xram_rdata
                                         }),
 
              .wbd_adr_slave            ({reg_uart_addr[14:0],
                                          reg_spi_addr[14:0],
                                          wb_xram_adr[14:0]}
                                        ),
 
              .wbd_be_slave             (),
 
              .wbd_we_slave             ({reg_uart_wr,
                                          reg_spi_wr,
                                          wb_xram_wr
                                          }),
 
              .wbd_ack_slave            ({reg_uart_ack,
                                          reg_spi_ack,
                                          wb_xram_ack
                                         }),
              .wbd_stb_slave            ({reg_uart_cs,
                                          reg_spi_cs,
                                          wb_xram_stb
                                         }),
 
              .wbd_cyc_slave            (),
              .wbd_err_slave            (),
              .wbd_rty_slave            ()
         );
 
 
 
//-------------------------------------
// UART core instantiation
//-------------------------------------
 
uart_core  u_uart_core
 
     (
          . app_reset_n                 (gen_resetn            ),
          . app_clk                     (app_clk               ),
 
 
        // Reg Bus Interface Signal
          . reg_cs                      (reg_uart_cs           ),
          . reg_wr                      (reg_uart_wr           ),
          . reg_addr                    (reg_uart_addr[3:0]    ),
          . reg_wdata                   (reg_uart_wdata        ),
          . reg_be                      (1'b1                  ),
 
            // Outputs
          . reg_rdata                   (reg_uart_rdata        ),
          . reg_ack                     (reg_uart_ack          ),
 
 
 
       // Line Interface
          . si                          (uart1_rxd             ),
          . so                          (uart1_txd             )
 
     );
 
 
//--------------------------------
// SPI core instantiation
//--------------------------------
 
 
spi_core u_spi_core (
 
          . clk                         (app_clk               ),
          . reset_n                     (gen_resetn            ),
 
        // Reg Bus Interface Signal
          . reg_cs                      (reg_spi_cs            ),
          . reg_wr                      (reg_spi_wr            ),
          . reg_addr                    (reg_spi_addr[3:0]     ),
          . reg_wdata                   (reg_spi_wdata         ),
          . reg_be                      (1'b1                  ),
 
            // Outputs
          . reg_rdata                   (reg_spi_rdata         ),
          . reg_ack                     (reg_spi_ack           ),
 
 
          . sck                         (spi_sck               ),
          . so                          (spi_so                ),
          . si                          (spi_si                ),
          . cs_n                        (spi_cs_n              )
 
           );
 
 
 
oc8051_top u_8051_core (
          . resetn                      (risc_resetn           ),
          . wb_clk_i                    (app_clk               ),
 
//interface to data ram
          . wbd_dat_i                   (wbd_risc_rdata        ),
          . wbd_dat_o                   (wbd_risc_wdata        ),
          . wbd_adr_o                   (wbd_risc_adr          ),
          . wbd_we_o                    (wbd_risc_we           ),
          . wbd_ack_i                   (wbd_risc_ack          ),
          . wbd_stb_o                   (wbd_risc_stb          ),
          . wbd_cyc_o                   (wbd_risc_cyc          ),
          . wbd_err_i                   (wbd_risc_err          ),
 
// interrupt interface
          . int0_i                      (                      ),
          . int1_i                      (                      ),
 
 
// port interface
  `ifdef OC8051_PORTS
        `ifdef OC8051_PORT0
          .p0_i                         ( p0                    ),
          .p0_o                         ( p0                    ),
        `endif
 
        `ifdef OC8051_PORT1
           .p1_i                        ( p1                    ),
           .p1_o                        ( p1                    ),
        `endif
 
        `ifdef OC8051_PORT2
           .p2_i                        ( p2                    ),
           .p2_o                        ( p2                    ),
        `endif
 
        `ifdef OC8051_PORT3
           .p3_i                        ( p3                    ),
           .p3_o                        ( p3                    ),
        `endif
  `endif
 
// serial interface
        `ifdef OC8051_UART
           .rxd_i                       (                      ),
           .txd_o                       (                      ),
        `endif
 
// counter interface
        `ifdef OC8051_TC01
           .t0_i                        (                      ),
           .t1_i                        (                      ),
        `endif
 
        `ifdef OC8051_TC2
           .t2_i                        (                      ),
           .t2ex_i                      (                      ),
        `endif
 
// BIST
`ifdef OC8051_BIST
            .scanb_rst                  (                      ),
            .scanb_clk                  (                      ),
            .scanb_si                   (                      ),
            .scanb_so                   (                      ),
            .scanb_en                   (                      ),
`endif
// external access (active low)
            .ea_in                      (ea_in                 )
         );
 
//
// external data ram
//
oc8051_xram oc8051_xram1 (
          .clk               (app_clk       ),
          .rst               (!reset_n      ),
          .wr                (wb_xram_wr    ),
          .addr              (wb_xram_adr   ),
          .data_in           (wb_xram_wdata ),
          .data_out          (wb_xram_rdata ),
          .ack               (wb_xram_ack   ),
          .stb               (wb_xram_stb   )
      );
 
 
defparam oc8051_xram1.DELAY = 2;
endmodule

Line No.	Rev	Author	Line
1	2	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3	11	dinesha	`//// OMS 8051 Digital core Module ////`
4	2	dinesha	`//// ////`
5			`//// This file is part of the OMS 8051 cores project ////`
6			`//// http://www.opencores.org/cores/oms8051mini/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// OMS 8051 definitions. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Dinesh Annayya, dinesha@opencores.org ////`
16			`//// ////`
17			`//// Revision : Nov 26, 2016 ////`
18			`//// ////`
19			`//////////////////////////////////////////////////////////////////////`
20	10	dinesha	`// v0.0 - Dinesh A, 26th Nov 2016`
21	2	dinesha	`// 1. MAC related logic are remved`
22	10	dinesha	`// v0.1 - Dinesh A, 1st Dec 2016`
23			`// 1. RAM and ROM are internally connected to interconnect`
24			`// 2. Memory Map Change`
25			`// 3. Remove the External ROM Option & Enabled Internal ROM`
26	11	dinesha	`// v0.2 - Dinesh A, 9st Dec 2016`
27			`// 1. Bus interface is changed from 32 bit to 8 bit`
28	19	dinesha	`// v0.3 - Dinesh A, 21 Dec 2016`
29			`// 1. Uart Message Handler is integrated`
30			`// 2. Message handler is connected as Register Master to`
31			`// Inter-connect`
32	2	dinesha	`//////////////////////////////////////////////////////////////////////`
33			`//// ////`
34			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
35			`//// ////`
36			`//// This source file may be used and distributed without ////`
37			`//// restriction provided that this copyright statement is not ////`
38			`//// removed from the file and that any derivative work contains ////`
39			`//// the original copyright notice and the associated disclaimer. ////`
40			`//// ////`
41			`//// This source file is free software; you can redistribute it ////`
42			`//// and/or modify it under the terms of the GNU Lesser General ////`
43			`//// Public License as published by the Free Software Foundation; ////`
44			`//// either version 2.1 of the License, or (at your option) any ////`
45			`//// later version. ////`
46			`//// ////`
47			`//// This source is distributed in the hope that it will be ////`
48			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
49			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
50			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
51			`//// details. ////`
52			`//// ////`
53			`//// You should have received a copy of the GNU Lesser General ////`
54			`//// Public License along with this source; if not, download it ////`
55			`//// from http://www.opencores.org/lgpl.shtml ////`
56			`//// ////`
57			`//////////////////////////////////////////////////////////////////////`
58
59			`include "top_defines.v"
60			`module digital_core (`
61
62			`reset_n ,`
63			`scan_mode ,`
64			`scan_enable ,`
65			`fastsim_mode ,`
66			`mastermode ,`
67			`xtal_clk ,`
68			`clkout ,`
69			`reset_out_n ,`
70	10	dinesha	`ea_in ,`
71	2	dinesha
72			`// Reg Bus Interface Signal`
73			`ext_reg_cs ,`
74			`ext_reg_tid ,`
75			`ext_reg_wr ,`
76			`ext_reg_addr ,`
77			`ext_reg_wdata ,`
78
79			`// Outputs`
80			`ext_reg_rdata ,`
81			`ext_reg_ack ,`
82
83
84
85			`// UART Line Interface`
86	19	dinesha	`uart0_txd ,`
87			`uart0_rxd ,`
88	2	dinesha
89	19	dinesha	`uart1_txd ,`
90			`uart1_rxd ,`
91	2	dinesha
92			`spi_sck ,`
93			`spi_so ,`
94			`spi_si ,`
95	10	dinesha	`spi_cs_n`
96	2	dinesha
97
98
99
100
101			`);`
102
103
104			`//----------------------------------------`
105			`// Global Clock Defination`
106			`//----------------------------------------`
107			`input reset_n ; // Active Low Reset`
108			`input scan_mode ; // scan mode`
109			`input scan_enable ; // scan enable`
110			`input fastsim_mode ; // Fast Sim Mode`
111			`input mastermode ; // 1 : Risc master mode`
112	10	dinesha	`input ea_in ; // input for external access (ea signal)`
113			`// ea=0 program is in external rom`
114			`// ea=1 program is in internal rom`
115	2	dinesha
116			`input xtal_clk ; // xtal clock 25Mhz`
117			`output clkout ; // clock output`
118			`output reset_out_n ; // clock output`
119
120			`//---------------------------------`
121			`// Reg Bus Interface Signal`
122			`//---------------------------------`
123			`input ext_reg_cs ;`
124			`input ext_reg_wr ;`
125			`input [3:0] ext_reg_tid ;`
126			`input [14:0] ext_reg_addr ;`
127	11	dinesha	`input [7:0] ext_reg_wdata ;`
128	2	dinesha
129			`// Outputs`
130	11	dinesha	`output [7:0] ext_reg_rdata ;`
131	2	dinesha	`output ext_reg_ack ;`
132
133
134
135			`//----------------------------------------`
136			`// UART Line Interface`
137			`//----------------------------------------`
138	19	dinesha	`input uart0_rxd ; // serial in`
139			`output uart0_txd ; // serial out`
140	2	dinesha
141	19	dinesha	`input uart1_rxd ; // serial in`
142			`output uart1_txd ; // serial out`
143
144	2	dinesha	`//----------------------------------------`
145			`// SPI Line Interface`
146			`//----------------------------------------`
147
148			`output spi_sck ; // clock`
149			`output spi_so ; // data out`
150			`input spi_si ; // data in`
151			`output [3:0] spi_cs_n ; // chip select`
152
153
154			`//----------------------------------------`
155			`// 8051 core RAM related signals`
156			`//---------------------------------------`
157	10	dinesha	`wire [15:0] wb_xram_adr ; // data-ram address`
158			`wire wb_xram_ack ; // data-ram acknowlage`
159			`wire wb_xram_err ; // data-ram error`
160			`wire wb_xram_wr ; // data-ram error`
161	11	dinesha	`wire [7:0] wb_xram_rdata ; // ram data input`
162			`wire [7:0] wb_xram_wdata ; // ram data input`
163	2	dinesha
164	10	dinesha	`wire wb_xram_stb ; // data-ram strobe`
165			`wire wb_xram_cyc ; // data-ram cycle`
166	2	dinesha
167
168	19	dinesha	`//----------------------------------------`
169			`// Message Controller Reg Master`
170			`//---------------------------------------`
171			`wire mh_reg_cs ;`
172			`wire mh_reg_wr ;`
173			`wire [3:0] mh_reg_tid ;`
174			`wire [15:0] mh_reg_addr ;`
175			`wire [7:0] mh_reg_wdata ;`
176	2	dinesha
177	19	dinesha	`// Outputs`
178			`wire [7:0] mh_reg_rdata ;`
179			`wire mh_reg_ack ;`
180
181	2	dinesha	`//-----------------------------`
182			`// wire Decleration`
183			`//-----------------------------`
184			`wire gen_resetn ;`
185
186
187			`//---------------------------------------------`
188			`// 8051 Instruction RAM interface`
189			`//---------------------------------------------`
190			`wire [15:0] wbd_risc_adr ;`
191			`wire [7:0] wbd_risc_rdata ;`
192			`wire [7:0] wbd_risc_wdata ;`
193
194
195			`wire [14:0] reg_uart_addr ;`
196	11	dinesha	`wire [7:0] reg_uart_wdata ;`
197			`wire [7:0] reg_uart_rdata ;`
198	2	dinesha	`wire reg_uart_ack ;`
199
200			`wire [14:0] reg_spi_addr ;`
201	11	dinesha	`wire [7:0] reg_spi_wdata ;`
202			`wire [7:0] reg_spi_rdata ;`
203	2	dinesha	`wire reg_spi_ack ;`
204
205
206			`wire [7:0] p0 ;`
207			`wire [7:0] p1 ;`
208			`wire [7:0] p2 ;`
209			`wire [7:0] p3 ;`
210
211
212	11	dinesha	`wire [7:0] reg_rdata = (reg_uart_ack) ? reg_uart_rdata :`
213	2	dinesha	`(reg_spi_ack) ? reg_spi_rdata : 'h0;`
214
215			`wire reg_ack = reg_uart_ack \| reg_spi_ack;`
216
217
218			`assign reset_out_n = gen_resetn;`
219
220			`assign wb_xram_adr[15] = 0;`
221
222			`//-------------------------------------------`
223			`// clock-gen instantiation`
224			`//-------------------------------------------`
225			`clkgen u_clkgen (`
226			`. reset_n (reset_n ),`
227			`. fastsim_mode (fastsim_mode ),`
228			`. mastermode (mastermode ),`
229			`. xtal_clk (xtal_clk ),`
230			`. clkout (clkout ),`
231			`. gen_resetn (gen_resetn ),`
232	25	dinesha	`. risc_resetn (risc_resetn ),`
233	2	dinesha	`. app_clk (app_clk ),`
234			`. uart_ref_clk (uart_clk_16x )`
235
236			`);`
237
238	19	dinesha	`/*********** Message Handler ********/`
239	2	dinesha
240	19	dinesha	`msg_handler_top u_msg_hand_top (`
241			`. line_reset_n (reset_n ),`
242			`. line_clk (app_clk ),`
243	2	dinesha
244	19	dinesha	`// Towards Register Interface`
245			`. reg_addr (mh_reg_addr ),`
246			`. reg_wr (mh_reg_wr ),`
247			`. reg_wdata (mh_reg_wdata ),`
248			`. reg_req (mh_reg_cs ),`
249			`. reg_ack (mh_reg_ack ),`
250			`. reg_rdata (mh_reg_rdata ),`
251
252			`// Status information`
253			`. frm_error ( ),`
254			`. par_error ( ),`
255
256			`. baud_clk_16x ( ),`
257
258			`// Line Interface`
259			`. rxd (uart0_rxd ),`
260			`. txd (uart0_txd )`
261
262
263			`);`
264
265
266
267			`/***************************************/`
268	11	dinesha	`wire [7:0] wb_master2_rdata;`
269	2	dinesha
270	11	dinesha	`assign wbd_risc_rdata = wb_master2_rdata[7:0];`
271	2	dinesha
272			`//------------------------------`
273			`// 8051 Data Memory Map`
274			`// 0x0000 to 0x7FFFF - Data Memory`
275			`// 0x8000 to 0x8FFF - SPI`
276			`// 0x9000 to 0x9FFF - UART`
277			`//--------------------------------------------------------------`
278			`// Target ID Mapping`
279	10	dinesha	`// 4'b0010 -- UART`
280			`// 4'b0001 -- SPI core`
281			`// 4'b0000 -- External RAM`
282	2	dinesha	`//--------------------------------------------------------------`
283			`//`
284	10	dinesha	`wire [3:0] wbd_tar_id = (wbd_risc_adr[15] == 1'b0 ) ? 4'b0000 :`
285			`(wbd_risc_adr[15:12] == 4'b1000 ) ? 4'b0001 :`
286			`(wbd_risc_adr[15:12] == 4'b1001 ) ? 4'b0010 : 4'b0000;`
287	2	dinesha
288	19	dinesha	`wire [3:0] mh_tar_id = (mh_reg_addr[15] == 1'b0 ) ? 4'b0000 :`
289			`(mh_reg_addr[15:12] == 4'b1000 ) ? 4'b0001 :`
290			`(mh_reg_addr[15:12] == 4'b1001 ) ? 4'b0010 : 4'b0000;`
291
292			`wb_crossbar #(.WB_MASTER(3),`
293	10	dinesha	`.WB_SLAVE(3),`
294	11	dinesha	`.D_WD(8),`
295			`.BE_WD(1),`
296			`.ADR_WD(15),`
297	2	dinesha	`.TAR_WD(4))`
298			`u_wb_crossbar (`
299
300			`.rst_n (gen_resetn ),`
301			`.clk (app_clk ),`
302
303
304			`// Master Interface Signal`
305	19	dinesha	`.wbd_taddr_master ({mh_tar_id,`
306			`wbd_tar_id,`
307	2	dinesha	`ext_reg_tid }),`
308
309	19	dinesha	`.wbd_din_master ({mh_reg_wdata,`
310			`wbd_risc_wdata[7:0],`
311	2	dinesha	`ext_reg_wdata }`
312			`),`
313
314	19	dinesha	`.wbd_dout_master ({mh_reg_rdata,`
315			`wb_master2_rdata,`
316	2	dinesha	`ext_reg_rdata}),`
317
318	19	dinesha	`.wbd_adr_master ({mh_reg_addr[14:0],`
319			`wbd_risc_adr[14:0],`
320	11	dinesha	`ext_reg_addr[14:0]}),`
321	2	dinesha
322	19	dinesha	`.wbd_be_master ({1'b1,1'b1,1'b1}),`
323	2	dinesha
324	19	dinesha	`.wbd_we_master ({mh_reg_wr,`
325			`wbd_risc_we,`
326			`ext_reg_wr } ),`
327	2	dinesha
328	19	dinesha	`.wbd_ack_master ({mh_reg_ack,`
329			`wbd_risc_ack,`
330	2	dinesha	`ext_reg_ack } ),`
331
332	19	dinesha	`.wbd_stb_master ({mh_reg_cs,`
333			`wbd_risc_stb,`
334	2	dinesha	`ext_reg_cs} ),`
335
336	19	dinesha	`.wbd_cyc_master ({mh_reg_cs\| mh_reg_ack,`
337			`wbd_risc_stb\|wbd_risc_ack,`
338	2	dinesha	`ext_reg_cs\|ext_reg_ack }),`
339
340			`.wbd_err_master (),`
341			`.wbd_rty_master (),`
342
343			`// Slave Interface Signal`
344			`.wbd_din_slave ({reg_uart_wdata,`
345			`reg_spi_wdata,`
346	10	dinesha	`wb_xram_wdata`
347	2	dinesha	`}),`
348
349			`.wbd_dout_slave ({reg_uart_rdata,`
350			`reg_spi_rdata,`
351	11	dinesha	`wb_xram_rdata`
352	2	dinesha	`}),`
353
354	11	dinesha	`.wbd_adr_slave ({reg_uart_addr[14:0],`
355			`reg_spi_addr[14:0],`
356			`wb_xram_adr[14:0]}`
357	2	dinesha	`),`
358
359	11	dinesha	`.wbd_be_slave (),`
360	2	dinesha
361			`.wbd_we_slave ({reg_uart_wr,`
362			`reg_spi_wr,`
363	10	dinesha	`wb_xram_wr`
364	2	dinesha	`}),`
365
366			`.wbd_ack_slave ({reg_uart_ack,`
367			`reg_spi_ack,`
368	10	dinesha	`wb_xram_ack`
369	2	dinesha	`}),`
370			`.wbd_stb_slave ({reg_uart_cs,`
371			`reg_spi_cs,`
372	10	dinesha	`wb_xram_stb`
373	2	dinesha	`}),`
374
375			`.wbd_cyc_slave (),`
376			`.wbd_err_slave (),`
377			`.wbd_rty_slave ()`
378			`);`
379
380
381
382			`//-------------------------------------`
383			`// UART core instantiation`
384			`//-------------------------------------`
385
386			`uart_core u_uart_core`
387
388			`(`
389			`. app_reset_n (gen_resetn ),`
390			`. app_clk (app_clk ),`
391
392
393			`// Reg Bus Interface Signal`
394			`. reg_cs (reg_uart_cs ),`
395			`. reg_wr (reg_uart_wr ),`
396	11	dinesha	`. reg_addr (reg_uart_addr[3:0] ),`
397	2	dinesha	`. reg_wdata (reg_uart_wdata ),`
398	11	dinesha	`. reg_be (1'b1 ),`
399	2	dinesha
400			`// Outputs`
401			`. reg_rdata (reg_uart_rdata ),`
402			`. reg_ack (reg_uart_ack ),`
403
404
405
406			`// Line Interface`
407	19	dinesha	`. si (uart1_rxd ),`
408			`. so (uart1_txd )`
409	2	dinesha
410			`);`
411
412
413			`//--------------------------------`
414			`// SPI core instantiation`
415			`//--------------------------------`
416
417
418			`spi_core u_spi_core (`
419
420			`. clk (app_clk ),`
421			`. reset_n (gen_resetn ),`
422
423			`// Reg Bus Interface Signal`
424			`. reg_cs (reg_spi_cs ),`
425			`. reg_wr (reg_spi_wr ),`
426	11	dinesha	`. reg_addr (reg_spi_addr[3:0] ),`
427	2	dinesha	`. reg_wdata (reg_spi_wdata ),`
428	11	dinesha	`. reg_be (1'b1 ),`
429	2	dinesha
430			`// Outputs`
431			`. reg_rdata (reg_spi_rdata ),`
432			`. reg_ack (reg_spi_ack ),`
433
434
435			`. sck (spi_sck ),`
436			`. so (spi_so ),`
437			`. si (spi_si ),`
438			`. cs_n (spi_cs_n )`
439
440			`);`
441
442
443
444			`oc8051_top u_8051_core (`
445	25	dinesha	`. resetn (risc_resetn ),`
446	2	dinesha	`. wb_clk_i (app_clk ),`
447
448			`//interface to data ram`
449			`. wbd_dat_i (wbd_risc_rdata ),`
450			`. wbd_dat_o (wbd_risc_wdata ),`
451			`. wbd_adr_o (wbd_risc_adr ),`
452			`. wbd_we_o (wbd_risc_we ),`
453			`. wbd_ack_i (wbd_risc_ack ),`
454			`. wbd_stb_o (wbd_risc_stb ),`
455			`. wbd_cyc_o (wbd_risc_cyc ),`
456			`. wbd_err_i (wbd_risc_err ),`
457
458			`// interrupt interface`
459			`. int0_i ( ),`
460			`. int1_i ( ),`
461
462
463			`// port interface`
464			`ifdef OC8051_PORTS
465			`ifdef OC8051_PORT0
466			`.p0_i ( p0 ),`
467			`.p0_o ( p0 ),`
468			`endif
469
470			`ifdef OC8051_PORT1
471			`.p1_i ( p1 ),`
472			`.p1_o ( p1 ),`
473			`endif
474
475			`ifdef OC8051_PORT2
476			`.p2_i ( p2 ),`
477			`.p2_o ( p2 ),`
478			`endif
479
480			`ifdef OC8051_PORT3
481			`.p3_i ( p3 ),`
482			`.p3_o ( p3 ),`
483			`endif
484			`endif
485
486			`// serial interface`
487			`ifdef OC8051_UART
488			`.rxd_i ( ),`
489			`.txd_o ( ),`
490			`endif
491
492			`// counter interface`
493			`ifdef OC8051_TC01
494			`.t0_i ( ),`
495			`.t1_i ( ),`
496			`endif
497
498			`ifdef OC8051_TC2
499			`.t2_i ( ),`
500			`.t2ex_i ( ),`

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