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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OMS 8051 Digital core Module                                ////
////                                                              ////
////  This file is part of the OMS 8051 cores project             ////
////  http://www.opencores.org/cores/oms8051mini/                 ////
////                                                              ////
////  Description                                                 ////
////  OMS 8051 definitions.                                       ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
////  Revision : Nov 26, 2016                                     //// 
////                                                              ////
//////////////////////////////////////////////////////////////////////
//     v0.0 - Dinesh A, 26th Nov 2016
//          1. MAC related logic are remved
//     v0.1 - Dinesh A, 1st Dec 2016
//          1. RAM and ROM are internally connected to interconnect
//          2. Memory Map Change
//          3. Remove the External ROM Option & Enabled Internal ROM
//     v0.2 - Dinesh A, 9st Dec 2016
//          1. Bus interface is changed from 32 bit to 8 bit
//     v0.3 - Dinesh A, 21 Dec 2016
//          1. Uart Message Handler is integrated 
//          2. Message handler is connected as Register Master to 
//             Inter-connect
//     v0.4 - Dinesh A, 6th Jan 2017
//          1. I2C Master Core is integrated
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
`include "top_defines.v"
module digital_core  (
 
             aresetn                ,
             scan_mode              ,
             scan_enable             ,
             fastsim_mode           ,
             mastermode             ,
             xtal_clk               ,
             clkout                 ,
             reset_out_n            ,
             ea_in                  ,
 
        // Reg Bus Interface Signal
             ext_reg_cs             ,
             ext_reg_tid            ,
             ext_reg_wr             ,
             ext_reg_addr           ,
             ext_reg_wdata          ,
 
            // Outputs
             ext_reg_rdata          ,
             ext_reg_ack            ,
 
 
 
       // UART Line Interface
             uart0_txd              ,
             uart0_rxd              ,
 
             uart1_txd              ,
             uart1_rxd              ,
 
             spi_sck                ,
             spi_so                 ,
             spi_si                 ,
             spi_cs_n               ,
 
        // i2cm clock line
             i2cm_scl_i             ,
             i2cm_scl_o             ,
             i2cm_scl_oen           ,
 
        // i2cm data line
             i2cm_sda_i             ,
             i2cm_sda_o             ,
             i2cm_sda_oen
 
 
        );
 
 
//----------------------------------------
// Global Clock Defination
//----------------------------------------
input            aresetn               ; // Async Active Low Reset           
input            scan_mode             ; // scan mode
input            scan_enable           ; // scan enable
input            fastsim_mode          ; // Fast Sim Mode
input            mastermode            ; // 1 : Risc master mode
input            ea_in                  ; // input for external access (ea signal)
                                          // ea=0 program is in external rom
                                          // ea=1 program is in internal rom
 
input            xtal_clk              ; // xtal clock 25Mhz
output           clkout                ; // clock output
output           reset_out_n           ; // clock output
 
//---------------------------------
// Reg Bus Interface Signal
//---------------------------------
input            ext_reg_cs            ;
input            ext_reg_wr            ;
input [3:0]      ext_reg_tid           ;
input [14:0]     ext_reg_addr          ;
input [7:0]      ext_reg_wdata         ;
 
// Outputs
output [7:0]     ext_reg_rdata         ;
output           ext_reg_ack           ;
 
 
 
//----------------------------------------
// UART Line Interface
//----------------------------------------
input            uart0_rxd             ; // serial in
output           uart0_txd             ; // serial out
 
input            uart1_rxd             ; // serial in
output           uart1_txd             ; // serial out
 
//----------------------------------------
// SPI Line Interface
//----------------------------------------
 
output           spi_sck                ; // clock
output           spi_so                 ; // data out
input            spi_si                 ; // data in
output  [3:0]    spi_cs_n               ; // chip select
 
//----------------------------------------
// i2cm clock line
//----------------------------------------
input            i2cm_scl_i             ;
output           i2cm_scl_o             ;
output           i2cm_scl_oen           ;
 
//----------------------------------------
// i2cm data line
//----------------------------------------
input            i2cm_sda_i             ;
output           i2cm_sda_o             ;
output           i2cm_sda_oen           ;
 
//----------------------------------------
// 8051 core RAM related signals
//---------------------------------------
wire [15:0]      wb_xram_adr            ; // data-ram address
wire             wb_xram_ack            ; // data-ram acknowlage
wire             wb_xram_err            ; // data-ram error
wire             wb_xram_wr             ; // data-ram error
wire [7:0]       wb_xram_rdata          ; // ram data input
wire [7:0]       wb_xram_wdata          ; // ram data input
 
wire             wb_xram_stb            ; // data-ram strobe
wire             wb_xram_cyc            ; // data-ram cycle
 
//----------------------------------------
// i2CM Wishbone I/F
//---------------------------------------
wire [15:0]      wb_i2cm_addr           ; // data-ram address
wire             wb_i2cm_ack            ; // data-ram acknowlage
wire             wb_i2cm_err            ; // data-ram error
wire             wb_i2cm_we             ; // data-ram error
wire [7:0]       wb_i2cm_rdata          ; // ram data input
wire [7:0]       wb_i2cm_wdata          ; // ram data input
 
wire             wb_i2cm_stb            ; // data-ram strobe
wire             wb_i2cm_cyc            ; // data-ram cycle
 
//----------------------------------------
// Message Controller Reg Master
//---------------------------------------
wire             mh_reg_cs              ;
wire             mh_reg_wr              ;
wire  [3:0]      mh_reg_tid             ;
wire  [15:0]     mh_reg_addr            ;
wire  [7:0]      mh_reg_wdata           ;
 
// Outputs
wire  [7:0]      mh_reg_rdata           ;
wire             mh_reg_ack             ;
 
//-----------------------------
// wire Decleration
//-----------------------------
wire             gen_resetn             ;
 
 
//---------------------------------------------
// 8051 Instruction RAM interface
//---------------------------------------------
wire    [15:0]   wbd_risc_adr           ;
wire    [7:0]    wbd_risc_rdata         ;
wire    [7:0]    wbd_risc_wdata         ;
 
 
wire    [14:0]   reg_uart_addr          ;
wire    [7:0]    reg_uart_wdata         ;
wire    [7:0]    reg_uart_rdata         ;
wire             reg_uart_ack           ;
 
wire    [14:0]   reg_spi_addr           ;
wire    [7:0]    reg_spi_wdata          ;
wire    [7:0]    reg_spi_rdata          ;
wire             reg_spi_ack            ;
 
 
wire    [7:0]    p0              ;
wire    [7:0]    p1              ;
wire    [7:0]    p2              ;
wire    [7:0]    p3              ;
 
 
wire [7:0] reg_rdata = (reg_uart_ack) ? reg_uart_rdata :
                        (reg_spi_ack)  ? reg_spi_rdata : 'h0;
 
wire reg_ack = reg_uart_ack | reg_spi_ack;
 
 
assign reset_out_n = gen_resetn;
 
assign wb_xram_adr[15]    = 0;
 
//-------------------------------------------
// clock-gen  instantiation
//-------------------------------------------
clkgen u_clkgen (
               . aresetn                (aresetn               ),
               . fastsim_mode           (fastsim_mode          ),
               . mastermode             (mastermode            ),
               . xtal_clk               (xtal_clk              ),
               . clkout                 (clkout                ),
               . gen_resetn             (gen_resetn            ),
               . risc_resetn            (risc_resetn           ),
               . app_clk                (app_clk               ),
               . uart_ref_clk           (uart_clk_16x          )
 
              );
 
/************* Message Handler **********/
 
msg_handler_top u_msg_hand_top (
              . line_reset_n            (aresetn               ),
              . line_clk                (app_clk               ),
 
      // Towards Register Interface
              . reg_addr                (mh_reg_addr           ),
              . reg_wr                  (mh_reg_wr             ),
              . reg_wdata               (mh_reg_wdata          ),
              . reg_req                 (mh_reg_cs             ),
              . reg_ack                 (mh_reg_ack            ),
              . reg_rdata               (mh_reg_rdata          ),
 
       // Status information
              . frm_error               (                      ),
              . par_error               (                      ),
 
              . baud_clk_16x            (                      ),
 
       // Line Interface
              . rxd                     (uart0_rxd             ),
              . txd                     (uart0_txd             )
 
 
     );
 
 
 
/***************************************/
wire [7:0] wb_master2_rdata;
 
assign     wbd_risc_rdata = wb_master2_rdata[7:0];
 
//------------------------------
// 8051 Data Memory Map
// 0x0000 to 0x7FFFF  - Data Memory
// 0x8000 to 0x8FFF   - SPI 
// 0x9000 to 0x9FFF   - UART
// 0xA000 to 0xAFFF   - I2CM
//--------------------------------------------------------------
// Target ID Mapping
// 4'b0011 -- I2CM
// 4'b0010 -- UART
// 4'b0001 -- SPI core
// 4'b0000 -- External RAM
//--------------------------------------------------------------
// 
wire [3:0] wbd_tar_id     = (wbd_risc_adr[15]    == 1'b0 ) ? 4'b0000 :
                            (wbd_risc_adr[15:12] == 4'b1000 ) ? 4'b0001 :
                            (wbd_risc_adr[15:12] == 4'b1001 ) ? 4'b0010 :
                            (wbd_risc_adr[15:12] == 4'b1010 ) ? 4'b0011 : 4'b0000;
 
wire [3:0] mh_tar_id     = (mh_reg_addr[15]    == 1'b0 ) ? 4'b0000 :
                           (mh_reg_addr[15:12] == 4'b1000 ) ? 4'b0001 :
                           (mh_reg_addr[15:12] == 4'b1001 ) ? 4'b0010 :
                           (mh_reg_addr[15:12] == 4'b1010 ) ? 4'b0011 : 4'b0000;
 
wb_crossbar #(.WB_MASTER(3),
              .WB_SLAVE(4),
              .D_WD(8),
              .BE_WD(1),
              .ADR_WD(15),
              .TAR_WD(4))
              u_wb_crossbar (
 
              .rst_n                    (gen_resetn           ),
              .clk                      (app_clk              ),
 
 
    // Master Interface Signal
              .wbd_taddr_master         ({mh_tar_id,
                                          wbd_tar_id,
                                          ext_reg_tid }),
 
              .wbd_din_master           ({mh_reg_wdata,
                                          wbd_risc_wdata[7:0],
                                          ext_reg_wdata }
                                         ),
 
              .wbd_dout_master          ({mh_reg_rdata,
                                          wb_master2_rdata,
                                          ext_reg_rdata}),
 
              .wbd_adr_master           ({mh_reg_addr[14:0],
                                          wbd_risc_adr[14:0],
                                          ext_reg_addr[14:0]}),
 
              .wbd_be_master            ({1'b1,1'b1,1'b1}),
 
              .wbd_we_master            ({mh_reg_wr,
                                          wbd_risc_we,
                                          ext_reg_wr }   ),
 
              .wbd_ack_master           ({mh_reg_ack,
                                          wbd_risc_ack,
                                          ext_reg_ack } ),
 
              .wbd_stb_master           ({mh_reg_cs,
                                          wbd_risc_stb,
                                          ext_reg_cs} ),
 
              .wbd_cyc_master           ({mh_reg_cs| mh_reg_ack,
                                          wbd_risc_stb|wbd_risc_ack,
                                          ext_reg_cs|ext_reg_ack }),
 
              .wbd_err_master           (),
              .wbd_rty_master           (),
 
    // Slave Interface Signal
              .wbd_din_slave            ({wb_i2cm_wdata,
                                          reg_uart_wdata,
                                          reg_spi_wdata,
                                          wb_xram_wdata
                                          }),
 
              .wbd_dout_slave           ({wb_i2cm_rdata,
                                          reg_uart_rdata,
                                          reg_spi_rdata,
                                          wb_xram_rdata
                                         }),
 
              .wbd_adr_slave            ({wb_i2cm_addr[14:0],
                                          reg_uart_addr[14:0],
                                          reg_spi_addr[14:0],
                                          wb_xram_adr[14:0]
                                          }
                                        ),
 
              .wbd_be_slave             (),
 
              .wbd_we_slave             ({wb_i2cm_we,
                                          reg_uart_wr,
                                          reg_spi_wr,
                                          wb_xram_wr
                                          }),
 
              .wbd_ack_slave            ({wb_i2cm_ack,
                                          reg_uart_ack,
                                          reg_spi_ack,
                                          wb_xram_ack
                                         }),
              .wbd_stb_slave            ({wb_i2cm_stb,
                                          reg_uart_cs,
                                          reg_spi_cs,
                                          wb_xram_stb
 
                                         }),
 
              .wbd_cyc_slave            ({wb_i2cm_cyc,
                                          wb_uart_cyc,
                                          wb_spi_cyc,
                                          wb_xram_cyc
                                          }),
              .wbd_err_slave            (),
              .wbd_rty_slave            ()
         );
 
 
 
//-------------------------------------
// UART core instantiation
//-------------------------------------
 
uart_core  u_uart_core
 
     (
          . app_reset_n                 (gen_resetn            ),
          . app_clk                     (app_clk               ),
 
 
        // Reg Bus Interface Signal
          . reg_cs                      (reg_uart_cs           ),
          . reg_wr                      (reg_uart_wr           ),
          . reg_addr                    (reg_uart_addr[3:0]    ),
          . reg_wdata                   (reg_uart_wdata        ),
          . reg_be                      (1'b1                  ),
 
            // Outputs
          . reg_rdata                   (reg_uart_rdata        ),
          . reg_ack                     (reg_uart_ack          ),
 
 
 
       // Line Interface
          . si                          (uart1_rxd             ),
          . so                          (uart1_txd             )
 
     );
 
 
//--------------------------------
// SPI core instantiation
//--------------------------------
 
 
spi_core u_spi_core (
 
          . clk                         (app_clk               ),
          . reset_n                     (gen_resetn            ),
 
        // Reg Bus Interface Signal
          . reg_cs                      (reg_spi_cs            ),
          . reg_wr                      (reg_spi_wr            ),
          . reg_addr                    (reg_spi_addr[3:0]     ),
          . reg_wdata                   (reg_spi_wdata         ),
          . reg_be                      (1'b1                  ),
 
            // Outputs
          . reg_rdata                   (reg_spi_rdata         ),
          . reg_ack                     (reg_spi_ack           ),
 
 
          . sck                         (spi_sck               ),
          . so                          (spi_so                ),
          . si                          (spi_si                ),
          . cs_n                        (spi_cs_n              )
 
           );
 
/******************************************************
*   I2C Master Core
*   ***************************************************/
i2cm_top  i_i2cm_core (
        // wishbone signals
                .wb_clk_i                (app_clk              ),
                .sresetn                 (gen_resetn           ),
                .aresetn                 (aresetn              ),
                .wb_adr_i                (wb_i2cm_addr[2:0]    ),
                .wb_dat_i                (wb_i2cm_wdata        ),
                .wb_dat_o                (wb_i2cm_rdata        ),
                .wb_we_i                 (wb_i2cm_we           ),
                .wb_stb_i                (wb_i2cm_stb          ),
                .wb_cyc_i                (wb_i2cm_cyc          ),
                .wb_ack_o                (wb_i2cm_ack          ),
                .wb_inta_o               (i2cm_inta            ),
 
        // I2C signals
        // i2c clock line
                .scl_pad_i              (i2cm_scl_i            ),
                .scl_pad_o              (i2cm_scl_o            ),
                .scl_padoen_o           (i2cm_scl_oen          ),
 
        // i2c data line
                .sda_pad_i              (i2cm_sda_i            ),
                .sda_pad_o              (i2cm_sda_o            ),
                .sda_padoen_o           (i2cm_sda_oen          )
 
         );
 
 
 
/******************************************************
*   8051 Core
*******************************************************/
 
oc8051_top u_8051_core (
          . resetn                      (risc_resetn           ),
          . wb_clk_i                    (app_clk               ),
 
//interface to data ram
          . wbd_dat_i                   (wbd_risc_rdata        ),
          . wbd_dat_o                   (wbd_risc_wdata        ),
          . wbd_adr_o                   (wbd_risc_adr          ),
          . wbd_we_o                    (wbd_risc_we           ),
          . wbd_ack_i                   (wbd_risc_ack          ),
          . wbd_stb_o                   (wbd_risc_stb          ),
          . wbd_cyc_o                   (wbd_risc_cyc          ),
          . wbd_err_i                   (wbd_risc_err          ),
 
// interrupt interface
          . int0_i                      (                      ),
          . int1_i                      (                      ),
 
 
// port interface
  `ifdef OC8051_PORTS
        `ifdef OC8051_PORT0
          .p0_i                         ( p0                    ),
          .p0_o                         ( p0                    ),
        `endif
 
        `ifdef OC8051_PORT1
           .p1_i                        ( p1                    ),
           .p1_o                        ( p1                    ),
        `endif
 
        `ifdef OC8051_PORT2
           .p2_i                        ( p2                    ),
           .p2_o                        ( p2                    ),
        `endif
 
        `ifdef OC8051_PORT3
           .p3_i                        ( p3                    ),
           .p3_o                        ( p3                    ),
        `endif
  `endif
 
// serial interface
        `ifdef OC8051_UART
           .rxd_i                       (                      ),
           .txd_o                       (                      ),
        `endif
 
// counter interface
        `ifdef OC8051_TC01
           .t0_i                        (                      ),
           .t1_i                        (                      ),
        `endif
 
        `ifdef OC8051_TC2
           .t2_i                        (                      ),
           .t2ex_i                      (                      ),
        `endif
 
// BIST
`ifdef OC8051_BIST
            .scanb_rst                  (                      ),
            .scanb_clk                  (                      ),
            .scanb_si                   (                      ),
            .scanb_so                   (                      ),
            .scanb_en                   (                      ),
`endif
// external access (active low)
            .ea_in                      (ea_in                 )
         );
 
//
// external data ram
//
oc8051_xram oc8051_xram1 (
          .clk               (app_clk       ),
          .rst               (!aresetn      ),
          .wr                (wb_xram_wr    ),
          .addr              (wb_xram_adr   ),
          .data_in           (wb_xram_wdata ),
          .data_out          (wb_xram_rdata ),
          .ack               (wb_xram_ack   ),
          .stb               (wb_xram_stb   )
      );
 
 
defparam oc8051_xram1.DELAY = 2;
endmodule

Line No.	Rev	Author	Line
1	2	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3	11	dinesha	`//// OMS 8051 Digital core Module ////`
4	2	dinesha	`//// ////`
5			`//// This file is part of the OMS 8051 cores project ////`
6			`//// http://www.opencores.org/cores/oms8051mini/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// OMS 8051 definitions. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Dinesh Annayya, dinesha@opencores.org ////`
16			`//// ////`
17			`//// Revision : Nov 26, 2016 ////`
18			`//// ////`
19			`//////////////////////////////////////////////////////////////////////`
20	10	dinesha	`// v0.0 - Dinesh A, 26th Nov 2016`
21	2	dinesha	`// 1. MAC related logic are remved`
22	10	dinesha	`// v0.1 - Dinesh A, 1st Dec 2016`
23			`// 1. RAM and ROM are internally connected to interconnect`
24			`// 2. Memory Map Change`
25			`// 3. Remove the External ROM Option & Enabled Internal ROM`
26	11	dinesha	`// v0.2 - Dinesh A, 9st Dec 2016`
27			`// 1. Bus interface is changed from 32 bit to 8 bit`
28	19	dinesha	`// v0.3 - Dinesh A, 21 Dec 2016`
29			`// 1. Uart Message Handler is integrated`
30			`// 2. Message handler is connected as Register Master to`
31			`// Inter-connect`
32	27	dinesha	`// v0.4 - Dinesh A, 6th Jan 2017`
33			`// 1. I2C Master Core is integrated`
34	2	dinesha	`//////////////////////////////////////////////////////////////////////`
35			`//// ////`
36			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
37			`//// ////`
38			`//// This source file may be used and distributed without ////`
39			`//// restriction provided that this copyright statement is not ////`
40			`//// removed from the file and that any derivative work contains ////`
41			`//// the original copyright notice and the associated disclaimer. ////`
42			`//// ////`
43			`//// This source file is free software; you can redistribute it ////`
44			`//// and/or modify it under the terms of the GNU Lesser General ////`
45			`//// Public License as published by the Free Software Foundation; ////`
46			`//// either version 2.1 of the License, or (at your option) any ////`
47			`//// later version. ////`
48			`//// ////`
49			`//// This source is distributed in the hope that it will be ////`
50			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
51			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
52			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
53			`//// details. ////`
54			`//// ////`
55			`//// You should have received a copy of the GNU Lesser General ////`
56			`//// Public License along with this source; if not, download it ////`
57			`//// from http://www.opencores.org/lgpl.shtml ////`
58			`//// ////`
59			`//////////////////////////////////////////////////////////////////////`
60
61			`include "top_defines.v"
62			`module digital_core (`
63
64	27	dinesha	`aresetn ,`
65	2	dinesha	`scan_mode ,`
66			`scan_enable ,`
67			`fastsim_mode ,`
68			`mastermode ,`
69			`xtal_clk ,`
70			`clkout ,`
71			`reset_out_n ,`
72	10	dinesha	`ea_in ,`
73	2	dinesha
74			`// Reg Bus Interface Signal`
75			`ext_reg_cs ,`
76			`ext_reg_tid ,`
77			`ext_reg_wr ,`
78			`ext_reg_addr ,`
79			`ext_reg_wdata ,`
80
81			`// Outputs`
82			`ext_reg_rdata ,`
83			`ext_reg_ack ,`
84
85
86
87			`// UART Line Interface`
88	19	dinesha	`uart0_txd ,`
89			`uart0_rxd ,`
90	2	dinesha
91	19	dinesha	`uart1_txd ,`
92			`uart1_rxd ,`
93	2	dinesha
94			`spi_sck ,`
95			`spi_so ,`
96			`spi_si ,`
97	27	dinesha	`spi_cs_n ,`
98	2	dinesha
99	27	dinesha	`// i2cm clock line`
100			`i2cm_scl_i ,`
101			`i2cm_scl_o ,`
102			`i2cm_scl_oen ,`
103	2	dinesha
104	27	dinesha	`// i2cm data line`
105			`i2cm_sda_i ,`
106			`i2cm_sda_o ,`
107			`i2cm_sda_oen`
108	2	dinesha
109
110			`);`
111
112
113			`//----------------------------------------`
114			`// Global Clock Defination`
115			`//----------------------------------------`
116	27	dinesha	`input aresetn ; // Async Active Low Reset`
117	2	dinesha	`input scan_mode ; // scan mode`
118			`input scan_enable ; // scan enable`
119			`input fastsim_mode ; // Fast Sim Mode`
120			`input mastermode ; // 1 : Risc master mode`
121	10	dinesha	`input ea_in ; // input for external access (ea signal)`
122			`// ea=0 program is in external rom`
123			`// ea=1 program is in internal rom`
124	2	dinesha
125			`input xtal_clk ; // xtal clock 25Mhz`
126			`output clkout ; // clock output`
127			`output reset_out_n ; // clock output`
128
129			`//---------------------------------`
130			`// Reg Bus Interface Signal`
131			`//---------------------------------`
132			`input ext_reg_cs ;`
133			`input ext_reg_wr ;`
134			`input [3:0] ext_reg_tid ;`
135			`input [14:0] ext_reg_addr ;`
136	11	dinesha	`input [7:0] ext_reg_wdata ;`
137	2	dinesha
138			`// Outputs`
139	11	dinesha	`output [7:0] ext_reg_rdata ;`
140	2	dinesha	`output ext_reg_ack ;`
141
142
143
144			`//----------------------------------------`
145			`// UART Line Interface`
146			`//----------------------------------------`
147	19	dinesha	`input uart0_rxd ; // serial in`
148			`output uart0_txd ; // serial out`
149	2	dinesha
150	19	dinesha	`input uart1_rxd ; // serial in`
151			`output uart1_txd ; // serial out`
152
153	2	dinesha	`//----------------------------------------`
154			`// SPI Line Interface`
155			`//----------------------------------------`
156
157			`output spi_sck ; // clock`
158			`output spi_so ; // data out`
159			`input spi_si ; // data in`
160			`output [3:0] spi_cs_n ; // chip select`
161
162	27	dinesha	`//----------------------------------------`
163			`// i2cm clock line`
164			`//----------------------------------------`
165			`input i2cm_scl_i ;`
166			`output i2cm_scl_o ;`
167			`output i2cm_scl_oen ;`
168	2	dinesha
169			`//----------------------------------------`
170	27	dinesha	`// i2cm data line`
171			`//----------------------------------------`
172			`input i2cm_sda_i ;`
173			`output i2cm_sda_o ;`
174			`output i2cm_sda_oen ;`
175
176			`//----------------------------------------`
177	2	dinesha	`// 8051 core RAM related signals`
178			`//---------------------------------------`
179	10	dinesha	`wire [15:0] wb_xram_adr ; // data-ram address`
180			`wire wb_xram_ack ; // data-ram acknowlage`
181			`wire wb_xram_err ; // data-ram error`
182			`wire wb_xram_wr ; // data-ram error`
183	11	dinesha	`wire [7:0] wb_xram_rdata ; // ram data input`
184			`wire [7:0] wb_xram_wdata ; // ram data input`
185	2	dinesha
186	10	dinesha	`wire wb_xram_stb ; // data-ram strobe`
187			`wire wb_xram_cyc ; // data-ram cycle`
188	2	dinesha
189	27	dinesha	`//----------------------------------------`
190			`// i2CM Wishbone I/F`
191			`//---------------------------------------`
192			`wire [15:0] wb_i2cm_addr ; // data-ram address`
193			`wire wb_i2cm_ack ; // data-ram acknowlage`
194			`wire wb_i2cm_err ; // data-ram error`
195			`wire wb_i2cm_we ; // data-ram error`
196			`wire [7:0] wb_i2cm_rdata ; // ram data input`
197			`wire [7:0] wb_i2cm_wdata ; // ram data input`
198	2	dinesha
199	27	dinesha	`wire wb_i2cm_stb ; // data-ram strobe`
200			`wire wb_i2cm_cyc ; // data-ram cycle`
201
202	19	dinesha	`//----------------------------------------`
203			`// Message Controller Reg Master`
204			`//---------------------------------------`
205			`wire mh_reg_cs ;`
206			`wire mh_reg_wr ;`
207			`wire [3:0] mh_reg_tid ;`
208			`wire [15:0] mh_reg_addr ;`
209			`wire [7:0] mh_reg_wdata ;`
210	2	dinesha
211	19	dinesha	`// Outputs`
212			`wire [7:0] mh_reg_rdata ;`
213			`wire mh_reg_ack ;`
214
215	2	dinesha	`//-----------------------------`
216			`// wire Decleration`
217			`//-----------------------------`
218			`wire gen_resetn ;`
219
220
221			`//---------------------------------------------`
222			`// 8051 Instruction RAM interface`
223			`//---------------------------------------------`
224			`wire [15:0] wbd_risc_adr ;`
225			`wire [7:0] wbd_risc_rdata ;`
226			`wire [7:0] wbd_risc_wdata ;`
227
228
229			`wire [14:0] reg_uart_addr ;`
230	11	dinesha	`wire [7:0] reg_uart_wdata ;`
231			`wire [7:0] reg_uart_rdata ;`
232	2	dinesha	`wire reg_uart_ack ;`
233
234			`wire [14:0] reg_spi_addr ;`
235	11	dinesha	`wire [7:0] reg_spi_wdata ;`
236			`wire [7:0] reg_spi_rdata ;`
237	2	dinesha	`wire reg_spi_ack ;`
238
239
240			`wire [7:0] p0 ;`
241			`wire [7:0] p1 ;`
242			`wire [7:0] p2 ;`
243			`wire [7:0] p3 ;`
244
245
246	11	dinesha	`wire [7:0] reg_rdata = (reg_uart_ack) ? reg_uart_rdata :`
247	2	dinesha	`(reg_spi_ack) ? reg_spi_rdata : 'h0;`
248
249			`wire reg_ack = reg_uart_ack \| reg_spi_ack;`
250
251
252			`assign reset_out_n = gen_resetn;`
253
254			`assign wb_xram_adr[15] = 0;`
255
256			`//-------------------------------------------`
257			`// clock-gen instantiation`
258			`//-------------------------------------------`
259			`clkgen u_clkgen (`
260	27	dinesha	`. aresetn (aresetn ),`
261	2	dinesha	`. fastsim_mode (fastsim_mode ),`
262			`. mastermode (mastermode ),`
263			`. xtal_clk (xtal_clk ),`
264			`. clkout (clkout ),`
265			`. gen_resetn (gen_resetn ),`
266	25	dinesha	`. risc_resetn (risc_resetn ),`
267	2	dinesha	`. app_clk (app_clk ),`
268			`. uart_ref_clk (uart_clk_16x )`
269
270			`);`
271
272	19	dinesha	`/*********** Message Handler ********/`
273	2	dinesha
274	19	dinesha	`msg_handler_top u_msg_hand_top (`
275	27	dinesha	`. line_reset_n (aresetn ),`
276	19	dinesha	`. line_clk (app_clk ),`
277	2	dinesha
278	19	dinesha	`// Towards Register Interface`
279			`. reg_addr (mh_reg_addr ),`
280			`. reg_wr (mh_reg_wr ),`
281			`. reg_wdata (mh_reg_wdata ),`
282			`. reg_req (mh_reg_cs ),`
283			`. reg_ack (mh_reg_ack ),`
284			`. reg_rdata (mh_reg_rdata ),`
285
286			`// Status information`
287			`. frm_error ( ),`
288			`. par_error ( ),`
289
290			`. baud_clk_16x ( ),`
291
292			`// Line Interface`
293			`. rxd (uart0_rxd ),`
294			`. txd (uart0_txd )`
295
296
297			`);`
298
299
300
301			`/***************************************/`
302	11	dinesha	`wire [7:0] wb_master2_rdata;`
303	2	dinesha
304	11	dinesha	`assign wbd_risc_rdata = wb_master2_rdata[7:0];`
305	2	dinesha
306			`//------------------------------`
307			`// 8051 Data Memory Map`
308			`// 0x0000 to 0x7FFFF - Data Memory`
309			`// 0x8000 to 0x8FFF - SPI`
310			`// 0x9000 to 0x9FFF - UART`
311	27	dinesha	`// 0xA000 to 0xAFFF - I2CM`
312	2	dinesha	`//--------------------------------------------------------------`
313			`// Target ID Mapping`
314	27	dinesha	`// 4'b0011 -- I2CM`
315	10	dinesha	`// 4'b0010 -- UART`
316			`// 4'b0001 -- SPI core`
317			`// 4'b0000 -- External RAM`
318	2	dinesha	`//--------------------------------------------------------------`
319			`//`
320	10	dinesha	`wire [3:0] wbd_tar_id = (wbd_risc_adr[15] == 1'b0 ) ? 4'b0000 :`
321			`(wbd_risc_adr[15:12] == 4'b1000 ) ? 4'b0001 :`
322	27	dinesha	`(wbd_risc_adr[15:12] == 4'b1001 ) ? 4'b0010 :`
323			`(wbd_risc_adr[15:12] == 4'b1010 ) ? 4'b0011 : 4'b0000;`
324	2	dinesha
325	19	dinesha	`wire [3:0] mh_tar_id = (mh_reg_addr[15] == 1'b0 ) ? 4'b0000 :`
326			`(mh_reg_addr[15:12] == 4'b1000 ) ? 4'b0001 :`
327	27	dinesha	`(mh_reg_addr[15:12] == 4'b1001 ) ? 4'b0010 :`
328			`(mh_reg_addr[15:12] == 4'b1010 ) ? 4'b0011 : 4'b0000;`
329	19	dinesha
330			`wb_crossbar #(.WB_MASTER(3),`
331	27	dinesha	`.WB_SLAVE(4),`
332	11	dinesha	`.D_WD(8),`
333			`.BE_WD(1),`
334			`.ADR_WD(15),`
335	2	dinesha	`.TAR_WD(4))`
336			`u_wb_crossbar (`
337
338			`.rst_n (gen_resetn ),`
339			`.clk (app_clk ),`
340
341
342			`// Master Interface Signal`
343	19	dinesha	`.wbd_taddr_master ({mh_tar_id,`
344			`wbd_tar_id,`
345	2	dinesha	`ext_reg_tid }),`
346
347	19	dinesha	`.wbd_din_master ({mh_reg_wdata,`
348			`wbd_risc_wdata[7:0],`
349	2	dinesha	`ext_reg_wdata }`
350			`),`
351
352	19	dinesha	`.wbd_dout_master ({mh_reg_rdata,`
353			`wb_master2_rdata,`
354	2	dinesha	`ext_reg_rdata}),`
355
356	19	dinesha	`.wbd_adr_master ({mh_reg_addr[14:0],`
357			`wbd_risc_adr[14:0],`
358	11	dinesha	`ext_reg_addr[14:0]}),`
359	2	dinesha
360	19	dinesha	`.wbd_be_master ({1'b1,1'b1,1'b1}),`
361	2	dinesha
362	19	dinesha	`.wbd_we_master ({mh_reg_wr,`
363			`wbd_risc_we,`
364			`ext_reg_wr } ),`
365	2	dinesha
366	19	dinesha	`.wbd_ack_master ({mh_reg_ack,`
367			`wbd_risc_ack,`
368	2	dinesha	`ext_reg_ack } ),`
369
370	19	dinesha	`.wbd_stb_master ({mh_reg_cs,`
371			`wbd_risc_stb,`
372	2	dinesha	`ext_reg_cs} ),`
373
374	19	dinesha	`.wbd_cyc_master ({mh_reg_cs\| mh_reg_ack,`
375			`wbd_risc_stb\|wbd_risc_ack,`
376	2	dinesha	`ext_reg_cs\|ext_reg_ack }),`
377
378			`.wbd_err_master (),`
379			`.wbd_rty_master (),`
380
381			`// Slave Interface Signal`
382	27	dinesha	`.wbd_din_slave ({wb_i2cm_wdata,`
383			`reg_uart_wdata,`
384	2	dinesha	`reg_spi_wdata,`
385	10	dinesha	`wb_xram_wdata`
386	2	dinesha	`}),`
387
388	27	dinesha	`.wbd_dout_slave ({wb_i2cm_rdata,`
389			`reg_uart_rdata,`
390	2	dinesha	`reg_spi_rdata,`
391	11	dinesha	`wb_xram_rdata`
392	2	dinesha	`}),`
393
394	27	dinesha	`.wbd_adr_slave ({wb_i2cm_addr[14:0],`
395			`reg_uart_addr[14:0],`
396	11	dinesha	`reg_spi_addr[14:0],`
397	27	dinesha	`wb_xram_adr[14:0]`
398			`}`
399	2	dinesha	`),`
400
401	11	dinesha	`.wbd_be_slave (),`
402	2	dinesha
403	27	dinesha	`.wbd_we_slave ({wb_i2cm_we,`
404			`reg_uart_wr,`
405	2	dinesha	`reg_spi_wr,`
406	10	dinesha	`wb_xram_wr`
407	2	dinesha	`}),`
408
409	27	dinesha	`.wbd_ack_slave ({wb_i2cm_ack,`
410			`reg_uart_ack,`
411	2	dinesha	`reg_spi_ack,`
412	10	dinesha	`wb_xram_ack`
413	2	dinesha	`}),`
414	27	dinesha	`.wbd_stb_slave ({wb_i2cm_stb,`
415			`reg_uart_cs,`
416	2	dinesha	`reg_spi_cs,`
417	10	dinesha	`wb_xram_stb`
418	27	dinesha
419	2	dinesha	`}),`
420
421	27	dinesha	`.wbd_cyc_slave ({wb_i2cm_cyc,`
422			`wb_uart_cyc,`
423			`wb_spi_cyc,`
424			`wb_xram_cyc`
425			`}),`
426	2	dinesha	`.wbd_err_slave (),`
427			`.wbd_rty_slave ()`
428			`);`
429
430
431
432			`//-------------------------------------`
433			`// UART core instantiation`
434			`//-------------------------------------`
435
436			`uart_core u_uart_core`
437
438			`(`
439			`. app_reset_n (gen_resetn ),`
440			`. app_clk (app_clk ),`
441
442
443			`// Reg Bus Interface Signal`
444			`. reg_cs (reg_uart_cs ),`
445			`. reg_wr (reg_uart_wr ),`
446	11	dinesha	`. reg_addr (reg_uart_addr[3:0] ),`
447	2	dinesha	`. reg_wdata (reg_uart_wdata ),`
448	11	dinesha	`. reg_be (1'b1 ),`
449	2	dinesha
450			`// Outputs`
451			`. reg_rdata (reg_uart_rdata ),`
452			`. reg_ack (reg_uart_ack ),`
453
454
455
456			`// Line Interface`
457	19	dinesha	`. si (uart1_rxd ),`
458			`. so (uart1_txd )`
459	2	dinesha
460			`);`
461
462
463			`//--------------------------------`
464			`// SPI core instantiation`
465			`//--------------------------------`
466
467
468			`spi_core u_spi_core (`
469
470			`. clk (app_clk ),`
471			`. reset_n (gen_resetn ),`
472
473			`// Reg Bus Interface Signal`
474			`. reg_cs (reg_spi_cs ),`
475			`. reg_wr (reg_spi_wr ),`
476	11	dinesha	`. reg_addr (reg_spi_addr[3:0] ),`
477	2	dinesha	`. reg_wdata (reg_spi_wdata ),`
478	11	dinesha	`. reg_be (1'b1 ),`
479	2	dinesha
480			`// Outputs`
481			`. reg_rdata (reg_spi_rdata ),`
482			`. reg_ack (reg_spi_ack ),`
483
484
485			`. sck (spi_sck ),`
486			`. so (spi_so ),`
487			`. si (spi_si ),`
488			`. cs_n (spi_cs_n )`
489
490			`);`
491
492	27	dinesha	`/******************************************************`
493			`* I2C Master Core`
494			`* ***************************************************/`
495	32	dinesha	`i2cm_top i_i2cm_core (`
496	27	dinesha	`// wishbone signals`
497			`.wb_clk_i (app_clk ),`
498			`.sresetn (gen_resetn ),`
499			`.aresetn (aresetn ),`
500			`.wb_adr_i (wb_i2cm_addr[2:0] ),`

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