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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OMS8051 I2C Master bit-controller Module                    ////
////  WISHBONE rev.B2 compliant I2C Master bit-controller         ////
////                                                              ////
////  This file is part of the OMS 8051 cores project             ////
////  http://www.opencores.org/cores/oms8051mini/                 ////
////                                                              ////
////  Description                                                 ////
////  OMS 8051 definitions.                                       ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
////  Author(s):                                                  ////
////      -Richard Herveille ,  richard@asics.ws, www.asics.ws    ////
////      -Dinesh Annayya, dinesha@opencores.org                  ////
////                                                              ////
////  Revision : Jan 6, 2017                                      //// 
////                                                              ////
//////////////////////////////////////////////////////////////////////
//     v0.0 - Dinesh A, 6th Jan 2017
//          1. Initail version picked from
//              http://www.opencores.org/projects/i2c/
//     v0.1 - Dinesh A, 19th Jan 2017
//          1. Lint warning clean up
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
/////////////////////////////////////
// Bit controller section
/////////////////////////////////////
//
// Translate simple commands into SCL/SDA transitions
// Each command has 5 states, A/B/C/D/idle
//
// start:       SCL     ~~~~~~~~~~\____
//      SDA     ~~~~~~~~\______
//               x | A | B | C | D | i
//
// repstart     SCL     ____/~~~~\___
//      SDA     __/~~~\______
//               x | A | B | C | D | i
//
// stop SCL     ____/~~~~~~~~
//      SDA     ==\____/~~~~~
//               x | A | B | C | D | i
//
//- write       SCL     ____/~~~~\____
//      SDA     ==X=========X=
//               x | A | B | C | D | i
//
//- read        SCL     ____/~~~~\____
//      SDA     XXXX=====XXXX
//               x | A | B | C | D | i
//
 
// Timing:     Normal mode      Fast mode
///////////////////////////////////////////////////////////////////////
// Fscl        100KHz           400KHz
// Th_scl      4.0us            0.6us   High period of SCL
// Tl_scl      4.7us            1.3us   Low period of SCL
// Tsu:sta     4.7us            0.6us   setup time for a repeated start condition
// Tsu:sto     4.0us            0.6us   setup time for a stop conditon
// Tbuf        4.7us            1.3us   Bus free time between a stop and start condition
//
 
 
`include "i2cm_defines.v"
 
module i2cm_bit_ctrl (
    input             clk,      // system clock
    input             sresetn,  // synchronous active low reset
    input             aresetn,  // asynchronous active low reset
    input             ena,      // core enable signal
 
    input      [15:0] clk_cnt,  // clock prescale value
 
    input      [ 3:0] cmd,      // command (from byte controller)
    output reg        cmd_ack,  // command complete acknowledge
    output reg        busy,     // i2c bus busy
    output reg        al,       // i2c bus arbitration lost
 
    input             din,
    output reg        dout,
 
    input             scl_i,    // i2c clock line input
    output            scl_o,    // i2c clock line output
    output reg        scl_oen,  // i2c clock line output enable (active low)
    input             sda_i,    // i2c data line input
    output            sda_o,    // i2c data line output
    output reg        sda_oen   // i2c data line output enable (active low)
);
 
 
    //
    // variable declarations
    //
 
    reg [ 1:0] cSCL, cSDA;      // capture SCL and SDA
    reg [ 2:0] fSCL, fSDA;      // SCL and SDA filter inputs
    reg        sSCL, sSDA;      // filtered and synchronized SCL and SDA inputs
    reg        dSCL, dSDA;      // delayed versions of sSCL and sSDA
    reg        dscl_oen;        // delayed scl_oen
    reg        sda_chk;         // check SDA output (Multi-master arbitration)
    reg        clk_en;          // clock generation signals
    reg        slave_wait;      // slave inserts wait states
    reg [15:0] cnt;             // clock divider counter (synthesis)
    reg [13:0] filter_cnt;      // clock divider for filter
 
 
    // state machine variable
    reg [17:0] c_state; // synopsys enum_state
 
    //
    // module body
    //
 
    // whenever the slave is not ready it can delay the cycle by pulling SCL low
    // delay scl_oen
    always @(posedge clk)
      dscl_oen <= scl_oen;
 
    // slave_wait is asserted when master wants to drive SCL high, but the slave pulls it low
    // slave_wait remains asserted until the slave releases SCL
    always @(posedge clk or negedge aresetn)
      if (!aresetn) slave_wait <= 1'b0;
      else         slave_wait <= (scl_oen & ~dscl_oen & ~sSCL) | (slave_wait & ~sSCL);
 
    // master drives SCL high, but another master pulls it low
    // master start counting down its low cycle now (clock synchronization)
    wire scl_sync   = dSCL & ~sSCL & scl_oen;
 
 
    // generate clk enable signal
    always @(posedge clk or negedge aresetn)
      if (~aresetn)
      begin
          cnt    <= 16'h0;
          clk_en <= 1'b1;
      end
      else if (!sresetn || ~|cnt || !ena || scl_sync)
      begin
          cnt    <= clk_cnt;
          clk_en <= 1'b1;
      end
      else if (slave_wait)
      begin
          cnt    <= cnt;
          clk_en <= 1'b0;
      end
      else
      begin
          cnt    <= cnt - 16'h1;
          clk_en <= 1'b0;
      end
 
 
    // generate bus status controller
 
    // capture SDA and SCL
    // reduce metastability risk
    always @(posedge clk or negedge aresetn)
      if (!aresetn)
      begin
          cSCL <= 2'b00;
          cSDA <= 2'b00;
      end
      else if (!sresetn)
      begin
          cSCL <= 2'b00;
          cSDA <= 2'b00;
      end
      else
      begin
          cSCL <= {cSCL[0],scl_i};
          cSDA <= {cSDA[0],sda_i};
      end
 
 
    // filter SCL and SDA signals; (attempt to) remove glitches
    always @(posedge clk or negedge aresetn)
      if      (!aresetn     ) filter_cnt <= 14'h0;
      else if (!sresetn || !ena ) filter_cnt <= 14'h0;
      else if (~|filter_cnt) filter_cnt <= clk_cnt >> 2; //16x I2C bus frequency
      else                   filter_cnt <= filter_cnt -1;
 
 
    always @(posedge clk or negedge aresetn)
      if (!aresetn)
      begin
          fSCL <= 3'b111;
          fSDA <= 3'b111;
      end
      else if (!sresetn)
      begin
          fSCL <= 3'b111;
          fSDA <= 3'b111;
      end
      else if (~|filter_cnt)
      begin
          fSCL <= {fSCL[1:0],cSCL[1]};
          fSDA <= {fSDA[1:0],cSDA[1]};
      end
 
 
    // generate filtered SCL and SDA signals
    always @(posedge clk or negedge aresetn)
      if (~aresetn)
      begin
          sSCL <= 1'b1;
          sSDA <= 1'b1;
 
          dSCL <= 1'b1;
          dSDA <= 1'b1;
      end
      else if (!sresetn)
      begin
          sSCL <= 1'b1;
          sSDA <= 1'b1;
 
          dSCL <= 1'b1;
          dSDA <= 1'b1;
      end
      else
      begin
          sSCL <= &fSCL[2:1] | &fSCL[1:0] | (fSCL[2] & fSCL[0]);
          sSDA <= &fSDA[2:1] | &fSDA[1:0] | (fSDA[2] & fSDA[0]);
 
          dSCL <= sSCL;
          dSDA <= sSDA;
      end
 
    // detect start condition => detect falling edge on SDA while SCL is high
    // detect stop condition => detect rising edge on SDA while SCL is high
    reg sta_condition;
    reg sto_condition;
    always @(posedge clk or negedge aresetn)
      if (~aresetn)
      begin
          sta_condition <= 1'b0;
          sto_condition <= 1'b0;
      end
      else if (!sresetn)
      begin
          sta_condition <= 1'b0;
          sto_condition <= 1'b0;
      end
      else
      begin
          sta_condition <= ~sSDA &  dSDA & sSCL;
          sto_condition <=  sSDA & ~dSDA & sSCL;
      end
 
 
    // generate i2c bus busy signal
    always @(posedge clk or negedge aresetn)
      if      (!aresetn) busy <= 1'b0;
      else if (!sresetn    ) busy <= 1'b0;
      else              busy <= (sta_condition | busy) & ~sto_condition;
 
 
    // generate arbitration lost signal
    // aribitration lost when:
    // 1) master drives SDA high, but the i2c bus is low
    // 2) stop detected while not requested
    reg cmd_stop;
    always @(posedge clk or negedge aresetn)
      if (~aresetn)
          cmd_stop <= 1'b0;
      else if (!sresetn)
          cmd_stop <= 1'b0;
      else if (clk_en)
          cmd_stop <= cmd == `I2C_CMD_STOP;
 
    always @(posedge clk or negedge aresetn)
      if (~aresetn)
          al <= 1'b0;
      else if (!sresetn)
          al <= 1'b0;
      else
          al <= (sda_chk & ~sSDA & sda_oen) | (|c_state & sto_condition & ~cmd_stop);
 
 
    // generate dout signal (store SDA on rising edge of SCL)
    always @(posedge clk)
      if (sSCL & ~dSCL) dout <= sSDA;
 
 
    // generate statemachine
 
    // nxt_state decoder
    parameter [17:0] idle    = 18'b0_0000_0000_0000_0000;
    parameter [17:0] start_a = 18'b0_0000_0000_0000_0001;
    parameter [17:0] start_b = 18'b0_0000_0000_0000_0010;
    parameter [17:0] start_c = 18'b0_0000_0000_0000_0100;
    parameter [17:0] start_d = 18'b0_0000_0000_0000_1000;
    parameter [17:0] start_e = 18'b0_0000_0000_0001_0000;
    parameter [17:0] stop_a  = 18'b0_0000_0000_0010_0000;
    parameter [17:0] stop_b  = 18'b0_0000_0000_0100_0000;
    parameter [17:0] stop_c  = 18'b0_0000_0000_1000_0000;
    parameter [17:0] stop_d  = 18'b0_0000_0001_0000_0000;
    parameter [17:0] rd_a    = 18'b0_0000_0010_0000_0000;
    parameter [17:0] rd_b    = 18'b0_0000_0100_0000_0000;
    parameter [17:0] rd_c    = 18'b0_0000_1000_0000_0000;
    parameter [17:0] rd_d    = 18'b0_0001_0000_0000_0000;
    parameter [17:0] wr_a    = 18'b0_0010_0000_0000_0000;
    parameter [17:0] wr_b    = 18'b0_0100_0000_0000_0000;
    parameter [17:0] wr_c    = 18'b0_1000_0000_0000_0000;
    parameter [17:0] wr_d    = 18'b1_0000_0000_0000_0000;
 
    always @(posedge clk or negedge aresetn)
      if (!aresetn)
      begin
          c_state <= idle;
          cmd_ack <= 1'b0;
          scl_oen <= 1'b1;
          sda_oen <= 1'b1;
          sda_chk <= 1'b0;
      end
      else if (!sresetn | al)
      begin
          c_state <= idle;
          cmd_ack <= 1'b0;
          scl_oen <= 1'b1;
          sda_oen <= 1'b1;
          sda_chk <= 1'b0;
      end
      else
      begin
          cmd_ack   <= 1'b0; // default no command acknowledge + assert cmd_ack only 1clk cycle
 
          if (clk_en)
              case (c_state) // synopsys full_case parallel_case
                    // idle state
                    idle:
                    begin
                        case (cmd) // synopsys full_case parallel_case
                             `I2C_CMD_START: c_state <= start_a;
                             `I2C_CMD_STOP:  c_state <= stop_a;
                             `I2C_CMD_WRITE: c_state <= wr_a;
                             `I2C_CMD_READ:  c_state <= rd_a;
                             default:        c_state <= idle;
                        endcase
 
                        scl_oen <= scl_oen; // keep SCL in same state
                        sda_oen <= sda_oen; // keep SDA in same state
                        sda_chk <= 1'b0;    // don't check SDA output
                    end
 
                    // start
                    start_a:
                    begin
                        c_state <= start_b;
                        scl_oen <= scl_oen; // keep SCL in same state
                        sda_oen <= 1'b1;    // set SDA high
                        sda_chk <= 1'b0;    // don't check SDA output
                    end
 
                    start_b:
                    begin
                        c_state <= start_c;
                        scl_oen <= 1'b1; // set SCL high
                        sda_oen <= 1'b1; // keep SDA high
                        sda_chk <= 1'b0; // don't check SDA output
                    end
 
                    start_c:
                    begin
                        c_state <= start_d;
                        scl_oen <= 1'b1; // keep SCL high
                        sda_oen <= 1'b0; // set SDA low
                        sda_chk <= 1'b0; // don't check SDA output
                    end
 
                    start_d:
                    begin
                        c_state <= start_e;
                        scl_oen <= 1'b1; // keep SCL high
                        sda_oen <= 1'b0; // keep SDA low
                        sda_chk <= 1'b0; // don't check SDA output
                    end
 
                    start_e:
                    begin
                        c_state <= idle;
                        cmd_ack <= 1'b1;
                        scl_oen <= 1'b0; // set SCL low
                        sda_oen <= 1'b0; // keep SDA low
                        sda_chk <= 1'b0; // don't check SDA output
                    end
 
                    // stop
                    stop_a:
                    begin
                        c_state <= stop_b;
                        scl_oen <= 1'b0; // keep SCL low
                        sda_oen <= 1'b0; // set SDA low
                        sda_chk <= 1'b0; // don't check SDA output
                    end
 
                    stop_b:
                    begin
                        c_state <= stop_c;
                        scl_oen <= 1'b1; // set SCL high
                        sda_oen <= 1'b0; // keep SDA low
                        sda_chk <= 1'b0; // don't check SDA output
                    end
 
                    stop_c:
                    begin
                        c_state <= stop_d;
                        scl_oen <= 1'b1; // keep SCL high
                        sda_oen <= 1'b0; // keep SDA low
                        sda_chk <= 1'b0; // don't check SDA output
                    end
 
                    stop_d:
                    begin
                        c_state <= idle;
                        cmd_ack <= 1'b1;
                        scl_oen <= 1'b1; // keep SCL high
                        sda_oen <= 1'b1; // set SDA high
                        sda_chk <= 1'b0; // don't check SDA output
                    end
 
                    // read
                    rd_a:
                    begin
                        c_state <= rd_b;
                        scl_oen <= 1'b0; // keep SCL low
                        sda_oen <= 1'b1; // tri-state SDA
                        sda_chk <= 1'b0; // don't check SDA output
                    end
 
                    rd_b:
                    begin
                        c_state <= rd_c;
                        scl_oen <= 1'b1; // set SCL high
                        sda_oen <= 1'b1; // keep SDA tri-stated
                        sda_chk <= 1'b0; // don't check SDA output
                    end
 
                    rd_c:
                    begin
                        c_state <= rd_d;
                        scl_oen <= 1'b1; // keep SCL high
                        sda_oen <= 1'b1; // keep SDA tri-stated
                        sda_chk <= 1'b0; // don't check SDA output
                    end
 
                    rd_d:
                    begin
                        c_state <= idle;
                        cmd_ack <= 1'b1;
                        scl_oen <= 1'b0; // set SCL low
                        sda_oen <= 1'b1; // keep SDA tri-stated
                        sda_chk <= 1'b0; // don't check SDA output
                    end
 
                    // write
                    wr_a:
                    begin
                        c_state <= wr_b;
                        scl_oen <= 1'b0; // keep SCL low
                        sda_oen <= din;  // set SDA
                        sda_chk <= 1'b0; // don't check SDA output (SCL low)
                    end
 
                    wr_b:
                    begin
                        c_state <= wr_c;
                        scl_oen <= 1'b1; // set SCL high
                        sda_oen <= din;  // keep SDA
                        sda_chk <= 1'b0; // don't check SDA output yet
                                            // allow some time for SDA and SCL to settle
                    end
 
                    wr_c:
                    begin
                        c_state <= wr_d;
                        scl_oen <= 1'b1; // keep SCL high
                        sda_oen <= din;
                        sda_chk <= 1'b1; // check SDA output
                    end
 
                    wr_d:
                    begin
                        c_state <= idle;
                        cmd_ack <= 1'b1;
                        scl_oen <= 1'b0; // set SCL low
                        sda_oen <= din;
                        sda_chk <= 1'b0; // don't check SDA output (SCL low)
                    end
 
              endcase
      end
 
 
    // assign scl and sda output (always gnd)
    assign scl_o = 1'b0;
    assign sda_o = 1'b0;
 
endmodule

Line No.	Rev	Author	Line
1	28	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OMS8051 I2C Master bit-controller Module ////`
4			`//// WISHBONE rev.B2 compliant I2C Master bit-controller ////`
5			`//// ////`
6			`//// This file is part of the OMS 8051 cores project ////`
7			`//// http://www.opencores.org/cores/oms8051mini/ ////`
8			`//// ////`
9			`//// Description ////`
10			`//// OMS 8051 definitions. ////`
11			`//// ////`
12			`//// To Do: ////`
13			`//// nothing ////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// -Richard Herveille , richard@asics.ws, www.asics.ws ////`
17			`//// -Dinesh Annayya, dinesha@opencores.org ////`
18			`//// ////`
19			`//// Revision : Jan 6, 2017 ////`
20			`//// ////`
21			`//////////////////////////////////////////////////////////////////////`
22			`// v0.0 - Dinesh A, 6th Jan 2017`
23			`// 1. Initail version picked from`
24			`// http://www.opencores.org/projects/i2c/`
25	36	dinesha	`// v0.1 - Dinesh A, 19th Jan 2017`
26			`// 1. Lint warning clean up`
27	28	dinesha	`//////////////////////////////////////////////////////////////////////`
28			`//// ////`
29			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
30			`//// ////`
31			`//// This source file may be used and distributed without ////`
32			`//// restriction provided that this copyright statement is not ////`
33			`//// removed from the file and that any derivative work contains ////`
34			`//// the original copyright notice and the associated disclaimer. ////`
35			`//// ////`
36			`//// This source file is free software; you can redistribute it ////`
37			`//// and/or modify it under the terms of the GNU Lesser General ////`
38			`//// Public License as published by the Free Software Foundation; ////`
39			`//// either version 2.1 of the License, or (at your option) any ////`
40			`//// later version. ////`
41			`//// ////`
42			`//// This source is distributed in the hope that it will be ////`
43			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
44			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
45			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
46			`//// details. ////`
47			`//// ////`
48			`//// You should have received a copy of the GNU Lesser General ////`
49			`//// Public License along with this source; if not, download it ////`
50			`//// from http://www.opencores.org/lgpl.shtml ////`
51			`//// ////`
52			`//////////////////////////////////////////////////////////////////////`
53			`/////////////////////////////////////`
54			`// Bit controller section`
55			`/////////////////////////////////////`
56			`//`
57			`// Translate simple commands into SCL/SDA transitions`
58			`// Each command has 5 states, A/B/C/D/idle`
59			`//`
60			`// start: SCL ~~~~~~~~~~\____`
61			`// SDA ~~~~~~~~\______`
62			`// x \| A \| B \| C \| D \| i`
63			`//`
64			`// repstart SCL ____/~~~~\___`
65			`// SDA __/~~~\______`
66			`// x \| A \| B \| C \| D \| i`
67			`//`
68			`// stop SCL ____/~~~~~~~~`
69			`// SDA ==\____/~~~~~`
70			`// x \| A \| B \| C \| D \| i`
71			`//`
72			`//- write SCL ____/~~~~\____`
73			`// SDA ==X=========X=`
74			`// x \| A \| B \| C \| D \| i`
75			`//`
76			`//- read SCL ____/~~~~\____`
77			`// SDA XXXX=====XXXX`
78			`// x \| A \| B \| C \| D \| i`
79			`//`
80
81			`// Timing: Normal mode Fast mode`
82			`///////////////////////////////////////////////////////////////////////`
83			`// Fscl 100KHz 400KHz`
84			`// Th_scl 4.0us 0.6us High period of SCL`
85			`// Tl_scl 4.7us 1.3us Low period of SCL`
86			`// Tsu:sta 4.7us 0.6us setup time for a repeated start condition`
87			`// Tsu:sto 4.0us 0.6us setup time for a stop conditon`
88			`// Tbuf 4.7us 1.3us Bus free time between a stop and start condition`
89			`//`
90
91
92			`include "i2cm_defines.v"
93
94			`module i2cm_bit_ctrl (`
95			`input clk, // system clock`
96			`input sresetn, // synchronous active low reset`
97			`input aresetn, // asynchronous active low reset`
98			`input ena, // core enable signal`
99
100			`input [15:0] clk_cnt, // clock prescale value`
101
102			`input [ 3:0] cmd, // command (from byte controller)`
103			`output reg cmd_ack, // command complete acknowledge`
104			`output reg busy, // i2c bus busy`
105			`output reg al, // i2c bus arbitration lost`
106
107			`input din,`
108			`output reg dout,`
109
110			`input scl_i, // i2c clock line input`
111			`output scl_o, // i2c clock line output`
112			`output reg scl_oen, // i2c clock line output enable (active low)`
113			`input sda_i, // i2c data line input`
114			`output sda_o, // i2c data line output`
115			`output reg sda_oen // i2c data line output enable (active low)`
116			`);`
117
118
119			`//`
120			`// variable declarations`
121			`//`
122
123			`reg [ 1:0] cSCL, cSDA; // capture SCL and SDA`
124			`reg [ 2:0] fSCL, fSDA; // SCL and SDA filter inputs`
125			`reg sSCL, sSDA; // filtered and synchronized SCL and SDA inputs`
126			`reg dSCL, dSDA; // delayed versions of sSCL and sSDA`
127			`reg dscl_oen; // delayed scl_oen`
128			`reg sda_chk; // check SDA output (Multi-master arbitration)`
129			`reg clk_en; // clock generation signals`
130			`reg slave_wait; // slave inserts wait states`
131			`reg [15:0] cnt; // clock divider counter (synthesis)`
132			`reg [13:0] filter_cnt; // clock divider for filter`
133
134
135			`// state machine variable`
136			`reg [17:0] c_state; // synopsys enum_state`
137
138			`//`
139			`// module body`
140			`//`
141
142			`// whenever the slave is not ready it can delay the cycle by pulling SCL low`
143			`// delay scl_oen`
144			`always @(posedge clk)`
145	36	dinesha	`dscl_oen <= scl_oen;`
146	28	dinesha
147			`// slave_wait is asserted when master wants to drive SCL high, but the slave pulls it low`
148			`// slave_wait remains asserted until the slave releases SCL`
149			`always @(posedge clk or negedge aresetn)`
150			`if (!aresetn) slave_wait <= 1'b0;`
151			`else slave_wait <= (scl_oen & ~dscl_oen & ~sSCL) \| (slave_wait & ~sSCL);`
152
153			`// master drives SCL high, but another master pulls it low`
154			`// master start counting down its low cycle now (clock synchronization)`
155			`wire scl_sync = dSCL & ~sSCL & scl_oen;`
156
157
158			`// generate clk enable signal`
159			`always @(posedge clk or negedge aresetn)`
160			`if (~aresetn)`
161			`begin`
162	36	dinesha	`cnt <= 16'h0;`
163			`clk_en <= 1'b1;`
164	28	dinesha	`end`
165			`else if (!sresetn \|\| ~\|cnt \|\| !ena \|\| scl_sync)`
166			`begin`
167	36	dinesha	`cnt <= clk_cnt;`
168			`clk_en <= 1'b1;`
169	28	dinesha	`end`
170			`else if (slave_wait)`
171			`begin`
172	36	dinesha	`cnt <= cnt;`
173			`clk_en <= 1'b0;`
174	28	dinesha	`end`
175			`else`
176			`begin`
177	36	dinesha	`cnt <= cnt - 16'h1;`
178			`clk_en <= 1'b0;`
179	28	dinesha	`end`
180
181
182			`// generate bus status controller`
183
184			`// capture SDA and SCL`
185			`// reduce metastability risk`
186			`always @(posedge clk or negedge aresetn)`
187			`if (!aresetn)`
188			`begin`
189	36	dinesha	`cSCL <= 2'b00;`
190			`cSDA <= 2'b00;`
191	28	dinesha	`end`
192			`else if (!sresetn)`
193			`begin`
194	36	dinesha	`cSCL <= 2'b00;`
195			`cSDA <= 2'b00;`
196	28	dinesha	`end`
197			`else`
198			`begin`
199			`cSCL <= {cSCL[0],scl_i};`
200			`cSDA <= {cSDA[0],sda_i};`
201			`end`
202
203
204			`// filter SCL and SDA signals; (attempt to) remove glitches`
205			`always @(posedge clk or negedge aresetn)`
206			`if (!aresetn ) filter_cnt <= 14'h0;`
207			`else if (!sresetn \|\| !ena ) filter_cnt <= 14'h0;`
208			`else if (~\|filter_cnt) filter_cnt <= clk_cnt >> 2; //16x I2C bus frequency`
209			`else filter_cnt <= filter_cnt -1;`
210
211
212			`always @(posedge clk or negedge aresetn)`
213			`if (!aresetn)`
214			`begin`
215			`fSCL <= 3'b111;`
216			`fSDA <= 3'b111;`
217			`end`
218			`else if (!sresetn)`
219			`begin`
220			`fSCL <= 3'b111;`
221			`fSDA <= 3'b111;`
222			`end`
223			`else if (~\|filter_cnt)`
224			`begin`
225			`fSCL <= {fSCL[1:0],cSCL[1]};`
226			`fSDA <= {fSDA[1:0],cSDA[1]};`
227			`end`
228
229
230			`// generate filtered SCL and SDA signals`
231			`always @(posedge clk or negedge aresetn)`
232			`if (~aresetn)`
233			`begin`
234	36	dinesha	`sSCL <= 1'b1;`
235			`sSDA <= 1'b1;`
236	28	dinesha
237	36	dinesha	`dSCL <= 1'b1;`
238			`dSDA <= 1'b1;`
239	28	dinesha	`end`
240			`else if (!sresetn)`
241			`begin`
242	36	dinesha	`sSCL <= 1'b1;`
243			`sSDA <= 1'b1;`
244	28	dinesha
245	36	dinesha	`dSCL <= 1'b1;`
246			`dSDA <= 1'b1;`
247	28	dinesha	`end`
248			`else`
249			`begin`
250	36	dinesha	`sSCL <= &fSCL[2:1] \| &fSCL[1:0] \| (fSCL[2] & fSCL[0]);`
251			`sSDA <= &fSDA[2:1] \| &fSDA[1:0] \| (fSDA[2] & fSDA[0]);`
252	28	dinesha
253	36	dinesha	`dSCL <= sSCL;`
254			`dSDA <= sSDA;`
255	28	dinesha	`end`
256
257			`// detect start condition => detect falling edge on SDA while SCL is high`
258			`// detect stop condition => detect rising edge on SDA while SCL is high`
259			`reg sta_condition;`
260			`reg sto_condition;`
261			`always @(posedge clk or negedge aresetn)`
262			`if (~aresetn)`
263			`begin`
264	36	dinesha	`sta_condition <= 1'b0;`
265			`sto_condition <= 1'b0;`
266	28	dinesha	`end`
267			`else if (!sresetn)`
268			`begin`
269	36	dinesha	`sta_condition <= 1'b0;`
270			`sto_condition <= 1'b0;`
271	28	dinesha	`end`
272			`else`
273			`begin`
274	36	dinesha	`sta_condition <= ~sSDA & dSDA & sSCL;`
275			`sto_condition <= sSDA & ~dSDA & sSCL;`
276	28	dinesha	`end`
277
278
279			`// generate i2c bus busy signal`
280			`always @(posedge clk or negedge aresetn)`
281	36	dinesha	`if (!aresetn) busy <= 1'b0;`
282			`else if (!sresetn ) busy <= 1'b0;`
283			`else busy <= (sta_condition \| busy) & ~sto_condition;`
284	28	dinesha
285
286			`// generate arbitration lost signal`
287			`// aribitration lost when:`
288			`// 1) master drives SDA high, but the i2c bus is low`
289			`// 2) stop detected while not requested`
290			`reg cmd_stop;`
291			`always @(posedge clk or negedge aresetn)`
292			`if (~aresetn)`
293	36	dinesha	`cmd_stop <= 1'b0;`
294	28	dinesha	`else if (!sresetn)`
295	36	dinesha	`cmd_stop <= 1'b0;`
296	28	dinesha	`else if (clk_en)`
297	36	dinesha	cmd_stop <= cmd == `I2C_CMD_STOP;
298	28	dinesha
299			`always @(posedge clk or negedge aresetn)`
300			`if (~aresetn)`
301	36	dinesha	`al <= 1'b0;`
302	28	dinesha	`else if (!sresetn)`
303	36	dinesha	`al <= 1'b0;`
304	28	dinesha	`else`
305	36	dinesha	`al <= (sda_chk & ~sSDA & sda_oen) \| (\|c_state & sto_condition & ~cmd_stop);`
306	28	dinesha
307
308			`// generate dout signal (store SDA on rising edge of SCL)`
309			`always @(posedge clk)`
310	36	dinesha	`if (sSCL & ~dSCL) dout <= sSDA;`
311	28	dinesha
312
313			`// generate statemachine`
314
315			`// nxt_state decoder`
316			`parameter [17:0] idle = 18'b0_0000_0000_0000_0000;`
317			`parameter [17:0] start_a = 18'b0_0000_0000_0000_0001;`
318			`parameter [17:0] start_b = 18'b0_0000_0000_0000_0010;`
319			`parameter [17:0] start_c = 18'b0_0000_0000_0000_0100;`
320			`parameter [17:0] start_d = 18'b0_0000_0000_0000_1000;`
321			`parameter [17:0] start_e = 18'b0_0000_0000_0001_0000;`
322			`parameter [17:0] stop_a = 18'b0_0000_0000_0010_0000;`
323			`parameter [17:0] stop_b = 18'b0_0000_0000_0100_0000;`
324			`parameter [17:0] stop_c = 18'b0_0000_0000_1000_0000;`
325			`parameter [17:0] stop_d = 18'b0_0000_0001_0000_0000;`
326			`parameter [17:0] rd_a = 18'b0_0000_0010_0000_0000;`
327			`parameter [17:0] rd_b = 18'b0_0000_0100_0000_0000;`
328			`parameter [17:0] rd_c = 18'b0_0000_1000_0000_0000;`
329			`parameter [17:0] rd_d = 18'b0_0001_0000_0000_0000;`
330			`parameter [17:0] wr_a = 18'b0_0010_0000_0000_0000;`
331			`parameter [17:0] wr_b = 18'b0_0100_0000_0000_0000;`
332			`parameter [17:0] wr_c = 18'b0_1000_0000_0000_0000;`
333			`parameter [17:0] wr_d = 18'b1_0000_0000_0000_0000;`
334
335			`always @(posedge clk or negedge aresetn)`
336			`if (!aresetn)`
337			`begin`
338	36	dinesha	`c_state <= idle;`
339			`cmd_ack <= 1'b0;`
340			`scl_oen <= 1'b1;`
341			`sda_oen <= 1'b1;`
342			`sda_chk <= 1'b0;`
343	28	dinesha	`end`
344			`else if (!sresetn \| al)`
345			`begin`
346	36	dinesha	`c_state <= idle;`
347			`cmd_ack <= 1'b0;`
348			`scl_oen <= 1'b1;`
349			`sda_oen <= 1'b1;`
350			`sda_chk <= 1'b0;`
351	28	dinesha	`end`
352			`else`
353			`begin`
354	36	dinesha	`cmd_ack <= 1'b0; // default no command acknowledge + assert cmd_ack only 1clk cycle`
355	28	dinesha
356			`if (clk_en)`
357			`case (c_state) // synopsys full_case parallel_case`
358			`// idle state`
359			`idle:`
360			`begin`
361			`case (cmd) // synopsys full_case parallel_case`
362	36	dinesha	`I2C_CMD_START: c_state <= start_a;
363			`I2C_CMD_STOP: c_state <= stop_a;
364			`I2C_CMD_WRITE: c_state <= wr_a;
365			`I2C_CMD_READ: c_state <= rd_a;
366			`default: c_state <= idle;`
367	28	dinesha	`endcase`
368
369	36	dinesha	`scl_oen <= scl_oen; // keep SCL in same state`
370			`sda_oen <= sda_oen; // keep SDA in same state`
371			`sda_chk <= 1'b0; // don't check SDA output`
372	28	dinesha	`end`
373
374			`// start`
375			`start_a:`
376			`begin`
377	36	dinesha	`c_state <= start_b;`
378			`scl_oen <= scl_oen; // keep SCL in same state`
379			`sda_oen <= 1'b1; // set SDA high`
380			`sda_chk <= 1'b0; // don't check SDA output`
381	28	dinesha	`end`
382
383			`start_b:`
384			`begin`
385	36	dinesha	`c_state <= start_c;`
386			`scl_oen <= 1'b1; // set SCL high`
387			`sda_oen <= 1'b1; // keep SDA high`
388			`sda_chk <= 1'b0; // don't check SDA output`
389	28	dinesha	`end`
390
391			`start_c:`
392			`begin`
393	36	dinesha	`c_state <= start_d;`
394			`scl_oen <= 1'b1; // keep SCL high`
395			`sda_oen <= 1'b0; // set SDA low`
396			`sda_chk <= 1'b0; // don't check SDA output`
397	28	dinesha	`end`
398
399			`start_d:`
400			`begin`
401	36	dinesha	`c_state <= start_e;`
402			`scl_oen <= 1'b1; // keep SCL high`
403			`sda_oen <= 1'b0; // keep SDA low`
404			`sda_chk <= 1'b0; // don't check SDA output`
405	28	dinesha	`end`
406
407			`start_e:`
408			`begin`
409	36	dinesha	`c_state <= idle;`
410			`cmd_ack <= 1'b1;`
411			`scl_oen <= 1'b0; // set SCL low`
412			`sda_oen <= 1'b0; // keep SDA low`
413			`sda_chk <= 1'b0; // don't check SDA output`
414	28	dinesha	`end`
415
416			`// stop`
417			`stop_a:`
418			`begin`
419	36	dinesha	`c_state <= stop_b;`
420			`scl_oen <= 1'b0; // keep SCL low`
421			`sda_oen <= 1'b0; // set SDA low`
422			`sda_chk <= 1'b0; // don't check SDA output`
423	28	dinesha	`end`
424
425			`stop_b:`
426			`begin`
427	36	dinesha	`c_state <= stop_c;`
428			`scl_oen <= 1'b1; // set SCL high`
429			`sda_oen <= 1'b0; // keep SDA low`
430			`sda_chk <= 1'b0; // don't check SDA output`
431	28	dinesha	`end`
432
433			`stop_c:`
434			`begin`
435	36	dinesha	`c_state <= stop_d;`
436			`scl_oen <= 1'b1; // keep SCL high`
437			`sda_oen <= 1'b0; // keep SDA low`
438			`sda_chk <= 1'b0; // don't check SDA output`
439	28	dinesha	`end`
440
441			`stop_d:`
442			`begin`
443	36	dinesha	`c_state <= idle;`
444			`cmd_ack <= 1'b1;`
445			`scl_oen <= 1'b1; // keep SCL high`
446			`sda_oen <= 1'b1; // set SDA high`
447			`sda_chk <= 1'b0; // don't check SDA output`
448	28	dinesha	`end`
449
450			`// read`
451			`rd_a:`
452			`begin`
453	36	dinesha	`c_state <= rd_b;`
454			`scl_oen <= 1'b0; // keep SCL low`
455			`sda_oen <= 1'b1; // tri-state SDA`
456			`sda_chk <= 1'b0; // don't check SDA output`
457	28	dinesha	`end`
458
459			`rd_b:`
460			`begin`
461	36	dinesha	`c_state <= rd_c;`
462			`scl_oen <= 1'b1; // set SCL high`
463			`sda_oen <= 1'b1; // keep SDA tri-stated`
464			`sda_chk <= 1'b0; // don't check SDA output`
465	28	dinesha	`end`
466
467			`rd_c:`
468			`begin`
469	36	dinesha	`c_state <= rd_d;`
470			`scl_oen <= 1'b1; // keep SCL high`
471			`sda_oen <= 1'b1; // keep SDA tri-stated`
472			`sda_chk <= 1'b0; // don't check SDA output`
473	28	dinesha	`end`
474
475			`rd_d:`
476			`begin`
477	36	dinesha	`c_state <= idle;`
478			`cmd_ack <= 1'b1;`
479			`scl_oen <= 1'b0; // set SCL low`
480			`sda_oen <= 1'b1; // keep SDA tri-stated`
481			`sda_chk <= 1'b0; // don't check SDA output`
482	28	dinesha	`end`
483
484			`// write`
485			`wr_a:`
486			`begin`
487	36	dinesha	`c_state <= wr_b;`
488			`scl_oen <= 1'b0; // keep SCL low`
489			`sda_oen <= din; // set SDA`
490			`sda_chk <= 1'b0; // don't check SDA output (SCL low)`
491	28	dinesha	`end`
492
493			`wr_b:`
494			`begin`
495	36	dinesha	`c_state <= wr_c;`
496			`scl_oen <= 1'b1; // set SCL high`
497			`sda_oen <= din; // keep SDA`
498			`sda_chk <= 1'b0; // don't check SDA output yet`
499	28	dinesha	`// allow some time for SDA and SCL to settle`
500			`end`

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