Subversion Repositories oms8051mini

Reading J:/Microsemi/Libero_SoC_v11.7/Model/tcl/vsim/pref.tcl

# 10.4c

# vsim -do "run.do" -c tb_top "+fib" "+INTERNAL_ROM"

# Start time: 11:09:08 on Jan 08,2017

# //  ModelSim Microsemi 10.4c Aug 12 2015

# //

# //  Copyright 1991-2015 Mentor Graphics Corporation

# //  All Rights Reserved.

# //

# //  THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION

# //  WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS

# //  LICENSORS AND IS SUBJECT TO LICENSE TERMS.

# //  THIS DOCUMENT CONTAINS TRADE SECRETS AND COMMERCIAL OR FINANCIAL

# //  INFORMATION THAT ARE PRIVILEGED, CONFIDENTIAL, AND EXEMPT FROM

# //  DISCLOSURE UNDER THE FREEDOM OF INFORMATION ACT, 5 U.S.C. SECTION 552.

# //  FURTHERMORE, THIS INFORMATION IS PROHIBITED FROM DISCLOSURE UNDER

# //  THE TRADE SECRETS ACT, 18 U.S.C. SECTION 1905.

# //

# Loading sv_std.std

# Loading work.tb_top

# ** Error: (vsim-7) Failed to open data file "F:/Yagna-Product/VLSI/opencores/oms8051mini/trunk/verif/run/work/delay/_primary.dat" in read mode.

#

# No such file or directory. (errno = ENOENT)

# Loading work.digital_core

# Loading work.clkgen

# Loading work.clk_ctl

# Loading work.msg_handler_top

# Loading work.uart_core_nf

# Loading work.uart_txfsm

# Loading work.uart_rxfsm

# Loading work.double_sync_low

# Loading work.msg_handler

# Loading work.wb_crossbar

# Loading work.uart_core

# Loading work.uart_cfg

# Loading work.generic_register

# Loading work.stat_register

# Loading work.async_fifo

# Loading work.spi_core

# Loading work.spi_if

# Loading work.spi_ctl

# Loading work.spi_cfg

# Loading work.req_register

# Loading work.i2cm_top

# Loading work.i2cm_byte_ctrl

# Loading work.i2cm_bit_ctrl

# Loading work.oc8051_top

# Loading work.oc8051_decoder

# Loading work.oc8051_alu

# Loading work.oc8051_multiply

# Loading work.oc8051_divide

# Loading work.oc8051_ram_top

# Loading work.oc8051_ram_256x8_two_bist

# Loading work.oc8051_alu_src_sel

# Loading work.oc8051_comp

# Loading work.oc8051_rom

# Loading work.oc8051_cy_select

# Loading work.oc8051_indi_addr

# Loading work.oc8051_memory_interface

# Loading work.oc8051_sfr

# Loading work.oc8051_acc

# Loading work.oc8051_b_register

# Loading work.oc8051_sp

# Loading work.oc8051_dptr

# Loading work.oc8051_psw

# Loading work.oc8051_ports

# Loading work.oc8051_int

# Loading work.oc8051_tc

# Loading work.oc8051_tc2

# Loading work.oc8051_xram

# Loading work.i2c_slave_model

# Loading work.uart_agent

# Loading work.m25p20

# Loading work.memory_access

# Loading work.acdc_check

# Loading work.internal_logic

# Loading work.AT45DB321

# Loading work.tb_glbl

# Loading work.bit_register

# ** Warning: (vsim-3017) ../tb/tb_top.v(135): [TFMPC] - Too few port connections. Expected 30, found 28.

#    Time: 0 ps  Iteration: 0  Instance: /tb_top/u_core File: ../../rtl/core/digital_core.v

# ** Warning: (vsim-3722) ../tb/tb_top.v(135): [TFMPC] - Missing connection for port 'scan_mode'.

# ** Warning: (vsim-3722) ../tb/tb_top.v(135): [TFMPC] - Missing connection for port 'scan_enable'.

# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(233): [TFMPC] - Too few port connections. Expected 14, found 12.

#    Time: 0 ps  Iteration: 0  Instance: /tb_top/u_core/u_uart_core/u_rxfifo File: ../../rtl/lib/async_fifo.v

# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(233): [TFMPC] - Missing connection for port 'afull'.

# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(233): [TFMPC] - Missing connection for port 'aempty'.

# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(249): [TFMPC] - Too few port connections. Expected 14, found 12.

#    Time: 0 ps  Iteration: 0  Instance: /tb_top/u_core/u_uart_core/u_txfifo File: ../../rtl/lib/async_fifo.v

# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(249): [TFMPC] - Missing connection for port 'afull'.

# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(249): [TFMPC] - Missing connection for port 'aempty'.

# ** Warning: (vsim-3017) ../../rtl/8051/oc8051_top.v(522): [TFMPC] - Too few port connections. Expected 56, found 53.

#    Time: 0 ps  Iteration: 0  Instance: /tb_top/u_core/u_8051_core/u_memory_interface File: ../../rtl/8051/oc8051_memory_interface.v

# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(522): [TFMPC] - Missing connection for port 'iack_i'.

# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(522): [TFMPC] - Missing connection for port 'istb_o'.

# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(522): [TFMPC] - Missing connection for port 'idat_i'.

# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(266): [TOFD] - System task or function '$shm_open' is not defined.

#    Time: 0 ps  Iteration: 0  Instance: /tb_top File: ../tb/tb_top.v

# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(267): [TOFD] - System task or function '$shm_probe' is not defined.

#    Time: 0 ps  Iteration: 0  Instance: /tb_top File: ../tb/tb_top.v

# do run.do

# NOTE : Load memory with Initial delivery content

# NOTE : Initial Load End

# --> Dumpping the design

# ** Error (suppressible): (vsim-12023) ../tb/tb_top.v(266): Cannot execute undefined system task/function '$shm_open'

#

# ** Error (suppressible): (vsim-12023) ../tb/tb_top.v(267): Cannot execute undefined system task/function '$shm_probe'

#

# NOTE: COMMUNICATION (RE)STARTED

# DEBUG i2c_slave; stop condition detected at                  101

################################

# TEST STATUS : PASSED

################################

# ** Note: $finish    : ../tb/tb_top.v(315)

#    Time: 62316 ps  Iteration: 0  Instance: /tb_top

# End time: 11:09:10 on Jan 08,2017, Elapsed time: 0:00:02

# Errors: 3, Warnings: 15