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[/] [oms8051mini/] [trunk/] [verif/] [tb/] [tb_top.v] - Blame information for rev 10

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  This file is part of the OMS 8051 cores project             ////
////  http://www.opencores.org/cores/oms8051/                     ////
////                                                              ////
////  Description                                                 ////
////  OMS 8051 definitions.                                       ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
 
 
`include "tb_defines.v"
 
module tb_top;
 
 
reg    reset_n;
reg    reset;
reg    xtal_clk;
reg    ref_clk_125;
wire   app_clk;
reg    ref_clk_50;
reg    uart_clk_16x;
 
 
parameter XTAL_CLK_PERIOD = 10; // 100MHZ 40; // 25Mhz
parameter APP_CLK_PERIOD = 10;
parameter REF_CLK_125_PERIOD = 8;
parameter REF_CLK_50_PERIOD = 20;
parameter UART_REF_CLK_PERIOD = 20;
 
reg[31:0] events_log;
 
initial
begin
        reset_n = 1;
   #100 reset_n = 0;
   #100 reset_n = 1;
end
 
 
initial begin
  xtal_clk = 1'b0;
  forever #(XTAL_CLK_PERIOD/2.0) xtal_clk = ~xtal_clk;
end
 
 
//initial begin
//  app_clk = 1'b0;
//  forever #(APP_CLK_PERIOD/2.0) app_clk = ~app_clk;
//end
 
initial begin
  ref_clk_125 = 1'b0;
  forever #(REF_CLK_125_PERIOD/2.0) ref_clk_125 = ~ref_clk_125;
end
 
initial begin
  ref_clk_50 = 1'b0;
  forever #(REF_CLK_50_PERIOD/2.0) ref_clk_50 = ~ref_clk_50;
end
 
 
initial begin
  uart_clk_16x = 1'b0;
  forever #(UART_REF_CLK_PERIOD/2.0) uart_clk_16x = ~uart_clk_16x;
end
 
 
wire [3:0]   phy_txd            ;
wire [3:0]   phy_rxd            ;
 
//---------------------------------
// Reg Bus Interface Signal
//---------------------------------
reg                reg_cs     ;
reg [3:0]          reg_id     ;
reg                reg_wr         ;
reg  [14:0]        reg_addr       ;
reg  [31:0]        reg_wdata      ;
reg  [3:0]         reg_be         ;
 
// Outputs
wire  [31:0]        reg_rdata      ;
wire                reg_ack        ;
 
reg                 master_mode   ;
reg                 ea_in   ;   // 1--> Internal Memory
 
 
wire         spi_sck            ;
wire         spi_so             ;
wire         spi_si             ;
wire [3:0]   spi_cs_n           ;
 
wire         clkout             ;
wire         reset_out_n        ;
 
//----------------------------------------
// 8051 core ROM related signals
//---------------------------------------
wire  [15:0]   wb_xrom_adr       ; // instruction address
wire           wb_xrom_ack       ; // instruction acknowlage
wire           wb_xrom_err       ; // instruction error
wire           wb_xrom_wr        ; // instruction error
wire    [31:0] wb_xrom_rdata     ; // rom data input
wire   [31:0]  wb_xrom_wdata     ; // rom data input
 
wire           wb_xrom_stb       ; // instruction strobe
wire           wb_xrom_cyc       ; // instruction cycle
 
 
//----------------------------------------
// 8051 core RAM related signals
//---------------------------------------
wire   [15:0] wb_xram_adr        ; // data-ram address
wire          wb_xram_ack        ; // data-ram acknowlage
wire          wb_xram_err        ; // data-ram error
wire          wb_xram_wr         ; // data-ram error
wire   [3:0]  wb_xram_be         ; // data-ram error
wire   [31:0] wb_xram_rdata      ; // ram data input
wire   [31:0] wb_xram_wdata      ; // ram data input
 
wire          wb_xram_stb        ; // data-ram strobe
wire          wb_xram_cyc        ; // data-ram cycle
 
//----------------------------------------
 
digital_core  u_core (
 
             . reset_n             (reset_n            ),
             . fastsim_mode        (1'b1               ),
             . mastermode          (master_mode        ),
 
             . xtal_clk            (xtal_clk           ),
             . clkout              (app_clk            ),
             . reset_out_n         (reset_out_n        ),
             . ea_in               (ea_in              ), // internal ROM
 
        // Reg Bus Interface Signal
             . ext_reg_cs          (reg_cs             ),
             . ext_reg_tid         (reg_id             ),
             . ext_reg_wr          (reg_wr             ),
             . ext_reg_addr        (reg_addr[14:0]     ),
             . ext_reg_wdata       (reg_wdata          ),
             . ext_reg_be          (reg_be             ),
 
            // Outputs
             . ext_reg_rdata       (reg_rdata          ),
             . ext_reg_ack         (reg_ack            ),
 
 
 
       // UART Line Interface
             .si                   (si                 ),
             .so                   (so                 ),
 
 
             .spi_sck              (spi_sck            ),
             .spi_so               (spi_so             ),
             .spi_si               (spi_si             ),
             .spi_cs_n             (spi_cs_n           )
 
 
        );
 
 
 uart_agent tb_uart (
               . test_clk          (uart_clk_16x       ),
               . sin               (si                 ),
               . dsr_n             (                   ),
               . cts_n             (                   ),
               . dcd_n             (                   ),
 
               . sout              (so                 ),
               . dtr_n             (1'b0               ),
               . rts_n             (1'b0               ),
               . out1_n            (1'b0               ),
               . out2_n            (1'b0               )
       );
 
 
//----------------------- SPI Agents
 
m25p20 i_m25p20_0 (
               .c                  (spi_sck            ),
               .s                  (spi_cs_n[0]        ), // Include selection logic
               .w                  (1'b1               ), // Write protect is always disabled
               .hold               (1'b1               ), // Hold support not used
               .data_in            (spi_so             ),
               .data_out           (spi_si             )
             );
 
 
AT45DB321 i_AT45DB321_0 (
               .CSB                (spi_cs_n[1]        ),
               .SCK                (spi_sck            ),
               .SI                 (spi_so             ),
               .WPB                (1'b1               ),
               .RESETB             (1'b1               ),
               .RDY_BUSYB          (                   ),
               .SO                 (spi_si             )
      );
/***************
spi_agent_3120 spi_agent_3120_0 (
               .cs_b               (spi_cs_n[2]        ),
               .spi_din            (spi_si             ),
               .spi_dout           (spi_so             ),
               .spi_clk            (spi_sck            )
       );
 
spi_agent_3120 spi_agent_3120_1 (
               .cs_b               (spi_cs_n[3]        ),
               .spi_din            (spi_si             ),
               .spi_dout           (spi_so             ),
               .spi_clk            (spi_sck            )
       );
*****************/
 
tb_glbl  tb_glbl ();
 
 
`ifdef DUMP_ENABLE
initial begin
   if ( $test$plusargs("DUMP") ) begin
          $fsdbDumpfile("../dump/test_1.fsdb");
      $fsdbDumpvars;
      $fsdbDumpon;
   end
end
`endif
 
initial begin //{
   $display ("--> Dumpping the design");
   $shm_open("simvision.shm");
   $shm_probe("AC");
end //}
 
 
initial begin
 
   if ( $test$plusargs("INTERNAL_ROM") )  begin
      ea_in       = 1;
      master_mode = 1;
   end else if ( $test$plusargs("EXTERNAL_ROM") ) begin
      ea_in       = 0;
      master_mode = 1;
   end else begin
      ea_in       = 0;
      master_mode = 0;
   end
 
  `TB_GLBL.init;
 
   #1000 wait(reset_out_n == 1);
 
   if ( $test$plusargs("uart_test_1") )
       uart_test1();
   else if ( $test$plusargs("spi_test_1") )
       spi_test1();
   else begin
     // 8051 Test Cases
     #80000000
     $display("time ",$time, "\n faulire: end of time\n \n");
   end
 
   `TB_GLBL.test_stats;
   `TB_GLBL.test_finish;
   #1000 $finish;
end
 
wire [7:0] p2_out = u_core.u_8051_core.p2_o;
wire [7:0] p3_out = u_core.u_8051_core.p3_o;
always @(p2_out or p3_out)
begin
  if((p2_out == 8'haa) &&      // fib.c
     (p3_out == 8'haa )) begin
      $display("################################");
      $display("TEST STATUS : PASSED ");
      $display("################################");
      #100
      $finish;
  end else if(p2_out == 8'h55) begin     // fib.c
      $display("");
      $display("time ",$time," Error: %h", p3_out);
      $display("TEST STATUS : FAILED ");
      $display("");
      #100
      $finish;
  end
end
 
 
 
 
`include "uart_test1.v"
`include "spi_test1.v"
`include "tb_tasks.v"
`include "spi_tasks.v"
 
 
endmodule
`include "tb_glbl.v"

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Subversion Repositories oms8051mini

[/] [oms8051mini/] [trunk/] [verif/] [tb/] [tb_top.v] - Blame information for rev 10

Line No.	Rev	Author	Line
1	2	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// ////`
4			`//// This file is part of the OMS 8051 cores project ////`
5			`//// http://www.opencores.org/cores/oms8051/ ////`
6			`//// ////`
7			`//// Description ////`
8			`//// OMS 8051 definitions. ////`
9			`//// ////`
10			`//// To Do: ////`
11			`//// nothing ////`
12			`//// ////`
13			`//// Author(s): ////`
14			`//// - Dinesh Annayya, dinesha@opencores.org ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42
43
44
45			`include "tb_defines.v"
46
47			`module tb_top;`
48
49
50			`reg reset_n;`
51			`reg reset;`
52			`reg xtal_clk;`
53			`reg ref_clk_125;`
54			`wire app_clk;`
55			`reg ref_clk_50;`
56			`reg uart_clk_16x;`
57
58
59			`parameter XTAL_CLK_PERIOD = 10; // 100MHZ 40; // 25Mhz`
60			`parameter APP_CLK_PERIOD = 10;`
61			`parameter REF_CLK_125_PERIOD = 8;`
62			`parameter REF_CLK_50_PERIOD = 20;`
63			`parameter UART_REF_CLK_PERIOD = 20;`
64
65			`reg[31:0] events_log;`
66
67			`initial`
68			`begin`
69			`reset_n = 1;`
70			`#100 reset_n = 0;`
71			`#100 reset_n = 1;`
72			`end`
73
74
75			`initial begin`
76			`xtal_clk = 1'b0;`
77			`forever #(XTAL_CLK_PERIOD/2.0) xtal_clk = ~xtal_clk;`
78			`end`
79
80
81			`//initial begin`
82			`// app_clk = 1'b0;`
83			`// forever #(APP_CLK_PERIOD/2.0) app_clk = ~app_clk;`
84			`//end`
85
86			`initial begin`
87			`ref_clk_125 = 1'b0;`
88			`forever #(REF_CLK_125_PERIOD/2.0) ref_clk_125 = ~ref_clk_125;`
89			`end`
90
91			`initial begin`
92			`ref_clk_50 = 1'b0;`
93			`forever #(REF_CLK_50_PERIOD/2.0) ref_clk_50 = ~ref_clk_50;`
94			`end`
95
96
97			`initial begin`
98			`uart_clk_16x = 1'b0;`
99			`forever #(UART_REF_CLK_PERIOD/2.0) uart_clk_16x = ~uart_clk_16x;`
100			`end`
101
102
103			`wire [3:0] phy_txd ;`
104			`wire [3:0] phy_rxd ;`
105
106			`//---------------------------------`
107			`// Reg Bus Interface Signal`
108			`//---------------------------------`
109			`reg reg_cs ;`
110			`reg [3:0] reg_id ;`
111			`reg reg_wr ;`
112			`reg [14:0] reg_addr ;`
113			`reg [31:0] reg_wdata ;`
114			`reg [3:0] reg_be ;`
115
116			`// Outputs`
117			`wire [31:0] reg_rdata ;`
118			`wire reg_ack ;`
119
120			`reg master_mode ;`
121			`reg ea_in ; // 1--> Internal Memory`
122
123
124			`wire spi_sck ;`
125			`wire spi_so ;`
126			`wire spi_si ;`
127			`wire [3:0] spi_cs_n ;`
128
129			`wire clkout ;`
130			`wire reset_out_n ;`
131
132			`//----------------------------------------`
133			`// 8051 core ROM related signals`
134			`//---------------------------------------`
135			`wire [15:0] wb_xrom_adr ; // instruction address`
136			`wire wb_xrom_ack ; // instruction acknowlage`
137			`wire wb_xrom_err ; // instruction error`
138			`wire wb_xrom_wr ; // instruction error`
139			`wire [31:0] wb_xrom_rdata ; // rom data input`
140			`wire [31:0] wb_xrom_wdata ; // rom data input`
141
142			`wire wb_xrom_stb ; // instruction strobe`
143			`wire wb_xrom_cyc ; // instruction cycle`
144
145
146			`//----------------------------------------`
147			`// 8051 core RAM related signals`
148			`//---------------------------------------`
149			`wire [15:0] wb_xram_adr ; // data-ram address`
150			`wire wb_xram_ack ; // data-ram acknowlage`
151			`wire wb_xram_err ; // data-ram error`
152			`wire wb_xram_wr ; // data-ram error`
153			`wire [3:0] wb_xram_be ; // data-ram error`
154			`wire [31:0] wb_xram_rdata ; // ram data input`
155			`wire [31:0] wb_xram_wdata ; // ram data input`
156
157			`wire wb_xram_stb ; // data-ram strobe`
158			`wire wb_xram_cyc ; // data-ram cycle`
159
160			`//----------------------------------------`
161
162			`digital_core u_core (`
163
164			`. reset_n (reset_n ),`
165			`. fastsim_mode (1'b1 ),`
166			`. mastermode (master_mode ),`
167
168			`. xtal_clk (xtal_clk ),`
169			`. clkout (app_clk ),`
170			`. reset_out_n (reset_out_n ),`
171	10	dinesha	`. ea_in (ea_in ), // internal ROM`
172	2	dinesha
173			`// Reg Bus Interface Signal`
174			`. ext_reg_cs (reg_cs ),`
175			`. ext_reg_tid (reg_id ),`
176			`. ext_reg_wr (reg_wr ),`
177			`. ext_reg_addr (reg_addr[14:0] ),`
178			`. ext_reg_wdata (reg_wdata ),`
179			`. ext_reg_be (reg_be ),`
180
181			`// Outputs`
182			`. ext_reg_rdata (reg_rdata ),`
183			`. ext_reg_ack (reg_ack ),`
184
185
186
187			`// UART Line Interface`
188			`.si (si ),`
189			`.so (so ),`
190
191
192			`.spi_sck (spi_sck ),`
193			`.spi_so (spi_so ),`
194			`.spi_si (spi_si ),`
195	10	dinesha	`.spi_cs_n (spi_cs_n )`
196	2	dinesha
197
198			`);`
199
200
201			`uart_agent tb_uart (`
202			`. test_clk (uart_clk_16x ),`
203			`. sin (si ),`
204			`. dsr_n ( ),`
205			`. cts_n ( ),`
206			`. dcd_n ( ),`
207
208			`. sout (so ),`
209			`. dtr_n (1'b0 ),`
210			`. rts_n (1'b0 ),`
211			`. out1_n (1'b0 ),`
212			`. out2_n (1'b0 )`
213			`);`
214
215
216			`//----------------------- SPI Agents`
217
218			`m25p20 i_m25p20_0 (`
219			`.c (spi_sck ),`
220			`.s (spi_cs_n[0] ), // Include selection logic`
221			`.w (1'b1 ), // Write protect is always disabled`
222			`.hold (1'b1 ), // Hold support not used`
223			`.data_in (spi_so ),`
224			`.data_out (spi_si )`
225			`);`
226
227
228			`AT45DB321 i_AT45DB321_0 (`
229			`.CSB (spi_cs_n[1] ),`
230			`.SCK (spi_sck ),`
231			`.SI (spi_so ),`
232			`.WPB (1'b1 ),`
233			`.RESETB (1'b1 ),`
234			`.RDY_BUSYB ( ),`
235			`.SO (spi_si )`
236			`);`
237			`/***************`
238			`spi_agent_3120 spi_agent_3120_0 (`
239			`.cs_b (spi_cs_n[2] ),`
240			`.spi_din (spi_si ),`
241			`.spi_dout (spi_so ),`
242			`.spi_clk (spi_sck )`
243			`);`
244
245			`spi_agent_3120 spi_agent_3120_1 (`
246			`.cs_b (spi_cs_n[3] ),`
247			`.spi_din (spi_si ),`
248			`.spi_dout (spi_so ),`
249			`.spi_clk (spi_sck )`
250			`);`
251			`*****************/`
252
253			`tb_glbl tb_glbl ();`
254
255
256			`ifdef DUMP_ENABLE
257			`initial begin`
258			`if ( $test$plusargs("DUMP") ) begin`
259			`$fsdbDumpfile("../dump/test_1.fsdb");`
260			`$fsdbDumpvars;`
261			`$fsdbDumpon;`
262			`end`
263			`end`
264			`endif
265
266			`initial begin //{`
267			`$display ("--> Dumpping the design");`
268			`$shm_open("simvision.shm");`
269			`$shm_probe("AC");`
270			`end //}`
271
272
273			`initial begin`
274
275			`if ( $test$plusargs("INTERNAL_ROM") ) begin`
276			`ea_in = 1;`
277			`master_mode = 1;`
278			`end else if ( $test$plusargs("EXTERNAL_ROM") ) begin`
279			`ea_in = 0;`
280			`master_mode = 1;`
281			`end else begin`
282			`ea_in = 0;`
283			`master_mode = 0;`
284			`end`
285
286			`TB_GLBL.init;
287
288			`#1000 wait(reset_out_n == 1);`
289
290			`if ( $test$plusargs("uart_test_1") )`
291			`uart_test1();`
292			`else if ( $test$plusargs("spi_test_1") )`
293			`spi_test1();`
294			`else begin`
295			`// 8051 Test Cases`
296			`#80000000`
297			`$display("time ",$time, "\n faulire: end of time\n \n");`
298			`end`
299
300			`TB_GLBL.test_stats;
301			`TB_GLBL.test_finish;
302			`#1000 $finish;`
303			`end`
304
305			`wire [7:0] p2_out = u_core.u_8051_core.p2_o;`
306			`wire [7:0] p3_out = u_core.u_8051_core.p3_o;`
307			`always @(p2_out or p3_out)`
308			`begin`
309			`if((p2_out == 8'haa) && // fib.c`
310			`(p3_out == 8'haa )) begin`
311			`$display("################################");`
312	4	dinesha	`$display("TEST STATUS : PASSED ");`
313	2	dinesha	`$display("################################");`
314			`#100`
315			`$finish;`
316			`end else if(p2_out == 8'h55) begin // fib.c`
317			`$display("");`
318			`$display("time ",$time," Error: %h", p3_out);`
319	4	dinesha	`$display("TEST STATUS : FAILED ");`
320	2	dinesha	`$display("");`
321			`#100`
322			`$finish;`
323			`end`
324			`end`
325
326
327
328
329			`include "uart_test1.v"
330			`include "spi_test1.v"
331			`include "tb_tasks.v"
332			`include "spi_tasks.v"
333
334
335			`endmodule`
336			`include "tb_glbl.v"