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[/] [oms8051mini/] [trunk/] [verif/] [testcase/] [i2cm_test1.v] - Blame information for rev 29

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/**********************************************************
             I2C Master Test
**********************************************************/
task i2cm_test1;
reg [7:0] rdata;
begin
 $display("############################################");
 $display("   Testing I2CM Read/Write Access           ");
 $display("############################################");
 
  @(posedge  app_clk);
  $display("---------- Initialize I2C Master ----------");
  //Wrire Prescale registers
   tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h0,8'hC7);
   tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h1,8'h00);
  // Core Enable
   tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h2,8'h80);
 
  // Writing Data
 
  $display("---------- Writing Data ----------");
  tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h3,8'h20); // Slave Addr + WR  
  tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h4,8'h90);
  rdata [1] = 1'b1;
  while(rdata[1]==1)
    tb_top.cpu_byte_read(`ADDR_SPACE_I2CM,8'h4,rdata);
 
  tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h3,8'h66);
  tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h4,8'h10);
 
  rdata [1] = 1'b1;
  while(rdata[1]==1)
    tb_top.cpu_byte_read(`ADDR_SPACE_I2CM,8'h4,rdata);
 
 /* Byte1: 12 */
  tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h3,8'h12);
  tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h4,8'h10); // No Stop + Write  
 
  rdata [1] = 1'b1;
  while(rdata[1]==1)
    tb_top.cpu_byte_read(`ADDR_SPACE_I2CM,8'h4,rdata);
 
 /* Byte1: 34 */
  tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h3,8'h34);
  tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h4,8'h10); // No Stop + Write 
 
  rdata [1] = 1'b1;
  while(rdata[1]==1)
    tb_top.cpu_byte_read(`ADDR_SPACE_I2CM,8'h4,rdata);
 
 /* Byte1: 56 */
  tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h3,8'h56);
  tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h4,8'h10); // No Stop + Write 
 
  rdata [1] = 1'b1;
  while(rdata[1]==1)
    tb_top.cpu_byte_read(`ADDR_SPACE_I2CM,8'h4,rdata);
 
 /* Byte1: 78 */
  tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h3,8'h78);
  tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h4,8'h50); // Stop + Write 
 
  rdata [1] = 1'b1;
  while(rdata[1]==1)
    tb_top.cpu_byte_read(`ADDR_SPACE_I2CM,8'h4,rdata);
 
  //Reading Data
 
  //Wrire Address
  $display("---------- Writing Data ----------");
  tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h3,8'h20);
  tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h4,8'h90);
  rdata [1] = 1'b1;
  while(rdata[1]==1)
    tb_top.cpu_byte_read(`ADDR_SPACE_I2CM,8'h4,rdata);
 
  tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h3,8'h66);
  tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h4,8'h50);
 
  rdata [1] = 1'b1;
  while(rdata[1]==1)
    tb_top.cpu_byte_read(`ADDR_SPACE_I2CM,8'h4,rdata);
 
  //Generate Read
  $display("---------- Writing Data ----------");
  tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h3,8'h21); // Slave Addr + RD  
  tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h4,8'h90);
  rdata [1] = 1'b1;
  while(rdata[1]==1)
    tb_top.cpu_byte_read(`ADDR_SPACE_I2CM,8'h4,rdata);
 
  /* BYTE-1 : 0x12  */
  tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h4,8'h20);  // RD + ACK
 
  rdata [1] = 1'b1;
  while(rdata[1]==1)
    tb_top.cpu_byte_read(`ADDR_SPACE_I2CM,8'h4,rdata);
 
  //Compare received data
  tb_top.cpu_byte_read_cmp(`ADDR_SPACE_I2CM,8'h3,8'h12);
 
  /* BYTE-2 : 0x34  */
  tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h4,8'h20);  // RD + ACK
 
  rdata [1] = 1'b1;
  while(rdata[1]==1)
    tb_top.cpu_byte_read(`ADDR_SPACE_I2CM,8'h4,rdata);
 
  //Compare received data
  tb_top.cpu_byte_read_cmp(`ADDR_SPACE_I2CM,8'h3,8'h34);
 
  /* BYTE-3 : 0x56  */
  tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h4,8'h20);  // RD + ACK
 
  rdata [1] = 1'b1;
  while(rdata[1]==1)
    tb_top.cpu_byte_read(`ADDR_SPACE_I2CM,8'h4,rdata);
 
  //Compare received data
  tb_top.cpu_byte_read_cmp(`ADDR_SPACE_I2CM,8'h3,8'h56);
 
  /* BYTE-4 : 0x78  */
  tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h4,8'h68);  // STOP + RD + NACK 
 
  rdata [1] = 1'b1;
  while(rdata[1]==1)
    tb_top.cpu_byte_read(`ADDR_SPACE_I2CM,8'h4,rdata);
 
  //Compare received data
  tb_top.cpu_byte_read_cmp(`ADDR_SPACE_I2CM,8'h3,8'h78);
 
  repeat(100)@(posedge app_clk);
end
endtask //}
 

Line No.	Rev	Author	Line
1	29	dinesha	`/**********************************************************`
2			`I2C Master Test`
3			`**********************************************************/`
4			`task i2cm_test1;`
5			`reg [7:0] rdata;`
6			`begin`
7			`$display("############################################");`
8			`$display(" Testing I2CM Read/Write Access ");`
9			`$display("############################################");`
10
11			`@(posedge app_clk);`
12			`$display("---------- Initialize I2C Master ----------");`
13			`//Wrire Prescale registers`
14			tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h0,8'hC7);
15			tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h1,8'h00);
16			`// Core Enable`
17			tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h2,8'h80);
18
19			`// Writing Data`
20
21			`$display("---------- Writing Data ----------");`
22			tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h3,8'h20); // Slave Addr + WR
23			tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h4,8'h90);
24			`rdata [1] = 1'b1;`
25			`while(rdata[1]==1)`
26			tb_top.cpu_byte_read(`ADDR_SPACE_I2CM,8'h4,rdata);
27
28			tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h3,8'h66);
29			tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h4,8'h10);
30
31			`rdata [1] = 1'b1;`
32			`while(rdata[1]==1)`
33			tb_top.cpu_byte_read(`ADDR_SPACE_I2CM,8'h4,rdata);
34
35			`/* Byte1: 12 */`
36			tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h3,8'h12);
37			tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h4,8'h10); // No Stop + Write
38
39			`rdata [1] = 1'b1;`
40			`while(rdata[1]==1)`
41			tb_top.cpu_byte_read(`ADDR_SPACE_I2CM,8'h4,rdata);
42
43			`/* Byte1: 34 */`
44			tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h3,8'h34);
45			tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h4,8'h10); // No Stop + Write
46
47			`rdata [1] = 1'b1;`
48			`while(rdata[1]==1)`
49			tb_top.cpu_byte_read(`ADDR_SPACE_I2CM,8'h4,rdata);
50
51			`/* Byte1: 56 */`
52			tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h3,8'h56);
53			tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h4,8'h10); // No Stop + Write
54
55			`rdata [1] = 1'b1;`
56			`while(rdata[1]==1)`
57			tb_top.cpu_byte_read(`ADDR_SPACE_I2CM,8'h4,rdata);
58
59			`/* Byte1: 78 */`
60			tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h3,8'h78);
61			tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h4,8'h50); // Stop + Write
62
63			`rdata [1] = 1'b1;`
64			`while(rdata[1]==1)`
65			tb_top.cpu_byte_read(`ADDR_SPACE_I2CM,8'h4,rdata);
66
67			`//Reading Data`
68
69			`//Wrire Address`
70			`$display("---------- Writing Data ----------");`
71			tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h3,8'h20);
72			tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h4,8'h90);
73			`rdata [1] = 1'b1;`
74			`while(rdata[1]==1)`
75			tb_top.cpu_byte_read(`ADDR_SPACE_I2CM,8'h4,rdata);
76
77			tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h3,8'h66);
78			tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h4,8'h50);
79
80			`rdata [1] = 1'b1;`
81			`while(rdata[1]==1)`
82			tb_top.cpu_byte_read(`ADDR_SPACE_I2CM,8'h4,rdata);
83
84			`//Generate Read`
85			`$display("---------- Writing Data ----------");`
86			tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h3,8'h21); // Slave Addr + RD
87			tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h4,8'h90);
88			`rdata [1] = 1'b1;`
89			`while(rdata[1]==1)`
90			tb_top.cpu_byte_read(`ADDR_SPACE_I2CM,8'h4,rdata);
91
92			`/* BYTE-1 : 0x12 */`
93			tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h4,8'h20); // RD + ACK
94
95			`rdata [1] = 1'b1;`
96			`while(rdata[1]==1)`
97			tb_top.cpu_byte_read(`ADDR_SPACE_I2CM,8'h4,rdata);
98
99			`//Compare received data`
100			tb_top.cpu_byte_read_cmp(`ADDR_SPACE_I2CM,8'h3,8'h12);
101
102			`/* BYTE-2 : 0x34 */`
103			tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h4,8'h20); // RD + ACK
104
105			`rdata [1] = 1'b1;`
106			`while(rdata[1]==1)`
107			tb_top.cpu_byte_read(`ADDR_SPACE_I2CM,8'h4,rdata);
108
109			`//Compare received data`
110			tb_top.cpu_byte_read_cmp(`ADDR_SPACE_I2CM,8'h3,8'h34);
111
112			`/* BYTE-3 : 0x56 */`
113			tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h4,8'h20); // RD + ACK
114
115			`rdata [1] = 1'b1;`
116			`while(rdata[1]==1)`
117			tb_top.cpu_byte_read(`ADDR_SPACE_I2CM,8'h4,rdata);
118
119			`//Compare received data`
120			tb_top.cpu_byte_read_cmp(`ADDR_SPACE_I2CM,8'h3,8'h56);
121
122			`/* BYTE-4 : 0x78 */`
123			tb_top.cpu_byte_write(`ADDR_SPACE_I2CM,8'h4,8'h68); // STOP + RD + NACK
124
125			`rdata [1] = 1'b1;`
126			`while(rdata[1]==1)`
127			tb_top.cpu_byte_read(`ADDR_SPACE_I2CM,8'h4,rdata);
128
129			`//Compare received data`
130			tb_top.cpu_byte_read_cmp(`ADDR_SPACE_I2CM,8'h3,8'h78);
131
132			`repeat(100)@(posedge app_clk);`
133			`end`
134			`endtask //}`
135

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Subversion Repositories oms8051mini

[/] [oms8051mini/] [trunk/] [verif/] [testcase/] [i2cm_test1.v] - Blame information for rev 29