OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] [o8_version.vhd] - Blame information for rev 334

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 270 jshamlet
-- Copyright (c)2020 Jeremy Seth Henry
2
-- All rights reserved.
3
--
4
-- Redistribution and use in source and binary forms, with or without
5
-- modification, are permitted provided that the following conditions are met:
6
--     * Redistributions of source code must retain the above copyright
7
--       notice, this list of conditions and the following disclaimer.
8
--     * Redistributions in binary form must reproduce the above copyright
9
--       notice, this list of conditions and the following disclaimer in the
10
--       documentation and/or other materials provided with the distribution,
11
--       where applicable (as part of a user interface, debugging port, etc.)
12
--
13
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
14
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
15
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
16
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
17
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
20
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23
--
24
-- VHDL Units :  o8_version
25 307 jshamlet
-- Description:  Provides 2 read-only values, which are set at compile time
26 270 jshamlet
--
27
-- Register Map:
28
-- Offset  Bitfield Description                        Read/Write
29 307 jshamlet
--   0x00  AAAAAAAA Minor Version                         (RO)
30
--   0x01  AAAAAAAA Major Version                         (RO)
31 334 jshamlet
--   0x02  AAAAAAAA SoC Version                           (RO)
32
--   0x03  AAAAAAAA Hardware Version                      (RO)
33 270 jshamlet
--
34
-- Revision History
35
-- Author          Date     Change
36
------------------ -------- ---------------------------------------------------
37
-- Seth Henry      10/21/20 Initial design
38
 
39
library ieee;
40
  use ieee.std_logic_1164.all;
41
  use ieee.std_logic_unsigned.all;
42
  use ieee.std_logic_arith.all;
43
  use ieee.std_logic_misc.all;
44
 
45
library work;
46
  use work.open8_pkg.all;
47
 
48
entity o8_version is
49
generic(
50
  Minor_Version              : DATA_TYPE := x"00";
51
  Major_Version              : DATA_TYPE := x"00";
52 334 jshamlet
  SoC_Version                : DATA_TYPE := x"00";
53
  Hardware_Version           : DATA_TYPE := x"00";
54 270 jshamlet
  Address                    : ADDRESS_TYPE
55
);
56
port(
57
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
58
  Rd_Data                    : out DATA_TYPE
59
);
60
end entity;
61
 
62
architecture behave of o8_version is
63
 
64
  alias Clock                is Open8_Bus.Clock;
65
  alias Reset                is Open8_Bus.Reset;
66
 
67 334 jshamlet
  constant User_Addr         : std_logic_vector(15 downto 2)
68
                               := Address(15 downto 2);
69
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 2);
70 270 jshamlet
  signal Addr_Match          : std_logic;
71
 
72 334 jshamlet
  alias  Reg_Sel_d           is Open8_Bus.Address(1 downto 0);
73
  signal Reg_Sel_q           : std_logic_vector(1 downto 0) := "00";
74 270 jshamlet
  signal Rd_En_d             : std_logic := '0';
75
  signal Rd_En_q             : std_logic := '0';
76
 
77
begin
78
 
79
  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
80
  Rd_En_d                    <= Addr_Match and Open8_Bus.Rd_En;
81
 
82
  io_reg: process( Clock, Reset )
83
  begin
84
    if( Reset = Reset_Level )then
85 334 jshamlet
      Reg_Sel_q              <= (others => '0');
86 270 jshamlet
      Rd_En_q                <= '0';
87
      Rd_Data                <= OPEN8_NULLBUS;
88
    elsif( rising_edge( Clock ) )then
89
      Reg_Sel_q              <= Reg_Sel_d;
90
 
91
      Rd_Data                <= OPEN8_NULLBUS;
92
      Rd_En_q                <= Rd_En_d;
93
 
94
      if( Rd_En_q = '1' )then
95 334 jshamlet
        case( Reg_Sel_q )is
96
          when "00" =>
97
            Rd_Data          <= Minor_Version;
98
          when "01" =>
99
            Rd_Data          <= Major_Version;
100
          when "10" =>
101
            Rd_Data          <= Soc_Version;
102
          when "11" =>
103
            Rd_Data          <= Hardware_Version;
104
          when others =>
105
            null;
106
        end case;
107
 
108 270 jshamlet
      end if;
109
    end if;
110
  end process;
111
 
112
end architecture;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.