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[/] [open_hitter/] [trunk/] [sim/] [rtl_sim/] [src/] [search_control_sim.vhd] - Blame information for rev 23

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1 20 stvhawes
--////////////////////////////////////////////////////////////////////
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--//                                                              ////
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--// search_control_sim.vhd                                       ////
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--//                                                              ////
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--// This file is part of the open_hitter opencores effort.       ////
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--// <http://www.opencores.org/cores/open_hitter/>                ////
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--//                                                              ////
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--// Module Description:                                          ////
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--// Simulation program (synthesizable)                           ////
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--// Unit test for search_control.vhd                             ////
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--//                                                              ////
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--// To Do:                                                       ////
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--//    #LOTS                                                     ////
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--//                                                              ////
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--// Author(s):                                                   ////
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--// - Stephen Hawes                                              ////
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--//                                                              ////
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--////////////////////////////////////////////////////////////////////
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--//                                                              ////
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--// Copyright (C) 2015 Stephen Hawes and OPENCORES.ORG           ////
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--//                                                              ////
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--// This source file may be used and distributed without         ////
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--// restriction provided that this copyright statement is not    ////
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--// removed from the file and that any derivative work contains  ////
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--// the original copyright notice and the associated disclaimer. ////
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--//                                                              ////
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--// This source file is free software; you can redistribute it   ////
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--// and/or modify it under the terms of the GNU Lesser General   ////
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--// Public License as published by the Free Software Foundation; ////
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--// either version 2.1 of the License, or (at your option) any   ////
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--// later version.                                               ////
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--//                                                              ////
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--// This source is distributed in the hope that it will be       ////
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--// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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--// PURPOSE. See the GNU Lesser General Public License for more  ////
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--// details.                                                     ////
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--//                                                              ////
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--// You should have received a copy of the GNU Lesser General    ////
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--// Public License along with this source; if not, download it   ////
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--// from <http://www.opencores.org/lgpl.shtml>                   ////
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--//                                                              ////
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--////////////////////////////////////////////////////////////////////
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--//
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--// \$Id\$  TAKE OUT THE \'s and this comment in order to get this to work
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--//
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--// CVS Revision History
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--//
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--// \$Log\$  TAKE OUT THE \'s and this comment in order to get this to work
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--//
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library ieee;
52
use ieee.std_logic_1164.all;
53
use ieee.numeric_std.ALL;
54
 
55
entity search_control_sim is
56
  port (
57
            RX_CLK: in std_logic;
58
            restart: in std_logic;
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            processing: out std_logic;
60
            result_one: out std_logic;
61
            result_two: out std_logic;
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            result_all_ok: out std_logic
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  );
64
end search_control_sim;
65
 
66
architecture behav of search_control_sim is
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   component search_control is
68
      generic ( searchitems : integer );
69
      port (
70
           RX_CLK: in std_logic;
71
           -- control flag(s) on the incoming bus
72
              search_px_valid_i: in std_logic;
73
           -- pxdata: in price_packet
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              search_px_type_i: in std_logic_vector(4 downto 0);
75
              search_buy_sell_i: in std_logic_vector(2 downto 0);   -- 111 buy, 000 sell
76
              search_px_i: in std_logic_vector(15 downto 0);     -- price
77
              search_qty_i: in std_logic_vector(15 downto 0);    -- quantity
78
              search_sec_i: in std_logic_vector(55 downto 0);    -- 7x 8bits securities identifier
79
              search_id_i: in std_logic_vector(15 downto 0);    -- unique/identifier/counter
80
           -- pxdata: out price_packet
81
              order_px_type_o: out std_logic_vector(4 downto 0);
82
              order_buy_sell_o: out std_logic_vector(2 downto 0);   -- 111 buy, 000 sell
83
              order_px_o: out std_logic_vector(15 downto 0);     -- price
84
              order_qty_o: out std_logic_vector(15 downto 0);    -- quantity
85
              order_sec_o: out std_logic_vector(55 downto 0);    -- 7x 8bits securities identifier
86
              order_id_o: out std_logic_vector(15 downto 0);     -- unique/identifier/counter
87
           -- control flag(s) on the outgoing bus
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              order_px_valid_o: out std_logic
89
        );
90
   end component;
91
   for search_control_0: search_control use entity work.search_control;
92
        -- control flag(s) on the incoming bus
93
           signal search_px_valid_i: std_logic;
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        -- pxdata: in price_packet
95
           signal search_px_type_i: std_logic_vector(4 downto 0);
96
           signal search_buy_sell_i: std_logic_vector(2 downto 0);   -- 111 buy, 000 sell
97
           signal search_px_i: std_logic_vector(15 downto 0);     -- price
98
           signal search_qty_i: std_logic_vector(15 downto 0);    -- quantity
99
           signal search_sec_i: std_logic_vector(55 downto 0);    -- 7x 8bits securities identifier
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           signal search_id_i: std_logic_vector(15 downto 0);    -- unique/identifier/counter
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        -- pxdata: out price_packet
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           signal order_px_type_o: std_logic_vector(4 downto 0);
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           signal order_buy_sell_o: std_logic_vector(2 downto 0);   -- 111 buy, 000 sell
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           signal order_px_o: std_logic_vector(15 downto 0);     -- price
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           signal order_qty_o: std_logic_vector(15 downto 0);    -- quantity
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           signal order_sec_o: std_logic_vector(55 downto 0);    -- 7x 8bits securities identifier
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           signal order_id_o: std_logic_vector(15 downto 0);     -- unique/identifier/counter
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        -- control
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           signal order_px_valid_o: std_logic;
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begin
111
    --  Component instantiation.
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        search_control_0: search_control
113 23 stvhawes
    --       generic map ( searchitems => 4 )   -- for test case when full at 4 orders
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           generic map ( searchitems => 200 )   -- a bit bigger
115 20 stvhawes
           port map (
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              RX_CLK => RX_CLK,
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           -- control flag(s) on the incoming bus
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              search_px_valid_i => search_px_valid_i,
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           -- pxdata: in price_packet
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              search_px_type_i => search_px_type_i,
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              search_buy_sell_i => search_buy_sell_i,
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              search_px_i => search_px_i,
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              search_qty_i => search_qty_i,
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              search_sec_i => search_sec_i,
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              search_id_i => search_id_i,
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           -- pxdata: out price_packet
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              order_px_type_o => order_px_type_o,
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              order_buy_sell_o => order_buy_sell_o,
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              order_px_o => order_px_o,
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              order_qty_o => order_qty_o,
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              order_sec_o => order_sec_o,
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              order_id_o => order_id_o,
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           -- control
134
              order_px_valid_o => order_px_valid_o
135
           );
136
    --
137
    process (RX_CLK) is
138
        type input_pattern_type is record
139
           -- control flag(s) on the incoming bus
140
              search_px_valid_i: std_logic;
141
           -- pxdata: in price_packet
142
              search_px_type_i: std_logic_vector(4 downto 0);
143
              search_buy_sell_i: std_logic_vector(2 downto 0);   -- 111 buy, 000 sell
144
              search_px_i: std_logic_vector(15 downto 0);     -- price
145
              search_qty_i: std_logic_vector(15 downto 0);    -- quantity
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              search_sec_i: std_logic_vector(55 downto 0);    -- 7x 8bits securities identifier
147
              -- search_id_i: std_logic_vector(15 downto 0);    -- unique/identifier/counter
148
         end record;
149
         type output_pattern_type is record
150
            -- pxdata: out price_packet
151
              order_px_type_o: std_logic_vector(4 downto 0);
152
              order_buy_sell_o: std_logic_vector(2 downto 0);   -- 111 buy, 000 sell
153
              order_px_o: std_logic_vector(15 downto 0);     -- price
154
              order_qty_o: std_logic_vector(15 downto 0);    -- quantity
155
              order_sec_o: std_logic_vector(55 downto 0);    -- 7x 8bits securities identifier
156
              order_id_o: std_logic_vector(15 downto 0);      -- unique/identifier/counter
157
         end record;
158
 
159
         --  The patterns to apply.
160
         constant zz_px: std_logic_vector(15 downto 0) := (others => 'Z');
161
         constant zz_qty: std_logic_vector(15 downto 0) := (others => 'Z');
162
         constant zz_sec: std_logic_vector(55 downto 0) := (others => 'Z');
163
         constant zz_id: std_logic_vector(15 downto 0) := (others => 'Z');
164
         constant set_qty: std_logic_vector(15 downto 0) := std_logic_vector'("0000000000010000");
165
         constant test_px: std_logic_vector(15 downto 0) := std_logic_vector'("0000000011100000");
166
         constant test_qty: std_logic_vector(15 downto 0) := std_logic_vector'("0000000000001100");
167
         constant remain_qty: std_logic_vector(15 downto 0) := std_logic_vector'("0000000000000100");
168
         constant test_sec0: std_logic_vector(55 downto 0) := std_logic_vector'(X"ABA544223478DC");
169
         constant test_sec1: std_logic_vector(55 downto 0) := std_logic_vector'(X"ABA543332178DC");
170
         constant test_sec2: std_logic_vector(55 downto 0) := std_logic_vector'(X"ABA234234378DC");
171
         constant test_sec3: std_logic_vector(55 downto 0) := std_logic_vector'(X"ABA534534578DC");
172
         constant test_id: std_logic_vector(15 downto 0) := std_logic_vector'("0110011001100110");
173
         constant other_id: std_logic_vector(15 downto 0) := std_logic_vector'("0000010001100010");
174
         constant other_px: std_logic_vector(15 downto 0) := std_logic_vector'("0000000000001110");
175
         constant other_sec: std_logic_vector(55 downto 0) := std_logic_vector'(X"CDC423354634AA");
176
         type input_pattern_array is array (natural range <>) of input_pattern_type;
177
           constant input_patterns : input_pattern_array :=
178
             ( ('1', std_logic_vector'("00000"), std_logic_vector'("ZZZ"), zz_px, zz_qty, zz_sec), -- 0 reset
179 21 stvhawes
               ('1', std_logic_vector'("10000"), std_logic_vector'("ZZZ"), zz_px, zz_qty, zz_sec), -- 1 nothing
180 20 stvhawes
               ('1', std_logic_vector'("00110"), std_logic_vector'("000"), test_px, set_qty, test_sec0),  -- 2 sec/set
181
               ('1', std_logic_vector'("00110"), std_logic_vector'("000"), test_px, set_qty, test_sec1),  -- 3 sec/set
182
               ('1', std_logic_vector'("00110"), std_logic_vector'("000"), test_px, set_qty, test_sec1),  -- 4 sec/set - repeat
183
               ('1', std_logic_vector'("00110"), std_logic_vector'("111"), test_px, set_qty, test_sec2),  -- 5 sec/set
184
               ('1', std_logic_vector'("00110"), std_logic_vector'("000"), test_px, set_qty, test_sec2),  -- 6 sec/set - diff buysell
185
               ('1', std_logic_vector'("00110"), std_logic_vector'("000"), test_px, set_qty, test_sec3),  -- 7 too many sec/set
186
               ('1', std_logic_vector'("11100"), std_logic_vector'("111"), test_px, test_qty, test_sec1),   -- 8 incoming px
187
               ('1', std_logic_vector'("11100"), std_logic_vector'("111"), test_px, zz_qty, other_sec),   -- 9 incoming px (wrong security)
188
               ('1', std_logic_vector'("11100"), std_logic_vector'("111"), other_px, test_qty, test_sec1),   -- 10incoming px (too low sale price)
189
               ('1', std_logic_vector'("11100"), std_logic_vector'("111"), test_px, test_qty, test_sec1) ); -- 11incoming px (part qty)
190
         type output_pattern_array is array (natural range <>) of output_pattern_type;
191
           constant output_patterns : output_pattern_array :=
192
             ( (std_logic_vector'("00000"), std_logic_vector'("ZZZ"), zz_px, zz_qty, zz_sec, zz_id),  -- 0 reset
193 21 stvhawes
               (std_logic_vector'("10000"), std_logic_vector'("ZZZ"), zz_px, zz_qty, zz_sec, zz_id),  -- 1 nothing
194 20 stvhawes
               (std_logic_vector'("01010"), std_logic_vector'("ZZZ"), zz_px, zz_qty, zz_sec, std_logic_vector'(X"0000")),  -- 2 sec/set
195
               (std_logic_vector'("01010"), std_logic_vector'("ZZZ"), zz_px, zz_qty, zz_sec, std_logic_vector'(X"0001")),  -- 3 sec/set
196
               (std_logic_vector'("00110"), std_logic_vector'("ZZZ"), zz_px, zz_qty, zz_sec, std_logic_vector'(X"0001")),  -- 4 sec/set
197
               (std_logic_vector'("01010"), std_logic_vector'("ZZZ"), zz_px, zz_qty, zz_sec, std_logic_vector'(X"0002")),  -- 5 sec/set
198
               (std_logic_vector'("01010"), std_logic_vector'("ZZZ"), zz_px, zz_qty, zz_sec, std_logic_vector'(X"0003")),  -- 6 sec/set
199
               (std_logic_vector'("11111"), std_logic_vector'("ZZZ"), zz_px, zz_qty, zz_sec, zz_id),  -- 7 bad sec/set (too many)
200
               (std_logic_vector'("11100"), std_logic_vector'("000"), test_px, test_qty, test_sec1, std_logic_vector'(X"0001")),  -- 8 incoming px
201
               (std_logic_vector'("11110"), std_logic_vector'("ZZZ"), zz_px, zz_qty, zz_sec, zz_id),  -- 9 incoming px (wrong security)
202
               (std_logic_vector'("11101"), std_logic_vector'("ZZZ"), zz_px, zz_qty, zz_sec, zz_id),  -- 10incoming px (too low sale price)
203
               (std_logic_vector'("11100"), std_logic_vector'("000"), test_px, remain_qty, test_sec1, std_logic_vector'(X"0001")) );  -- 11incoming px (part qty)
204
 
205
       -- process control
206
       variable pos: integer;
207
       variable i: integer := 99;   -- pattern id
208
       variable subcount: integer := 99;   -- pattern step
209
       variable res: integer;
210
       variable res_ok: std_logic;
211
    begin
212
       if rising_edge(RX_CLK) then
213
           if restart = '1'  then
214
              i := 0;
215
              subcount := 0;
216
              --
217
              result_all_ok <= '0';
218
              result_one <= '0';
219
              result_two <= '0';
220 21 stvhawes
              processing <= '1';
221
           else
222 20 stvhawes
 
223 21 stvhawes
             --  Pattern step
224
             if i < input_patterns'right+1 then
225 20 stvhawes
              -- diagnostics (uncomment)
226
              -- write (l, String'("Wrapper start loop i: "));
227
              -- write (l, i);
228
              -- writeline (output, l);
229
 
230 21 stvhawes
           --   processing <= '1';
231 20 stvhawes
 
232
              if subcount = 0 then
233
                 --  Set the inputs.
234
                 search_px_valid_i <= input_patterns(i).search_px_valid_i;
235
                 search_px_type_i <= input_patterns(i).search_px_type_i;
236
                 search_buy_sell_i <= input_patterns(i).search_buy_sell_i;
237
                 search_px_i <= input_patterns(i).search_px_i;
238
                 search_qty_i <= input_patterns(i).search_qty_i;
239
                 search_sec_i <= input_patterns(i).search_sec_i;
240
                 --search_id_i <= input_patterns(i).search_id_i;
241
                 res := 0;
242
                 res_ok := '1';
243
                 subcount := 1;
244
              else
245
                 -- reset the go instruction
246
                 search_px_valid_i <= '0';
247
                 --  Check the outputs.
248
 
249
                 -- diagnostics (uncomment)
250
                 -- write (l, String'("  Wrapper wait results r: "));
251
                 -- write (l, r);
252
                 -- write (l, String'(" order_px_valid_o: "));
253
                 -- write (l, std_logic'image(order_px_valid_o));
254
                 -- writeline (output, l);
255
 
256
                 -- got a return .. check it
257
                 if order_px_valid_o = '1' then
258
 
259 21 stvhawes
--                    result_one <= '1';
260
 
261 23 stvhawes
                    if i = 4 then
262 21 stvhawes
                       if order_px_type_o = output_patterns(i).order_px_type_o then
263
                          result_one <= '1';
264
                       end if;
265
                    end if;
266
 
267 23 stvhawes
                    if i = 8 then
268 21 stvhawes
                       if order_px_type_o = output_patterns(i).order_px_type_o then
269
                          result_two <= '1';
270
                       end if;
271
                    end if;
272
 
273 23 stvhawes
                    if i = 11 then
274 21 stvhawes
                       if order_px_type_o = output_patterns(i).order_px_type_o then
275
                          result_all_ok <= '1';
276
                       end if;
277
                    end if;
278
 
279
 
280
--                       if order_px_type_o /= output_patterns(i).order_px_type_o
281
--                        or order_buy_sell_o /= output_patterns(i).order_buy_sell_o 
282
--                        or order_px_o /= output_patterns(i).order_px_o 
283
--                        or order_qty_o /= output_patterns(i).order_qty_o then
284
--                        or order_sec_o /= output_patterns(i).order_sec_o 
285
--                        or order_id_o /= output_patterns(i).order_id_o  then
286 20 stvhawes
                       --
287 21 stvhawes
 
288
--                        res_ok := '0';
289
--                      else
290
--                         result_all_ok <= '1';                    
291
--                      end if;
292
 
293 20 stvhawes
                    res := res + 1;
294
                 end if;
295
 
296 21 stvhawes
                 if subcount = 6 then
297 20 stvhawes
                    -- check result
298 21 stvhawes
--                    if res /= 1 then
299
--                       res_ok := '0';
300
--                    end if;
301 20 stvhawes
 
302
                    -- reporting
303 21 stvhawes
--                    if i = 11 then
304
--                       result_all_ok <= res_ok;  -- success!
305
--                    elsif i = 6 then
306
--                       result_two <= res_ok;     -- loader tasks oka
307
--                    elsif i = 0 then
308
--                       result_one <= res_ok;     -- initial reset worked
309
--                    end if;
310 20 stvhawes
 
311
                    -- next pattern
312
                    i := i + 1;
313
                    subcount := 0;
314
                 else
315
                    subcount := subcount + 1;
316
                 end if;
317
              end if;
318
           else
319
              -- not processing (done or not started)
320
              processing <= '0';
321
           end if;   -- i
322 21 stvhawes
         end if;
323 20 stvhawes
       end if;        -- RX_CLK
324
    end process;
325
end behav;

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