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--! @file
--! @brief Arithmetic logic unit http://en.wikipedia.org/wiki/Arithmetic_logic_unit
 
--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith)
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
 
--! Use CPU Definitions package
use work.pkgOpenCPU32.all;
 
--! Cpu top level file
 
--! Include the Control Unit and datapath
entity openCpu is
    generic (n : integer := nBits - 1);                                                                 --! Generic value (Used to easily change the size of the Alu on the package)
         Port ( rst : in  STD_LOGIC;                                                                                            --! Reset signal
           clk : in  STD_LOGIC;                                                                                         --! Clock signal
           mem_rd : out  STD_LOGIC;                                                                                     --! Main memory Read enable
           mem_rd_addr : out  STD_LOGIC_VECTOR (n downto 0);                     --! Main memory Read address
           mem_wr : out  STD_LOGIC;                                                                                     --! Main memory Write enable
           mem_wr_addr : out  STD_LOGIC_VECTOR (n downto 0);                     --! Main memory Write address
                          mem_data_in : in  STD_LOGIC_VECTOR (n downto 0);                       --! Data comming from main memory
                          mem_data_out : out  STD_LOGIC_VECTOR (n downto 0)              --! Data to main memory
                          );
end openCpu;
 
--! @brief Cpu http://en.wikipedia.org/wiki/Central_processing_unit
--! @details This description will instantiate the components ControlUnit and DataPath
architecture Behavioral of openCpu is
COMPONENT DataPath is
    generic (n : integer := nBits - 1);                                                                 --! Generic value (Used to easily change the size of the Alu on the package)
         Port ( inputMm : in  STD_LOGIC_VECTOR (n downto 0);                     --! Input of Datapath from main memory       
                          inputImm : in  STD_LOGIC_VECTOR (n downto 0);                  --! Input of Datapath from imediate value (instructions...)
                          clk : in  STD_LOGIC;                                                                                          --! Clock signal
           outEn : in  typeEnDis;                                                                                       --! Enable/Disable datapath output
           aluOp : in  aluOps;                                                                                          --! Alu operations
           muxSel : in  STD_LOGIC_VECTOR (2 downto 0);                           --! Select inputs from dataPath(Memory,Imediate,RegisterFile,Alu)
                          muxRegFile : in STD_LOGIC_VECTOR(1 downto 0);                          --! Select Alu InputA (Memory,Imediate,RegFileA)
           regFileWriteAddr : in  generalRegisters;                                     --! General register write address
           regFileWriteEn : in  STD_LOGIC;                                                              --! RegisterFile write enable signal
           regFileReadAddrA : in  generalRegisters;                                     --! General register read address (PortA)
           regFileReadAddrB : in  generalRegisters;                                     --! General register read address (PortB)
           regFileEnA : in  STD_LOGIC;                                                                          --! Enable RegisterFile PortA
           regFileEnB : in  STD_LOGIC;                                                                          --! Enable RegisterFile PortB
                          outputDp : out  STD_LOGIC_VECTOR (n downto 0);                 --! DataPath Output
           dpFlags : out  STD_LOGIC_VECTOR (2 downto 0));                        --! Alu Flags
end COMPONENT;
 
COMPONENT ControlUnit is
    generic (n : integer := nBits - 1);                                                                 --! Generic value (Used to easily change the size of the Alu on the package)
         Port ( reset : in  STD_LOGIC;
           clk : in  STD_LOGIC;                                                                                         --! Main system clock
           FlagsDp : in  STD_LOGIC_VECTOR (2 downto 0);                          --! Flags comming from the Datapath
           DataDp : in  STD_LOGIC_VECTOR (n downto 0);                           --! Data comming from the Datapath
           MuxDp : out  STD_LOGIC_VECTOR (2 downto 0);                           --! Select on datapath data from (Memory, Imediate, RegFileA, RegFileB, AluOut)
                          MuxRegDp : out STD_LOGIC_VECTOR(1 downto 0);                           --! Select Alu InputA (Memory,Imediate,RegFileA)
           ImmDp : out  STD_LOGIC_VECTOR (n downto 0);                           --! Imediate value passed to the Datapath
           DpAluOp : out  aluOps;                                                                                       --! Alu operations
                          DpRegFileWriteAddr : out  generalRegisters;                           --! General register address to write
           DpRegFileWriteEn : out  STD_LOGIC;                                                   --! Enable register write
           DpRegFileReadAddrA : out  generalRegisters;                          --! General register address to read
           DpRegFileReadAddrB : out  generalRegisters;                          --! General register address to read
           DpRegFileReadEnA : out  STD_LOGIC;                                                   --! Enable register read (PortA)
           DpRegFileReadEnB : out  STD_LOGIC;                                                   --! Enable register read (PortB)
           MemoryDataReadEn : out std_logic;                                                            --! Enable Main memory read
                          MemoryDataWriteEn: out std_logic;                                                             --! Enable Main memory write
                          MemoryDataInput : in  STD_LOGIC_VECTOR (n downto 0);   --! Incoming data from main memory
           MemoryDataRdAddr : out  STD_LOGIC_VECTOR (n downto 0);        --! Main memory Read address
                          MemoryDataWrAddr : out  STD_LOGIC_VECTOR (n downto 0); --! Main memory Write address
           MemoryDataOut : out  STD_LOGIC_VECTOR (n downto 0));  --! Data to write on main memory
end COMPONENT;
 
signal InputImediate : STD_LOGIC_VECTOR (n downto 0);
signal enableOutputDp : typeEnDis;
signal aluOperations : aluOps;
signal InputDataPathSelector : STD_LOGIC_VECTOR (2 downto 0);
signal InputDataPathAluASelector : STD_LOGIC_VECTOR (1 downto 0);
signal registerFileWriteAddress : generalRegisters;
signal registerFileWriteEnable : STD_LOGIC;
signal registerFileReadAddressA : generalRegisters;
signal registerFileReadAddressB : generalRegisters;
signal registerFileReadEnableA : STD_LOGIC;
signal registerFileReadEnableB : STD_LOGIC;
signal dataPathOutput : STD_LOGIC_VECTOR (n downto 0);
signal dataPathFlags : STD_LOGIC_VECTOR (2 downto 0);
begin
        --! Instantiate the Datapath
   uDataPath: DataPath PORT MAP (
                        inputMm => InputImediate,
                        inputImm => mem_data_in,
                        clk => clk,
                        outEn => enableOutputDp,
                        aluOp => aluOperations,
                        muxSel => InputDataPathSelector,
                        muxRegFile => InputDataPathAluASelector,
                        regFileWriteAddr => registerFileWriteAddress,
                        regFileWriteEn => registerFileWriteEnable,
                        regFileReadAddrA => registerFileReadAddressA,
                        regFileReadAddrB => registerFileReadAddressB,
                        regFileEnA => registerFileReadEnableA,
                        regFileEnB => registerFileReadEnableB,
                        outputDp => dataPathOutput,
                        dpFlags => dataPathFlags
        );
 
        --! Instantiate the control unit
        uControlUnit: ControlUnit PORT MAP (
                        reset => rst,
                        clk => clk,
                        FlagsDp => dataPathFlags,
                        DataDp => dataPathOutput,
                        MuxDp => InputDataPathSelector,
                        MuxRegDp => InputDataPathAluASelector,
                        ImmDp => InputImediate,
                        DpAluOp => aluOperations,
                        DpRegFileWriteAddr => registerFileWriteAddress,
                        DpRegFileWriteEn => registerFileWriteEnable,
                        DpRegFileReadAddrA => registerFileReadAddressA,
                        DpRegFileReadAddrB => registerFileReadAddressB,
                        DpRegFileReadEnA => registerFileReadEnableA,
                        DpRegFileReadEnB => registerFileReadEnableB,
                        MemoryDataReadEn => mem_rd,
                        MemoryDataWriteEn => mem_wr,
                        MemoryDataInput => mem_data_in,
                        MemoryDataRdAddr => mem_rd_addr,
                        MemoryDataWrAddr => mem_wr_addr,
                        MemoryDataOut => mem_data_out
        );
 
end Behavioral;
 

Line No.	Rev	Author	Line
1	30	leonardoar	`--! @file`
2			`--! @brief Arithmetic logic unit http://en.wikipedia.org/wiki/Arithmetic_logic_unit`
3
4			`--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith)`
5			`library IEEE;`
6			`use ieee.std_logic_1164.all;`
7			`use ieee.std_logic_unsigned.all;`
8			`use ieee.std_logic_arith.all;`
9
10			`--! Use CPU Definitions package`
11			`use work.pkgOpenCPU32.all;`
12
13			`--! Cpu top level file`
14
15			`--! Include the Control Unit and datapath`
16			`entity openCpu is`
17			`generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)`
18			`Port ( rst : in STD_LOGIC; --! Reset signal`
19			`clk : in STD_LOGIC; --! Clock signal`
20			`mem_rd : out STD_LOGIC; --! Main memory Read enable`
21			`mem_rd_addr : out STD_LOGIC_VECTOR (n downto 0); --! Main memory Read address`
22			`mem_wr : out STD_LOGIC; --! Main memory Write enable`
23			`mem_wr_addr : out STD_LOGIC_VECTOR (n downto 0); --! Main memory Write address`
24			`mem_data_in : in STD_LOGIC_VECTOR (n downto 0); --! Data comming from main memory`
25			`mem_data_out : out STD_LOGIC_VECTOR (n downto 0) --! Data to main memory`
26			`);`
27			`end openCpu;`
28
29			`--! @brief Cpu http://en.wikipedia.org/wiki/Central_processing_unit`
30			`--! @details This description will instantiate the components ControlUnit and DataPath`
31			`architecture Behavioral of openCpu is`
32			`COMPONENT DataPath is`
33			`generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)`
34			`Port ( inputMm : in STD_LOGIC_VECTOR (n downto 0); --! Input of Datapath from main memory`
35			`inputImm : in STD_LOGIC_VECTOR (n downto 0); --! Input of Datapath from imediate value (instructions...)`
36			`clk : in STD_LOGIC; --! Clock signal`
37			`outEn : in typeEnDis; --! Enable/Disable datapath output`
38			`aluOp : in aluOps; --! Alu operations`
39			`muxSel : in STD_LOGIC_VECTOR (2 downto 0); --! Select inputs from dataPath(Memory,Imediate,RegisterFile,Alu)`
40			`muxRegFile : in STD_LOGIC_VECTOR(1 downto 0); --! Select Alu InputA (Memory,Imediate,RegFileA)`
41			`regFileWriteAddr : in generalRegisters; --! General register write address`
42			`regFileWriteEn : in STD_LOGIC; --! RegisterFile write enable signal`
43			`regFileReadAddrA : in generalRegisters; --! General register read address (PortA)`
44			`regFileReadAddrB : in generalRegisters; --! General register read address (PortB)`
45			`regFileEnA : in STD_LOGIC; --! Enable RegisterFile PortA`
46			`regFileEnB : in STD_LOGIC; --! Enable RegisterFile PortB`
47			`outputDp : out STD_LOGIC_VECTOR (n downto 0); --! DataPath Output`
48			`dpFlags : out STD_LOGIC_VECTOR (2 downto 0)); --! Alu Flags`
49			`end COMPONENT;`
50
51			`COMPONENT ControlUnit is`
52			`generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)`
53			`Port ( reset : in STD_LOGIC;`
54			`clk : in STD_LOGIC; --! Main system clock`
55			`FlagsDp : in STD_LOGIC_VECTOR (2 downto 0); --! Flags comming from the Datapath`
56			`DataDp : in STD_LOGIC_VECTOR (n downto 0); --! Data comming from the Datapath`
57			`MuxDp : out STD_LOGIC_VECTOR (2 downto 0); --! Select on datapath data from (Memory, Imediate, RegFileA, RegFileB, AluOut)`
58			`MuxRegDp : out STD_LOGIC_VECTOR(1 downto 0); --! Select Alu InputA (Memory,Imediate,RegFileA)`
59			`ImmDp : out STD_LOGIC_VECTOR (n downto 0); --! Imediate value passed to the Datapath`
60			`DpAluOp : out aluOps; --! Alu operations`
61			`DpRegFileWriteAddr : out generalRegisters; --! General register address to write`
62			`DpRegFileWriteEn : out STD_LOGIC; --! Enable register write`
63			`DpRegFileReadAddrA : out generalRegisters; --! General register address to read`
64			`DpRegFileReadAddrB : out generalRegisters; --! General register address to read`
65			`DpRegFileReadEnA : out STD_LOGIC; --! Enable register read (PortA)`
66			`DpRegFileReadEnB : out STD_LOGIC; --! Enable register read (PortB)`
67			`MemoryDataReadEn : out std_logic; --! Enable Main memory read`
68			`MemoryDataWriteEn: out std_logic; --! Enable Main memory write`
69			`MemoryDataInput : in STD_LOGIC_VECTOR (n downto 0); --! Incoming data from main memory`
70			`MemoryDataRdAddr : out STD_LOGIC_VECTOR (n downto 0); --! Main memory Read address`
71			`MemoryDataWrAddr : out STD_LOGIC_VECTOR (n downto 0); --! Main memory Write address`
72			`MemoryDataOut : out STD_LOGIC_VECTOR (n downto 0)); --! Data to write on main memory`
73			`end COMPONENT;`
74
75			`signal InputImediate : STD_LOGIC_VECTOR (n downto 0);`
76			`signal enableOutputDp : typeEnDis;`
77			`signal aluOperations : aluOps;`
78			`signal InputDataPathSelector : STD_LOGIC_VECTOR (2 downto 0);`
79			`signal InputDataPathAluASelector : STD_LOGIC_VECTOR (1 downto 0);`
80			`signal registerFileWriteAddress : generalRegisters;`
81			`signal registerFileWriteEnable : STD_LOGIC;`
82			`signal registerFileReadAddressA : generalRegisters;`
83			`signal registerFileReadAddressB : generalRegisters;`
84			`signal registerFileReadEnableA : STD_LOGIC;`
85			`signal registerFileReadEnableB : STD_LOGIC;`
86			`signal dataPathOutput : STD_LOGIC_VECTOR (n downto 0);`
87			`signal dataPathFlags : STD_LOGIC_VECTOR (2 downto 0);`
88			`begin`
89			`--! Instantiate the Datapath`
90			`uDataPath: DataPath PORT MAP (`
91			`inputMm => InputImediate,`
92			`inputImm => mem_data_in,`
93			`clk => clk,`
94			`outEn => enableOutputDp,`
95			`aluOp => aluOperations,`
96			`muxSel => InputDataPathSelector,`
97			`muxRegFile => InputDataPathAluASelector,`
98			`regFileWriteAddr => registerFileWriteAddress,`
99			`regFileWriteEn => registerFileWriteEnable,`
100			`regFileReadAddrA => registerFileReadAddressA,`
101			`regFileReadAddrB => registerFileReadAddressB,`
102			`regFileEnA => registerFileReadEnableA,`
103			`regFileEnB => registerFileReadEnableB,`
104			`outputDp => dataPathOutput,`
105			`dpFlags => dataPathFlags`
106			`);`
107
108			`--! Instantiate the control unit`
109			`uControlUnit: ControlUnit PORT MAP (`
110			`reset => rst,`
111			`clk => clk,`
112			`FlagsDp => dataPathFlags,`
113			`DataDp => dataPathOutput,`
114			`MuxDp => InputDataPathSelector,`
115			`MuxRegDp => InputDataPathAluASelector,`
116			`ImmDp => InputImediate,`
117			`DpAluOp => aluOperations,`
118			`DpRegFileWriteAddr => registerFileWriteAddress,`
119			`DpRegFileWriteEn => registerFileWriteEnable,`
120			`DpRegFileReadAddrA => registerFileReadAddressA,`
121			`DpRegFileReadAddrB => registerFileReadAddressB,`
122			`DpRegFileReadEnA => registerFileReadEnableA,`
123			`DpRegFileReadEnB => registerFileReadEnableB,`
124			`MemoryDataReadEn => mem_rd,`
125			`MemoryDataWriteEn => mem_wr,`
126			`MemoryDataInput => mem_data_in,`
127			`MemoryDataRdAddr => mem_rd_addr,`
128			`MemoryDataWrAddr => mem_wr_addr,`
129			`MemoryDataOut => mem_data_out`
130			`);`
131
132			`end Behavioral;`
133

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[/] [opencpu32/] [trunk/] [hdl/] [opencpu32/] [openCpu.vhd] - Blame information for rev 30