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[/] [opengfx430/] [trunk/] [core/] [rtl/] [verilog/] [ogfx_backend.v] - Blame information for rev 3

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//----------------------------------------------------------------------------
// Copyright (C) 2015 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
//
//----------------------------------------------------------------------------
//
// *File Name: ogfx_backend.v
//
// *Module Description:
//                      Backend module of the graphic controller.
//                      The purpose of this block is to:
//
//                          - fetch the data from the specified frame buffer
//                          - convert data depending on selected video mode
//
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//
//----------------------------------------------------------------------------
// $Rev$
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`ifdef OGFX_NO_INCLUDE
`else
`include "openGFX430_defines.v"
`endif
 
module  ogfx_backend (
 
// OUTPUTs
    refresh_data_o,                               // Display refresh data
    refresh_data_ready_o,                         // Display refresh new data is ready
 
    vid_ram_addr_o,                               // Video-RAM refresh address
    vid_ram_cen_o,                                // Video-RAM refresh enable (active low)
 
`ifdef WITH_PROGRAMMABLE_LUT
    lut_ram_addr_o,                               // LUT-RAM refresh address
    lut_ram_cen_o,                                // LUT-RAM refresh enable (active low)
`endif
 
// INPUTs
    mclk,                                         // Main system clock
    puc_rst,                                      // Main system reset
 
    display_width_i,                              // Display width
    display_height_i,                             // Display height
    display_size_i,                               // Display size (number of pixels)
    display_y_swap_i,                             // Display configuration: swap Y axis (horizontal symmetry)
    display_x_swap_i,                             // Display configuration: swap X axis (vertical symmetry)
    display_cl_swap_i,                            // Display configuration: swap column/lines
 
    gfx_mode_i,                                   // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)
 
`ifdef WITH_PROGRAMMABLE_LUT
    lut_ram_dout_i,                               // LUT-RAM data output
    lut_ram_dout_rdy_nxt_i,                       // LUT-RAM data output ready during next cycle
`endif
 
    vid_ram_dout_i,                               // Video-RAM data output
    vid_ram_dout_rdy_nxt_i,                       // Video-RAM data output ready during next cycle
 
    refresh_active_i,                             // Display refresh on going
    refresh_data_request_i,                       // Display refresh new data request
    refresh_frame_base_addr_i,                    // Refresh frame base address
    refresh_lut_select_i                          // Refresh LUT bank selection
);
 
// OUTPUTs
//=========
output        [15:0] refresh_data_o;              // Display refresh data
output               refresh_data_ready_o;        // Display refresh new data is ready
 
output [`VRAM_MSB:0] vid_ram_addr_o;              // Video-RAM refresh address
output               vid_ram_cen_o;               // Video-RAM refresh enable (active low)
 
`ifdef WITH_PROGRAMMABLE_LUT
output [`LRAM_MSB:0] lut_ram_addr_o;              // LUT-RAM refresh address
output               lut_ram_cen_o;               // LUT-RAM refresh enable (active low)
`endif
 
// INPUTs
//=========
input                mclk;                        // Main system clock
input                puc_rst;                     // Main system reset
 
input  [`LPIX_MSB:0] display_width_i;             // Display width
input  [`LPIX_MSB:0] display_height_i;            // Display height
input  [`SPIX_MSB:0] display_size_i;              // Display size (number of pixels)
input                display_y_swap_i;            // Display configuration: swap Y axis (horizontal symmetry)
input                display_x_swap_i;            // Display configuration: swap X axis (vertical symmetry)
input                display_cl_swap_i;           // Display configuration: swap column/lines
 
input          [2:0] gfx_mode_i;                  // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)
 
`ifdef WITH_PROGRAMMABLE_LUT
input         [15:0] lut_ram_dout_i;              // LUT-RAM data output
input                lut_ram_dout_rdy_nxt_i;      // LUT-RAM data output ready during next cycle
`endif
 
input         [15:0] vid_ram_dout_i;              // Video-RAM data output
input                vid_ram_dout_rdy_nxt_i;      // Video-RAM data output ready during next cycle
 
input                refresh_active_i;            // Display refresh on going
input                refresh_data_request_i;      // Display refresh new data request
input  [`APIX_MSB:0] refresh_frame_base_addr_i;   // Refresh frame base address
input          [1:0] refresh_lut_select_i;        // Refresh LUT bank selection
 
 
//=============================================================================
// 1)  WIRE, REGISTERS AND PARAMETER DECLARATION
//=============================================================================
 
// Wires
wire  [15:0] frame_data;
wire         frame_data_ready;
wire         frame_data_request;
 
 
//============================================================================
// 2) FRAME MEMORY ACCESS
//============================================================================
 
ogfx_backend_frame_fifo  ogfx_backend_frame_fifo_inst (
 
// OUTPUTs
    .frame_data_o                  ( frame_data                ),  // Frame data
    .frame_data_ready_o            ( frame_data_ready          ),  // Frame data ready
 
    .vid_ram_addr_o                ( vid_ram_addr_o            ),  // Video-RAM address
    .vid_ram_cen_o                 ( vid_ram_cen_o             ),  // Video-RAM enable (active low)
 
// INPUTs
    .mclk                          ( mclk                      ),  // Main system clock
    .puc_rst                       ( puc_rst                   ),  // Main system reset
 
    .display_width_i               ( display_width_i           ),  // Display width
    .display_height_i              ( display_height_i          ),  // Display height
    .display_size_i                ( display_size_i            ),  // Display size (number of pixels)
    .display_y_swap_i              ( display_y_swap_i          ),  // Display configuration: swap Y axis (horizontal symmetry)
    .display_x_swap_i              ( display_x_swap_i          ),  // Display configuration: swap X axis (vertical symmetry)
    .display_cl_swap_i             ( display_cl_swap_i         ),  // Display configuration: swap column/lines
 
    .frame_data_request_i          ( frame_data_request        ),  // Request for next frame data
 
    .gfx_mode_i                    ( gfx_mode_i                ),  // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)
 
    .vid_ram_dout_i                ( vid_ram_dout_i            ),  // Video-RAM data output
    .vid_ram_dout_rdy_nxt_i        ( vid_ram_dout_rdy_nxt_i    ),  // Video-RAM data output ready during next cycle
 
    .refresh_active_i              ( refresh_active_i          ),  // Display refresh on going
    .refresh_frame_base_addr_i     ( refresh_frame_base_addr_i )   // Refresh frame base address
);
 
 
//============================================================================
// 3) LUT MEMORY ACCESS
//============================================================================
 
ogfx_backend_lut_fifo  ogfx_backend_lut_fifo_inst (
 
// OUTPUTs
    .frame_data_request_o          ( frame_data_request        ),  // Request for next frame data
 
    .refresh_data_o                ( refresh_data_o            ),  // Display Refresh data
    .refresh_data_ready_o          ( refresh_data_ready_o      ),  // Display Refresh data ready
 
`ifdef WITH_PROGRAMMABLE_LUT
    .lut_ram_addr_o                ( lut_ram_addr_o            ),  // LUT-RAM address
    .lut_ram_cen_o                 ( lut_ram_cen_o             ),  // LUT-RAM enable (active low)
`endif
 
// INPUTs
    .mclk                          ( mclk                      ),  // Main system clock
    .puc_rst                       ( puc_rst                   ),  // Main system reset
 
    .frame_data_i                  ( frame_data                ),  // Frame data
    .frame_data_ready_i            ( frame_data_ready          ),  // Frame data ready
 
    .gfx_mode_i                    ( gfx_mode_i                ),  // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)
 
`ifdef WITH_PROGRAMMABLE_LUT
    .lut_ram_dout_i                ( lut_ram_dout_i            ),  // LUT-RAM data output
    .lut_ram_dout_rdy_nxt_i        ( lut_ram_dout_rdy_nxt_i    ),  // LUT-RAM data output ready during next cycle
`endif
 
    .refresh_active_i              ( refresh_active_i          ),  // Display refresh on going
    .refresh_data_request_i        ( refresh_data_request_i    ),  // Request for next refresh data
    .refresh_lut_select_i          ( refresh_lut_select_i      )   // Refresh LUT bank selection
);
 
 
endmodule // ogfx_backend
 
`ifdef OGFX_NO_INCLUDE
`else
`include "openGFX430_undefines.v"
`endif

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[/] [opengfx430/] [trunk/] [core/] [rtl/] [verilog/] [ogfx_backend.v] - Blame information for rev 3

Line No.	Rev	Author	Line
1	3	olivier.gi	`//----------------------------------------------------------------------------`
2			`// Copyright (C) 2015 Authors`
3			`//`
4			`// This source file may be used and distributed without restriction provided`
5			`// that this copyright statement is not removed from the file and that any`
6			`// derivative work contains the original copyright notice and the associated`
7			`// disclaimer.`
8			`//`
9			`// This source file is free software; you can redistribute it and/or modify`
10			`// it under the terms of the GNU Lesser General Public License as published`
11			`// by the Free Software Foundation; either version 2.1 of the License, or`
12			`// (at your option) any later version.`
13			`//`
14			`// This source is distributed in the hope that it will be useful, but WITHOUT`
15			`// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or`
16			`// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public`
17			`// License for more details.`
18			`//`
19			`// You should have received a copy of the GNU Lesser General Public License`
20			`// along with this source; if not, write to the Free Software Foundation,`
21			`// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA`
22			`//`
23			`//----------------------------------------------------------------------------`
24			`//`
25			`// *File Name: ogfx_backend.v`
26			`//`
27			`// *Module Description:`
28			`// Backend module of the graphic controller.`
29			`// The purpose of this block is to:`
30			`//`
31			`// - fetch the data from the specified frame buffer`
32			`// - convert data depending on selected video mode`
33			`//`
34			`// *Author(s):`
35			`// - Olivier Girard, olgirard@gmail.com`
36			`//`
37			`//----------------------------------------------------------------------------`
38			`// $Rev$`
39			`// $LastChangedBy$`
40			`// $LastChangedDate$`
41			`//----------------------------------------------------------------------------`
42			`ifdef OGFX_NO_INCLUDE
43			`else
44			`include "openGFX430_defines.v"
45			`endif
46
47			`module ogfx_backend (`
48
49			`// OUTPUTs`
50			`refresh_data_o, // Display refresh data`
51			`refresh_data_ready_o, // Display refresh new data is ready`
52
53			`vid_ram_addr_o, // Video-RAM refresh address`
54			`vid_ram_cen_o, // Video-RAM refresh enable (active low)`
55
56			`ifdef WITH_PROGRAMMABLE_LUT
57			`lut_ram_addr_o, // LUT-RAM refresh address`
58			`lut_ram_cen_o, // LUT-RAM refresh enable (active low)`
59			`endif
60
61			`// INPUTs`
62			`mclk, // Main system clock`
63			`puc_rst, // Main system reset`
64
65			`display_width_i, // Display width`
66			`display_height_i, // Display height`
67			`display_size_i, // Display size (number of pixels)`
68			`display_y_swap_i, // Display configuration: swap Y axis (horizontal symmetry)`
69			`display_x_swap_i, // Display configuration: swap X axis (vertical symmetry)`
70			`display_cl_swap_i, // Display configuration: swap column/lines`
71
72			`gfx_mode_i, // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)`
73
74			`ifdef WITH_PROGRAMMABLE_LUT
75			`lut_ram_dout_i, // LUT-RAM data output`
76			`lut_ram_dout_rdy_nxt_i, // LUT-RAM data output ready during next cycle`
77			`endif
78
79			`vid_ram_dout_i, // Video-RAM data output`
80			`vid_ram_dout_rdy_nxt_i, // Video-RAM data output ready during next cycle`
81
82			`refresh_active_i, // Display refresh on going`
83			`refresh_data_request_i, // Display refresh new data request`
84			`refresh_frame_base_addr_i, // Refresh frame base address`
85			`refresh_lut_select_i // Refresh LUT bank selection`
86			`);`
87
88			`// OUTPUTs`
89			`//=========`
90			`output [15:0] refresh_data_o; // Display refresh data`
91			`output refresh_data_ready_o; // Display refresh new data is ready`
92
93			output [`VRAM_MSB:0] vid_ram_addr_o; // Video-RAM refresh address
94			`output vid_ram_cen_o; // Video-RAM refresh enable (active low)`
95
96			`ifdef WITH_PROGRAMMABLE_LUT
97			output [`LRAM_MSB:0] lut_ram_addr_o; // LUT-RAM refresh address
98			`output lut_ram_cen_o; // LUT-RAM refresh enable (active low)`
99			`endif
100
101			`// INPUTs`
102			`//=========`
103			`input mclk; // Main system clock`
104			`input puc_rst; // Main system reset`
105
106			input [`LPIX_MSB:0] display_width_i; // Display width
107			input [`LPIX_MSB:0] display_height_i; // Display height
108			input [`SPIX_MSB:0] display_size_i; // Display size (number of pixels)
109			`input display_y_swap_i; // Display configuration: swap Y axis (horizontal symmetry)`
110			`input display_x_swap_i; // Display configuration: swap X axis (vertical symmetry)`
111			`input display_cl_swap_i; // Display configuration: swap column/lines`
112
113			`input [2:0] gfx_mode_i; // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)`
114
115			`ifdef WITH_PROGRAMMABLE_LUT
116			`input [15:0] lut_ram_dout_i; // LUT-RAM data output`
117			`input lut_ram_dout_rdy_nxt_i; // LUT-RAM data output ready during next cycle`
118			`endif
119
120			`input [15:0] vid_ram_dout_i; // Video-RAM data output`
121			`input vid_ram_dout_rdy_nxt_i; // Video-RAM data output ready during next cycle`
122
123			`input refresh_active_i; // Display refresh on going`
124			`input refresh_data_request_i; // Display refresh new data request`
125			input [`APIX_MSB:0] refresh_frame_base_addr_i; // Refresh frame base address
126			`input [1:0] refresh_lut_select_i; // Refresh LUT bank selection`
127
128
129			`//=============================================================================`
130			`// 1) WIRE, REGISTERS AND PARAMETER DECLARATION`
131			`//=============================================================================`
132
133			`// Wires`
134			`wire [15:0] frame_data;`
135			`wire frame_data_ready;`
136			`wire frame_data_request;`
137
138
139			`//============================================================================`
140			`// 2) FRAME MEMORY ACCESS`
141			`//============================================================================`
142
143			`ogfx_backend_frame_fifo ogfx_backend_frame_fifo_inst (`
144
145			`// OUTPUTs`
146			`.frame_data_o ( frame_data ), // Frame data`
147			`.frame_data_ready_o ( frame_data_ready ), // Frame data ready`
148
149			`.vid_ram_addr_o ( vid_ram_addr_o ), // Video-RAM address`
150			`.vid_ram_cen_o ( vid_ram_cen_o ), // Video-RAM enable (active low)`
151
152			`// INPUTs`
153			`.mclk ( mclk ), // Main system clock`
154			`.puc_rst ( puc_rst ), // Main system reset`
155
156			`.display_width_i ( display_width_i ), // Display width`
157			`.display_height_i ( display_height_i ), // Display height`
158			`.display_size_i ( display_size_i ), // Display size (number of pixels)`
159			`.display_y_swap_i ( display_y_swap_i ), // Display configuration: swap Y axis (horizontal symmetry)`
160			`.display_x_swap_i ( display_x_swap_i ), // Display configuration: swap X axis (vertical symmetry)`
161			`.display_cl_swap_i ( display_cl_swap_i ), // Display configuration: swap column/lines`
162
163			`.frame_data_request_i ( frame_data_request ), // Request for next frame data`
164
165			`.gfx_mode_i ( gfx_mode_i ), // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)`
166
167			`.vid_ram_dout_i ( vid_ram_dout_i ), // Video-RAM data output`
168			`.vid_ram_dout_rdy_nxt_i ( vid_ram_dout_rdy_nxt_i ), // Video-RAM data output ready during next cycle`
169
170			`.refresh_active_i ( refresh_active_i ), // Display refresh on going`
171			`.refresh_frame_base_addr_i ( refresh_frame_base_addr_i ) // Refresh frame base address`
172			`);`
173
174
175			`//============================================================================`
176			`// 3) LUT MEMORY ACCESS`
177			`//============================================================================`
178
179			`ogfx_backend_lut_fifo ogfx_backend_lut_fifo_inst (`
180
181			`// OUTPUTs`
182			`.frame_data_request_o ( frame_data_request ), // Request for next frame data`
183
184			`.refresh_data_o ( refresh_data_o ), // Display Refresh data`
185			`.refresh_data_ready_o ( refresh_data_ready_o ), // Display Refresh data ready`
186
187			`ifdef WITH_PROGRAMMABLE_LUT
188			`.lut_ram_addr_o ( lut_ram_addr_o ), // LUT-RAM address`
189			`.lut_ram_cen_o ( lut_ram_cen_o ), // LUT-RAM enable (active low)`
190			`endif
191
192			`// INPUTs`
193			`.mclk ( mclk ), // Main system clock`
194			`.puc_rst ( puc_rst ), // Main system reset`
195
196			`.frame_data_i ( frame_data ), // Frame data`
197			`.frame_data_ready_i ( frame_data_ready ), // Frame data ready`
198
199			`.gfx_mode_i ( gfx_mode_i ), // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)`
200
201			`ifdef WITH_PROGRAMMABLE_LUT
202			`.lut_ram_dout_i ( lut_ram_dout_i ), // LUT-RAM data output`
203			`.lut_ram_dout_rdy_nxt_i ( lut_ram_dout_rdy_nxt_i ), // LUT-RAM data output ready during next cycle`
204			`endif
205
206			`.refresh_active_i ( refresh_active_i ), // Display refresh on going`
207			`.refresh_data_request_i ( refresh_data_request_i ), // Request for next refresh data`
208			`.refresh_lut_select_i ( refresh_lut_select_i ) // Refresh LUT bank selection`
209			`);`
210
211
212			`endmodule // ogfx_backend`
213
214			`ifdef OGFX_NO_INCLUDE
215			`else
216			`include "openGFX430_undefines.v"
217			`endif