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[/] [openhmc/] [trunk/] [openHMC/] [rtl/] [hmc_controller/] [register_file/] [openhmc_rf.v] - Blame information for rev 15

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/*
 *                              .--------------. .----------------. .------------.
 *                             | .------------. | .--------------. | .----------. |
 *                             | | ____  ____ | | | ____    ____ | | |   ______ | |
 *                             | ||_   ||   _|| | ||_   \  /   _|| | | .' ___  || |
 *       ___  _ __   ___ _ __  | |  | |__| |  | | |  |   \/   |  | | |/ .'   \_|| |
 *      / _ \| '_ \ / _ \ '_ \ | |  |  __  |  | | |  | |\  /| |  | | || |       | |
 *       (_) | |_) |  __/ | | || | _| |  | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
 *      \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
 *           | |               | |            | | |              | | |          | |
 *           |_|               | '------------' | '--------------' | '----------' |
 *                              '--------------' '----------------' '------------'
 *
 *  openHMC - An Open Source Hybrid Memory Cube Controller
 *  (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
 *  www.ziti.uni-heidelberg.de
 *  B6, 26
 *  68159 Mannheim
 *  Germany
 *
 *  Contact: openhmc@ziti.uni-heidelberg.de
 *  http://ra.ziti.uni-heidelberg.de/openhmc
 *
 *   This source file is free software: you can redistribute it and/or modify
 *   it under the terms of the GNU Lesser General Public License as published by
 *   the Free Software Foundation, either version 3 of the License, or
 *   (at your option) any later version.
 *
 *   This source file is distributed in the hope that it will be useful,
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *   GNU Lesser General Public License for more details.
 *
 *   You should have received a copy of the GNU Lesser General Public License
 *   along with this source file.  If not, see <http://www.gnu.org/licenses/>.
 *
 *
 *  Module name: openhmc_rf
 *
 */
 
`default_nettype none
 
module openhmc_rf #(
    parameter NUM_LANES         = 8,
    parameter XIL_CNT_PIPELINED = 1,
    parameter LOG_MAX_RX_TOKENS = 8,
    parameter LOG_MAX_HMC_TOKENS= 8,
    parameter RF_COUNTER_SIZE   = 64,
    parameter HMC_RF_RWIDTH     = 0,
    parameter HMC_RF_AWIDTH     = 0,
    parameter HMC_RF_WWIDTH     = 0
) (
    input wire clk,
    input wire res_n,
    input wire [HMC_RF_AWIDTH-1:0] address,
    output reg invalid_address,
    output reg access_complete,
    input wire read_en,
    output reg[HMC_RF_RWIDTH-1:0] read_data,
    input wire write_en,
    input wire[HMC_RF_WWIDTH-1:0] write_data,
    input wire status_general_link_up_next,
    input wire status_general_link_training_next,
    input wire status_general_sleep_mode_next,
    input wire status_general_FERR_N_next,
    input wire status_general_lanes_reversed_next,
    input wire status_general_phy_tx_ready_next,
    input wire status_general_phy_rx_ready_next,
    input wire[LOG_MAX_HMC_TOKENS-1:0] status_general_hmc_tokens_remaining_next,
    input wire[LOG_MAX_RX_TOKENS-1:0] status_general_rx_tokens_remaining_next,
    input wire[NUM_LANES-1:0] status_general_lane_polarity_reversed_next,
    input wire[NUM_LANES-1:0] status_init_lane_descramblers_locked_next,
    input wire[NUM_LANES-1:0] status_init_descrambler_part_aligned_next,
    input wire[NUM_LANES-1:0] status_init_descrambler_aligned_next,
    input wire status_init_all_descramblers_aligned_next,
    input wire[2:0] status_init_rx_init_state_next,
    input wire[1:0] status_init_tx_init_state_next,
    output reg control_p_rst_n,
    output reg control_hmc_init_cont_set,
    output reg control_set_hmc_sleep,
    output reg control_warm_reset,
    output reg control_scrambler_disable,
    output reg control_run_length_enable,
    output reg[LOG_MAX_RX_TOKENS-1:0] control_rx_token_count,
    output reg[4:0] control_irtry_received_threshold,
    output reg[4:0] control_irtry_to_send,
    input wire[RF_COUNTER_SIZE-1:0] sent_p_cnt_next,
    input wire[RF_COUNTER_SIZE-1:0] sent_np_cnt_next,
    input wire[RF_COUNTER_SIZE-1:0] sent_r_cnt_next,
    input wire[RF_COUNTER_SIZE-1:0] poisoned_packets_cnt_next,
    input wire[RF_COUNTER_SIZE-1:0] rcvd_rsp_cnt_next,
    input wire tx_link_retries_count_countup,
    input wire errors_on_rx_count_countup,
    input wire run_length_bit_flip_count_countup,
    input wire error_abort_not_cleared_count_countup
);
    reg status_general_link_up;
    reg status_general_link_training;
    reg status_general_sleep_mode;
    reg status_general_FERR_N;
    reg status_general_lanes_reversed;
    reg status_general_phy_tx_ready;
    reg status_general_phy_rx_ready;
    reg[LOG_MAX_HMC_TOKENS-1:0] status_general_hmc_tokens_remaining;
    reg[LOG_MAX_RX_TOKENS-1:0] status_general_rx_tokens_remaining;
    reg[NUM_LANES-1:0] status_general_lane_polarity_reversed;
    reg[NUM_LANES-1:0] status_init_lane_descramblers_locked;
    reg[NUM_LANES-1:0] status_init_descrambler_part_aligned;
    reg[NUM_LANES-1:0] status_init_descrambler_aligned;
    reg status_init_all_descramblers_aligned;
    reg[2:0] status_init_rx_init_state;
    reg[1:0] status_init_tx_init_state;
    reg[RF_COUNTER_SIZE-1:0] sent_p_cnt;
    reg[RF_COUNTER_SIZE-1:0] sent_np_cnt;
    reg[RF_COUNTER_SIZE-1:0] sent_r_cnt;
    reg[RF_COUNTER_SIZE-1:0] poisoned_packets_cnt;
    reg[RF_COUNTER_SIZE-1:0] rcvd_rsp_cnt;
    reg rreinit;
    wire[47:0] tx_link_retries_count;
    wire[47:0] errors_on_rx_count;
    wire[47:0] run_length_bit_flip_count;
    wire[47:0] error_abort_not_cleared_count;
 
    `ifdef XILINX
        openhmc_counter48_wrapper_xilinx #(
            .INC_SIZE(1),
            .PIPELINED(XIL_CNT_PIPELINED)
        ) tx_link_retries_count_I (
            .clk(clk),
            .res_n(res_n),
            .inc_value(tx_link_retries_count_countup),
            .value(tx_link_retries_count)
        );
 
        openhmc_counter48_wrapper_xilinx #(
            .INC_SIZE(1),
            .PIPELINED(XIL_CNT_PIPELINED)
        ) errors_on_rx_count_I (
            .clk(clk),
            .res_n(res_n),
            .inc_value(errors_on_rx_count_countup),
            .value(errors_on_rx_count)
        );
 
        openhmc_counter48_wrapper_xilinx #(
            .INC_SIZE(1),
            .PIPELINED(XIL_CNT_PIPELINED)
        ) run_length_bit_flip_count_I (
            .clk(clk),
            .res_n(res_n),
            .inc_value(run_length_bit_flip_count_countup),
            .value(run_length_bit_flip_count)
        );
 
        openhmc_counter48_wrapper_xilinx #(
            .INC_SIZE(1),
            .PIPELINED(XIL_CNT_PIPELINED)
        ) error_abort_not_cleared_count_I (
            .clk(clk),
            .res_n(res_n),
            .inc_value(error_abort_not_cleared_count_countup),
            .value(error_abort_not_cleared_count)
        );
    `else
        openhmc_counter48 #(
                .DATASIZE(48)
        ) tx_link_retries_count_I (
                .clk(clk),
                .res_n(res_n),
                .increment(tx_link_retries_count_countup),
                .load_enable(rreinit),
                .value(tx_link_retries_count)
        );
 
        openhmc_counter48 #(
                .DATASIZE(48)
        ) errors_on_rx_count_I (
                .clk(clk),
                .res_n(res_n),
                .increment(errors_on_rx_count_countup),
                .load_enable(rreinit),
                .value(errors_on_rx_count)
        );
 
        openhmc_counter48 #(
                .DATASIZE(48)
        ) run_length_bit_flip_count_I (
                .clk(clk),
                .res_n(res_n),
                .increment(run_length_bit_flip_count_countup),
                .load_enable(rreinit),
                .value(run_length_bit_flip_count)
        );
 
        openhmc_counter48 #(
                .DATASIZE(48)
        ) error_abort_not_cleared_count_I (
                .clk(clk),
                .res_n(res_n),
                .increment(error_abort_not_cleared_count_countup),
                .load_enable(rreinit),
                .value(error_abort_not_cleared_count)
        );
    `endif
 
    //Register: status_general
    `ifdef ASYNC_RES
    always @(posedge clk or negedge res_n) `else
    always @(posedge clk) `endif
    begin
        `ifdef RESET_ALL
        if(!res_n)
        begin
            status_general_link_up          <= 1'h0;
            status_general_link_training    <= 1'h0;
            status_general_sleep_mode       <= 1'h0;
            status_general_FERR_N           <= 1'h0;
            status_general_lanes_reversed   <= 1'h0;
            status_general_phy_tx_ready     <= 1'h0;
            status_general_phy_rx_ready     <= 1'h0;
            status_general_hmc_tokens_remaining     <= {LOG_MAX_HMC_TOKENS{1'b0}};
            status_general_rx_tokens_remaining      <= {LOG_MAX_RX_TOKENS{1'b0}};
            status_general_lane_polarity_reversed   <= {NUM_LANES{1'b0}};
        end
        else
        `endif
        begin
            status_general_link_up      <= status_general_link_up_next;
            status_general_link_training<= status_general_link_training_next;
            status_general_sleep_mode   <= status_general_sleep_mode_next;
            status_general_FERR_N       <= status_general_FERR_N_next;
            status_general_lanes_reversed   <= status_general_lanes_reversed_next;
            status_general_phy_tx_ready     <= status_general_phy_tx_ready_next;
            status_general_phy_rx_ready     <= status_general_phy_rx_ready_next;
            status_general_hmc_tokens_remaining     <= status_general_hmc_tokens_remaining_next;
            status_general_rx_tokens_remaining      <= status_general_rx_tokens_remaining_next;
            status_general_lane_polarity_reversed   <= status_general_lane_polarity_reversed_next;
        end
 
    end
 
    //Register: status_init
    `ifdef ASYNC_RES
    always @(posedge clk or negedge res_n) `else
    always @(posedge clk) `endif
    begin
        `ifdef RESET_ALL
        if(!res_n)
        begin
            status_init_lane_descramblers_locked<= {NUM_LANES{1'b0}};
            status_init_descrambler_part_aligned<= {NUM_LANES{1'b0}};
            status_init_descrambler_aligned     <= {NUM_LANES{1'b0}};
            status_init_all_descramblers_aligned<= 1'h0;
            status_init_rx_init_state           <= 3'h0;
            status_init_tx_init_state           <= 2'h0;
        end
        else
        `endif
        begin
            status_init_lane_descramblers_locked<= status_init_lane_descramblers_locked_next;
            status_init_descrambler_part_aligned<= status_init_descrambler_part_aligned_next;
            status_init_descrambler_aligned     <= status_init_descrambler_aligned_next;
            status_init_all_descramblers_aligned<= status_init_all_descramblers_aligned_next;
            status_init_rx_init_state           <= status_init_rx_init_state_next;
            status_init_tx_init_state           <= status_init_tx_init_state_next;
        end
 
    end
 
    //Register: control
    `ifdef ASYNC_RES
    always @(posedge clk or negedge res_n) `else
    always @(posedge clk) `endif
    begin
 
        if(!res_n)
        begin
            control_p_rst_n             <= 1'h0;
            control_hmc_init_cont_set   <= 1'b0;
            control_set_hmc_sleep       <= 1'h0;
            control_warm_reset          <= 1'h0;
            control_scrambler_disable   <= 1'h0;
            control_run_length_enable   <= 1'h0;
            control_rx_token_count      <= {LOG_MAX_RX_TOKENS{1'b1}};
            control_irtry_received_threshold    <= 5'h10;
            control_irtry_to_send       <= 5'h18;
        end
        else
        begin
 
            if((address == 2) && write_en)
            begin
                control_p_rst_n <= write_data[0:0];
            end
 
            if((address == 2) && write_en)
            begin
                control_hmc_init_cont_set <= write_data[1:1];
            end
 
            if((address == 2) && write_en)
            begin
                control_set_hmc_sleep <= write_data[2:2];
            end
 
            if((address == 2) && write_en)
            begin
                control_warm_reset <= write_data[3:3];
            end
 
            if((address == 2) && write_en)
            begin
                control_scrambler_disable <= write_data[4:4];
            end
 
            if((address == 2) && write_en)
            begin
                control_run_length_enable <= write_data[5:5];
            end
 
            if((address == 2) && write_en)
            begin
                control_rx_token_count <= write_data[16+LOG_MAX_RX_TOKENS-1:16];
            end
 
            if((address == 2) && write_en)
            begin
                control_irtry_received_threshold <= write_data[36:32];
            end
 
            if((address == 2) && write_en)
            begin
                control_irtry_to_send <= write_data[44:40];
            end
 
        end
 
    end
 
    //Register: sent_p
    `ifdef ASYNC_RES
    always @(posedge clk or negedge res_n) `else
    always @(posedge clk) `endif
    begin
        `ifdef RESET_ALL
        if(!res_n)
        begin
            sent_p_cnt <= {RF_COUNTER_SIZE{1'b0}};
        end
        else
        `endif
        begin
            sent_p_cnt <= sent_p_cnt_next;
        end
 
    end
 
    //Register: sent_np
    `ifdef ASYNC_RES
    always @(posedge clk or negedge res_n) `else
    always @(posedge clk) `endif
    begin
        `ifdef RESET_ALL
        if(!res_n)
        begin
            sent_np_cnt <= {RF_COUNTER_SIZE{1'b0}};
        end
        else
        `endif
        begin
            sent_np_cnt <= sent_np_cnt_next;
        end
 
    end
 
    //Register: sent_r
    `ifdef ASYNC_RES
    always @(posedge clk or negedge res_n) `else
    always @(posedge clk) `endif
    begin
        `ifdef RESET_ALL
        if(!res_n)
        begin
            sent_r_cnt <= {RF_COUNTER_SIZE{1'b0}};
        end
        else
        `endif
        begin
            sent_r_cnt <= sent_r_cnt_next;
        end
 
    end
 
    //Register: poisoned_packets
    `ifdef ASYNC_RES
    always @(posedge clk or negedge res_n) `else
    always @(posedge clk) `endif
    begin
        `ifdef RESET_ALL
        if(!res_n)
        begin
            poisoned_packets_cnt <= {RF_COUNTER_SIZE{1'b0}};
        end
        else
        `endif
        begin
            poisoned_packets_cnt <= poisoned_packets_cnt_next;
        end
 
    end
 
    //Register: rcvd_rsp
    `ifdef ASYNC_RES
    always @(posedge clk or negedge res_n) `else
    always @(posedge clk) `endif
    begin
        `ifdef RESET_ALL
        if(!res_n)
        begin
            rcvd_rsp_cnt <= {RF_COUNTER_SIZE{1'b0}};
        end
        else
        `endif
        begin
            rcvd_rsp_cnt <= rcvd_rsp_cnt_next;
        end
 
    end
 
    //Register: counter_reset
    `ifdef ASYNC_RES
    always @(posedge clk or negedge res_n) `else
    always @(posedge clk) `endif
    begin
 
        if(!res_n)
        begin
            rreinit <= 1'b0;
        end
        else
        begin
 
            if((address == 8) && write_en)
            begin
                rreinit <= 1'b1;
            end
            else
            begin
                rreinit <= 1'b0;
            end
        end
 
    end
 
    //Address Decoder Software Read:
    `ifdef ASYNC_RES
    always @(posedge clk or negedge res_n) `else
    always @(posedge clk) `endif
    begin
 
        if(!res_n)
        begin
            invalid_address <= 1'b0;
            access_complete <= 1'b0;
            read_data       <= {HMC_RF_RWIDTH{1'b0}};
        end
        else
        begin
 
            casex(address)
                4'h0:
                begin
                    read_data       <= {HMC_RF_RWIDTH{1'b0}};
                    read_data[0:0] <= status_general_link_up;
                    read_data[1:1] <= status_general_link_training;
                    read_data[2:2] <= status_general_sleep_mode;
                    read_data[3:3] <= status_general_FERR_N;
                    read_data[4:4] <= status_general_lanes_reversed;
                    read_data[8:8] <= status_general_phy_tx_ready;
                    read_data[9:9] <= status_general_phy_rx_ready;
                    read_data[16+LOG_MAX_HMC_TOKENS-1:16] <= status_general_hmc_tokens_remaining;
                    read_data[32+LOG_MAX_RX_TOKENS-1:32] <= status_general_rx_tokens_remaining;
                    read_data[63:48] <= status_general_lane_polarity_reversed;
                    invalid_address <= write_en;
                    access_complete <= read_en || write_en;
                end
                4'h1:
                begin
                    read_data       <= {HMC_RF_RWIDTH{1'b0}};
                    read_data[NUM_LANES-1:0] <= status_init_lane_descramblers_locked;
                    read_data[16+NUM_LANES-1:16] <= status_init_descrambler_part_aligned;
                    read_data[32+NUM_LANES-1:32] <= status_init_descrambler_aligned;
                    read_data[48:48] <= status_init_all_descramblers_aligned;
                    read_data[51:49] <= status_init_rx_init_state;
                    read_data[53:52] <= status_init_tx_init_state;
                    invalid_address <= write_en;
                    access_complete <= read_en || write_en;
                end
                4'h2:
                begin
                    read_data       <= {HMC_RF_RWIDTH{1'b0}};
                    read_data[0:0] <= control_p_rst_n;
                    read_data[1:1] <= control_hmc_init_cont_set;
                    read_data[2:2] <= control_set_hmc_sleep;
                    read_data[3:3] <= control_warm_reset;
                    read_data[4:4] <= control_scrambler_disable;
                    read_data[5:5] <= control_run_length_enable;
                    read_data[16+LOG_MAX_RX_TOKENS-1:16] <= control_rx_token_count;
                    read_data[36:32] <= control_irtry_received_threshold;
                    read_data[44:40] <= control_irtry_to_send;
                    invalid_address <= 1'b0;
                    access_complete <= read_en || write_en;
                end
                4'h3:
                begin
                    read_data       <= {HMC_RF_RWIDTH{1'b0}};
                    read_data[RF_COUNTER_SIZE-1:0] <= sent_p_cnt;
                    invalid_address <= write_en;
                    access_complete <= read_en || write_en;
                end
                4'h4:
                begin
                    read_data       <= {HMC_RF_RWIDTH{1'b0}};
                    read_data[RF_COUNTER_SIZE-1:0] <= sent_np_cnt;
                    invalid_address <= write_en;
                    access_complete <= read_en || write_en;
                end
                4'h5:
                begin
                    read_data       <= {HMC_RF_RWIDTH{1'b0}};
                    read_data[RF_COUNTER_SIZE-1:0] <= sent_r_cnt;
                    invalid_address <= write_en;
                    access_complete <= read_en || write_en;
                end
                4'h6:
                begin
                    read_data       <= {HMC_RF_RWIDTH{1'b0}};
                    read_data[RF_COUNTER_SIZE-1:0] <= poisoned_packets_cnt;
                    invalid_address <= write_en;
                    access_complete <= read_en || write_en;
                end
                4'h7:
                begin
                    read_data       <= {HMC_RF_RWIDTH{1'b0}};
                    read_data[RF_COUNTER_SIZE-1:0] <= rcvd_rsp_cnt;
                    invalid_address <= write_en;
                    access_complete <= read_en || write_en;
                end
                4'h8:
                begin
                    read_data       <= {HMC_RF_RWIDTH{1'b0}};
                    invalid_address <= read_en;
                    access_complete <= read_en || write_en;
                end
                4'h9:
                begin
                    read_data       <= {HMC_RF_RWIDTH{1'b0}};
                    read_data[47:0] <= tx_link_retries_count;
                    invalid_address <= write_en;
                    access_complete <= read_en || write_en;
                end
                4'ha:
                begin
                    read_data       <= {HMC_RF_RWIDTH{1'b0}};
                    read_data[47:0] <= errors_on_rx_count;
                    invalid_address <= write_en;
                    access_complete <= read_en || write_en;
                end
                4'hb:
                begin
                    read_data       <= {HMC_RF_RWIDTH{1'b0}};
                    read_data[47:0] <= run_length_bit_flip_count;
                    invalid_address <= write_en;
                    access_complete <= read_en || write_en;
                end
                4'hc:
                begin
                    read_data       <= {HMC_RF_RWIDTH{1'b0}};
                    read_data[47:0] <= error_abort_not_cleared_count;
                    invalid_address <= write_en;
                    access_complete <= read_en || write_en;
                end
                default:
                begin
                    read_data       <= {HMC_RF_RWIDTH{1'b0}};
                    invalid_address <= read_en || write_en;
                    access_complete <= read_en || write_en;
                end
 
            endcase
        end
 
    end
 
endmodule
 
`default_nettype wire

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[/] [openhmc/] [trunk/] [openHMC/] [rtl/] [hmc_controller/] [register_file/] [openhmc_rf.v] - Blame information for rev 15

Line No.	Rev	Author	Line
1	15	juko	`/*`
2			`* .--------------. .----------------. .------------.`
3			`* \| .------------. \| .--------------. \| .----------. \|`
4			`* \| \| ____ ____ \| \| \| ____ ____ \| \| \| ______ \| \|`
5			`* \| \|\|_ \|\| _\|\| \| \|\|_ \ / _\|\| \| \| .' ___ \|\| \|`
6			`* ___ _ __ ___ _ __ \| \| \| \|__\| \| \| \| \| \| \/ \| \| \| \|/ .' \_\|\| \|`
7			`* / _ \\| '_ \ / _ \ '_ \ \| \| \| __ \| \| \| \| \| \|\ /\| \| \| \| \|\| \| \| \|`
8			* (_) \| \|_) \| __/ \| \| \|\| \| _\| \| \| \|_ \| \| \| _\| \|_\/_\| \|_ \| \| \|\ `.___.'\\| \|
9			* \___/\| .__/ \___\|_\| \|_\|\| \|\|____\|\|____\|\| \| \|\|_____\|\|_____\|\| \| \| `._____.'\| \|
10			`* \| \| \| \| \| \| \| \| \| \| \| \|`
11			`* \|_\| \| '------------' \| '--------------' \| '----------' \|`
12			`* '--------------' '----------------' '------------'`
13			`*`
14			`* openHMC - An Open Source Hybrid Memory Cube Controller`
15			`* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg`
16			`* www.ziti.uni-heidelberg.de`
17			`* B6, 26`
18			`* 68159 Mannheim`
19			`* Germany`
20			`*`
21			`* Contact: openhmc@ziti.uni-heidelberg.de`
22			`* http://ra.ziti.uni-heidelberg.de/openhmc`
23			`*`
24			`* This source file is free software: you can redistribute it and/or modify`
25			`* it under the terms of the GNU Lesser General Public License as published by`
26			`* the Free Software Foundation, either version 3 of the License, or`
27			`* (at your option) any later version.`
28			`*`
29			`* This source file is distributed in the hope that it will be useful,`
30			`* but WITHOUT ANY WARRANTY; without even the implied warranty of`
31			`* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
32			`* GNU Lesser General Public License for more details.`
33			`*`
34			`* You should have received a copy of the GNU Lesser General Public License`
35			`* along with this source file. If not, see <http://www.gnu.org/licenses/>.`
36			`*`
37			`*`
38			`* Module name: openhmc_rf`
39			`*`
40			`*/`
41
42			`default_nettype none
43
44			`module openhmc_rf #(`
45			`parameter NUM_LANES = 8,`
46			`parameter XIL_CNT_PIPELINED = 1,`
47			`parameter LOG_MAX_RX_TOKENS = 8,`
48			`parameter LOG_MAX_HMC_TOKENS= 8,`
49			`parameter RF_COUNTER_SIZE = 64,`
50			`parameter HMC_RF_RWIDTH = 0,`
51			`parameter HMC_RF_AWIDTH = 0,`
52			`parameter HMC_RF_WWIDTH = 0`
53			`) (`
54			`input wire clk,`
55			`input wire res_n,`
56			`input wire [HMC_RF_AWIDTH-1:0] address,`
57			`output reg invalid_address,`
58			`output reg access_complete,`
59			`input wire read_en,`
60			`output reg[HMC_RF_RWIDTH-1:0] read_data,`
61			`input wire write_en,`
62			`input wire[HMC_RF_WWIDTH-1:0] write_data,`
63			`input wire status_general_link_up_next,`
64			`input wire status_general_link_training_next,`
65			`input wire status_general_sleep_mode_next,`
66			`input wire status_general_FERR_N_next,`
67			`input wire status_general_lanes_reversed_next,`
68			`input wire status_general_phy_tx_ready_next,`
69			`input wire status_general_phy_rx_ready_next,`
70			`input wire[LOG_MAX_HMC_TOKENS-1:0] status_general_hmc_tokens_remaining_next,`
71			`input wire[LOG_MAX_RX_TOKENS-1:0] status_general_rx_tokens_remaining_next,`
72			`input wire[NUM_LANES-1:0] status_general_lane_polarity_reversed_next,`
73			`input wire[NUM_LANES-1:0] status_init_lane_descramblers_locked_next,`
74			`input wire[NUM_LANES-1:0] status_init_descrambler_part_aligned_next,`
75			`input wire[NUM_LANES-1:0] status_init_descrambler_aligned_next,`
76			`input wire status_init_all_descramblers_aligned_next,`
77			`input wire[2:0] status_init_rx_init_state_next,`
78			`input wire[1:0] status_init_tx_init_state_next,`
79			`output reg control_p_rst_n,`
80			`output reg control_hmc_init_cont_set,`
81			`output reg control_set_hmc_sleep,`
82			`output reg control_warm_reset,`
83			`output reg control_scrambler_disable,`
84			`output reg control_run_length_enable,`
85			`output reg[LOG_MAX_RX_TOKENS-1:0] control_rx_token_count,`
86			`output reg[4:0] control_irtry_received_threshold,`
87			`output reg[4:0] control_irtry_to_send,`
88			`input wire[RF_COUNTER_SIZE-1:0] sent_p_cnt_next,`
89			`input wire[RF_COUNTER_SIZE-1:0] sent_np_cnt_next,`
90			`input wire[RF_COUNTER_SIZE-1:0] sent_r_cnt_next,`
91			`input wire[RF_COUNTER_SIZE-1:0] poisoned_packets_cnt_next,`
92			`input wire[RF_COUNTER_SIZE-1:0] rcvd_rsp_cnt_next,`
93			`input wire tx_link_retries_count_countup,`
94			`input wire errors_on_rx_count_countup,`
95			`input wire run_length_bit_flip_count_countup,`
96			`input wire error_abort_not_cleared_count_countup`
97			`);`
98			`reg status_general_link_up;`
99			`reg status_general_link_training;`
100			`reg status_general_sleep_mode;`
101			`reg status_general_FERR_N;`
102			`reg status_general_lanes_reversed;`
103			`reg status_general_phy_tx_ready;`
104			`reg status_general_phy_rx_ready;`
105			`reg[LOG_MAX_HMC_TOKENS-1:0] status_general_hmc_tokens_remaining;`
106			`reg[LOG_MAX_RX_TOKENS-1:0] status_general_rx_tokens_remaining;`
107			`reg[NUM_LANES-1:0] status_general_lane_polarity_reversed;`
108			`reg[NUM_LANES-1:0] status_init_lane_descramblers_locked;`
109			`reg[NUM_LANES-1:0] status_init_descrambler_part_aligned;`
110			`reg[NUM_LANES-1:0] status_init_descrambler_aligned;`
111			`reg status_init_all_descramblers_aligned;`
112			`reg[2:0] status_init_rx_init_state;`
113			`reg[1:0] status_init_tx_init_state;`
114			`reg[RF_COUNTER_SIZE-1:0] sent_p_cnt;`
115			`reg[RF_COUNTER_SIZE-1:0] sent_np_cnt;`
116			`reg[RF_COUNTER_SIZE-1:0] sent_r_cnt;`
117			`reg[RF_COUNTER_SIZE-1:0] poisoned_packets_cnt;`
118			`reg[RF_COUNTER_SIZE-1:0] rcvd_rsp_cnt;`
119			`reg rreinit;`
120			`wire[47:0] tx_link_retries_count;`
121			`wire[47:0] errors_on_rx_count;`
122			`wire[47:0] run_length_bit_flip_count;`
123			`wire[47:0] error_abort_not_cleared_count;`
124
125			`ifdef XILINX
126			`openhmc_counter48_wrapper_xilinx #(`
127			`.INC_SIZE(1),`
128			`.PIPELINED(XIL_CNT_PIPELINED)`
129			`) tx_link_retries_count_I (`
130			`.clk(clk),`
131			`.res_n(res_n),`
132			`.inc_value(tx_link_retries_count_countup),`
133			`.value(tx_link_retries_count)`
134			`);`
135
136			`openhmc_counter48_wrapper_xilinx #(`
137			`.INC_SIZE(1),`
138			`.PIPELINED(XIL_CNT_PIPELINED)`
139			`) errors_on_rx_count_I (`
140			`.clk(clk),`
141			`.res_n(res_n),`
142			`.inc_value(errors_on_rx_count_countup),`
143			`.value(errors_on_rx_count)`
144			`);`
145
146			`openhmc_counter48_wrapper_xilinx #(`
147			`.INC_SIZE(1),`
148			`.PIPELINED(XIL_CNT_PIPELINED)`
149			`) run_length_bit_flip_count_I (`
150			`.clk(clk),`
151			`.res_n(res_n),`
152			`.inc_value(run_length_bit_flip_count_countup),`
153			`.value(run_length_bit_flip_count)`
154			`);`
155
156			`openhmc_counter48_wrapper_xilinx #(`
157			`.INC_SIZE(1),`
158			`.PIPELINED(XIL_CNT_PIPELINED)`
159			`) error_abort_not_cleared_count_I (`
160			`.clk(clk),`
161			`.res_n(res_n),`
162			`.inc_value(error_abort_not_cleared_count_countup),`
163			`.value(error_abort_not_cleared_count)`
164			`);`
165			`else
166			`openhmc_counter48 #(`
167			`.DATASIZE(48)`
168			`) tx_link_retries_count_I (`
169			`.clk(clk),`
170			`.res_n(res_n),`
171			`.increment(tx_link_retries_count_countup),`
172			`.load_enable(rreinit),`
173			`.value(tx_link_retries_count)`
174			`);`
175
176			`openhmc_counter48 #(`
177			`.DATASIZE(48)`
178			`) errors_on_rx_count_I (`
179			`.clk(clk),`
180			`.res_n(res_n),`
181			`.increment(errors_on_rx_count_countup),`
182			`.load_enable(rreinit),`
183			`.value(errors_on_rx_count)`
184			`);`
185
186			`openhmc_counter48 #(`
187			`.DATASIZE(48)`
188			`) run_length_bit_flip_count_I (`
189			`.clk(clk),`
190			`.res_n(res_n),`
191			`.increment(run_length_bit_flip_count_countup),`
192			`.load_enable(rreinit),`
193			`.value(run_length_bit_flip_count)`
194			`);`
195
196			`openhmc_counter48 #(`
197			`.DATASIZE(48)`
198			`) error_abort_not_cleared_count_I (`
199			`.clk(clk),`
200			`.res_n(res_n),`
201			`.increment(error_abort_not_cleared_count_countup),`
202			`.load_enable(rreinit),`
203			`.value(error_abort_not_cleared_count)`
204			`);`
205			`endif
206
207			`//Register: status_general`
208			`ifdef ASYNC_RES
209			always @(posedge clk or negedge res_n) `else
210			always @(posedge clk) `endif
211			`begin`
212			`ifdef RESET_ALL
213			`if(!res_n)`
214			`begin`
215			`status_general_link_up <= 1'h0;`
216			`status_general_link_training <= 1'h0;`
217			`status_general_sleep_mode <= 1'h0;`
218			`status_general_FERR_N <= 1'h0;`
219			`status_general_lanes_reversed <= 1'h0;`
220			`status_general_phy_tx_ready <= 1'h0;`
221			`status_general_phy_rx_ready <= 1'h0;`
222			`status_general_hmc_tokens_remaining <= {LOG_MAX_HMC_TOKENS{1'b0}};`
223			`status_general_rx_tokens_remaining <= {LOG_MAX_RX_TOKENS{1'b0}};`
224			`status_general_lane_polarity_reversed <= {NUM_LANES{1'b0}};`
225			`end`
226			`else`
227			`endif
228			`begin`
229			`status_general_link_up <= status_general_link_up_next;`
230			`status_general_link_training<= status_general_link_training_next;`
231			`status_general_sleep_mode <= status_general_sleep_mode_next;`
232			`status_general_FERR_N <= status_general_FERR_N_next;`
233			`status_general_lanes_reversed <= status_general_lanes_reversed_next;`
234			`status_general_phy_tx_ready <= status_general_phy_tx_ready_next;`
235			`status_general_phy_rx_ready <= status_general_phy_rx_ready_next;`
236			`status_general_hmc_tokens_remaining <= status_general_hmc_tokens_remaining_next;`
237			`status_general_rx_tokens_remaining <= status_general_rx_tokens_remaining_next;`
238			`status_general_lane_polarity_reversed <= status_general_lane_polarity_reversed_next;`
239			`end`
240
241			`end`
242
243			`//Register: status_init`
244			`ifdef ASYNC_RES
245			always @(posedge clk or negedge res_n) `else
246			always @(posedge clk) `endif
247			`begin`
248			`ifdef RESET_ALL
249			`if(!res_n)`
250			`begin`
251			`status_init_lane_descramblers_locked<= {NUM_LANES{1'b0}};`
252			`status_init_descrambler_part_aligned<= {NUM_LANES{1'b0}};`
253			`status_init_descrambler_aligned <= {NUM_LANES{1'b0}};`
254			`status_init_all_descramblers_aligned<= 1'h0;`
255			`status_init_rx_init_state <= 3'h0;`
256			`status_init_tx_init_state <= 2'h0;`
257			`end`
258			`else`
259			`endif
260			`begin`
261			`status_init_lane_descramblers_locked<= status_init_lane_descramblers_locked_next;`
262			`status_init_descrambler_part_aligned<= status_init_descrambler_part_aligned_next;`
263			`status_init_descrambler_aligned <= status_init_descrambler_aligned_next;`
264			`status_init_all_descramblers_aligned<= status_init_all_descramblers_aligned_next;`
265			`status_init_rx_init_state <= status_init_rx_init_state_next;`
266			`status_init_tx_init_state <= status_init_tx_init_state_next;`
267			`end`
268
269			`end`
270
271			`//Register: control`
272			`ifdef ASYNC_RES
273			always @(posedge clk or negedge res_n) `else
274			always @(posedge clk) `endif
275			`begin`
276
277			`if(!res_n)`
278			`begin`
279			`control_p_rst_n <= 1'h0;`
280			`control_hmc_init_cont_set <= 1'b0;`
281			`control_set_hmc_sleep <= 1'h0;`
282			`control_warm_reset <= 1'h0;`
283			`control_scrambler_disable <= 1'h0;`
284			`control_run_length_enable <= 1'h0;`
285			`control_rx_token_count <= {LOG_MAX_RX_TOKENS{1'b1}};`
286			`control_irtry_received_threshold <= 5'h10;`
287			`control_irtry_to_send <= 5'h18;`
288			`end`
289			`else`
290			`begin`
291
292			`if((address == 2) && write_en)`
293			`begin`
294			`control_p_rst_n <= write_data[0:0];`
295			`end`
296
297			`if((address == 2) && write_en)`
298			`begin`
299			`control_hmc_init_cont_set <= write_data[1:1];`
300			`end`
301
302			`if((address == 2) && write_en)`
303			`begin`
304			`control_set_hmc_sleep <= write_data[2:2];`
305			`end`
306
307			`if((address == 2) && write_en)`
308			`begin`
309			`control_warm_reset <= write_data[3:3];`
310			`end`
311
312			`if((address == 2) && write_en)`
313			`begin`
314			`control_scrambler_disable <= write_data[4:4];`
315			`end`
316
317			`if((address == 2) && write_en)`
318			`begin`
319			`control_run_length_enable <= write_data[5:5];`
320			`end`
321
322			`if((address == 2) && write_en)`
323			`begin`
324			`control_rx_token_count <= write_data[16+LOG_MAX_RX_TOKENS-1:16];`
325			`end`
326
327			`if((address == 2) && write_en)`
328			`begin`
329			`control_irtry_received_threshold <= write_data[36:32];`
330			`end`
331
332			`if((address == 2) && write_en)`
333			`begin`
334			`control_irtry_to_send <= write_data[44:40];`
335			`end`
336
337			`end`
338
339			`end`
340
341			`//Register: sent_p`
342			`ifdef ASYNC_RES
343			always @(posedge clk or negedge res_n) `else
344			always @(posedge clk) `endif
345			`begin`
346			`ifdef RESET_ALL
347			`if(!res_n)`
348			`begin`
349			`sent_p_cnt <= {RF_COUNTER_SIZE{1'b0}};`
350			`end`
351			`else`
352			`endif
353			`begin`
354			`sent_p_cnt <= sent_p_cnt_next;`
355			`end`
356
357			`end`
358
359			`//Register: sent_np`
360			`ifdef ASYNC_RES
361			always @(posedge clk or negedge res_n) `else
362			always @(posedge clk) `endif
363			`begin`
364			`ifdef RESET_ALL
365			`if(!res_n)`
366			`begin`
367			`sent_np_cnt <= {RF_COUNTER_SIZE{1'b0}};`
368			`end`
369			`else`
370			`endif
371			`begin`
372			`sent_np_cnt <= sent_np_cnt_next;`
373			`end`
374
375			`end`
376
377			`//Register: sent_r`
378			`ifdef ASYNC_RES
379			always @(posedge clk or negedge res_n) `else
380			always @(posedge clk) `endif
381			`begin`
382			`ifdef RESET_ALL
383			`if(!res_n)`
384			`begin`
385			`sent_r_cnt <= {RF_COUNTER_SIZE{1'b0}};`
386			`end`
387			`else`
388			`endif
389			`begin`
390			`sent_r_cnt <= sent_r_cnt_next;`
391			`end`
392
393			`end`
394
395			`//Register: poisoned_packets`
396			`ifdef ASYNC_RES
397			always @(posedge clk or negedge res_n) `else
398			always @(posedge clk) `endif
399			`begin`
400			`ifdef RESET_ALL
401			`if(!res_n)`
402			`begin`
403			`poisoned_packets_cnt <= {RF_COUNTER_SIZE{1'b0}};`
404			`end`
405			`else`
406			`endif
407			`begin`
408			`poisoned_packets_cnt <= poisoned_packets_cnt_next;`
409			`end`
410
411			`end`
412
413			`//Register: rcvd_rsp`
414			`ifdef ASYNC_RES
415			always @(posedge clk or negedge res_n) `else
416			always @(posedge clk) `endif
417			`begin`
418			`ifdef RESET_ALL
419			`if(!res_n)`
420			`begin`
421			`rcvd_rsp_cnt <= {RF_COUNTER_SIZE{1'b0}};`
422			`end`
423			`else`
424			`endif
425			`begin`
426			`rcvd_rsp_cnt <= rcvd_rsp_cnt_next;`
427			`end`
428
429			`end`
430
431			`//Register: counter_reset`
432			`ifdef ASYNC_RES
433			always @(posedge clk or negedge res_n) `else
434			always @(posedge clk) `endif
435			`begin`
436
437			`if(!res_n)`
438			`begin`
439			`rreinit <= 1'b0;`
440			`end`
441			`else`
442			`begin`
443
444			`if((address == 8) && write_en)`
445			`begin`
446			`rreinit <= 1'b1;`
447			`end`
448			`else`
449			`begin`
450			`rreinit <= 1'b0;`
451			`end`
452			`end`
453
454			`end`
455
456			`//Address Decoder Software Read:`
457			`ifdef ASYNC_RES
458			always @(posedge clk or negedge res_n) `else
459			always @(posedge clk) `endif
460			`begin`
461
462			`if(!res_n)`
463			`begin`
464			`invalid_address <= 1'b0;`
465			`access_complete <= 1'b0;`
466			`read_data <= {HMC_RF_RWIDTH{1'b0}};`
467			`end`
468			`else`
469			`begin`
470
471			`casex(address)`
472			`4'h0:`
473			`begin`
474			`read_data <= {HMC_RF_RWIDTH{1'b0}};`
475			`read_data[0:0] <= status_general_link_up;`
476			`read_data[1:1] <= status_general_link_training;`
477			`read_data[2:2] <= status_general_sleep_mode;`
478			`read_data[3:3] <= status_general_FERR_N;`
479			`read_data[4:4] <= status_general_lanes_reversed;`
480			`read_data[8:8] <= status_general_phy_tx_ready;`
481			`read_data[9:9] <= status_general_phy_rx_ready;`
482			`read_data[16+LOG_MAX_HMC_TOKENS-1:16] <= status_general_hmc_tokens_remaining;`
483			`read_data[32+LOG_MAX_RX_TOKENS-1:32] <= status_general_rx_tokens_remaining;`
484			`read_data[63:48] <= status_general_lane_polarity_reversed;`
485			`invalid_address <= write_en;`
486			`access_complete <= read_en \|\| write_en;`
487			`end`
488			`4'h1:`
489			`begin`
490			`read_data <= {HMC_RF_RWIDTH{1'b0}};`
491			`read_data[NUM_LANES-1:0] <= status_init_lane_descramblers_locked;`
492			`read_data[16+NUM_LANES-1:16] <= status_init_descrambler_part_aligned;`
493			`read_data[32+NUM_LANES-1:32] <= status_init_descrambler_aligned;`
494			`read_data[48:48] <= status_init_all_descramblers_aligned;`
495			`read_data[51:49] <= status_init_rx_init_state;`
496			`read_data[53:52] <= status_init_tx_init_state;`
497			`invalid_address <= write_en;`
498			`access_complete <= read_en \|\| write_en;`
499			`end`
500			`4'h2:`
501			`begin`
502			`read_data <= {HMC_RF_RWIDTH{1'b0}};`
503			`read_data[0:0] <= control_p_rst_n;`
504			`read_data[1:1] <= control_hmc_init_cont_set;`
505			`read_data[2:2] <= control_set_hmc_sleep;`
506			`read_data[3:3] <= control_warm_reset;`
507			`read_data[4:4] <= control_scrambler_disable;`
508			`read_data[5:5] <= control_run_length_enable;`
509			`read_data[16+LOG_MAX_RX_TOKENS-1:16] <= control_rx_token_count;`
510			`read_data[36:32] <= control_irtry_received_threshold;`
511			`read_data[44:40] <= control_irtry_to_send;`
512			`invalid_address <= 1'b0;`
513			`access_complete <= read_en \|\| write_en;`
514			`end`
515			`4'h3:`
516			`begin`
517			`read_data <= {HMC_RF_RWIDTH{1'b0}};`
518			`read_data[RF_COUNTER_SIZE-1:0] <= sent_p_cnt;`
519			`invalid_address <= write_en;`
520			`access_complete <= read_en \|\| write_en;`
521			`end`
522			`4'h4:`
523			`begin`
524			`read_data <= {HMC_RF_RWIDTH{1'b0}};`
525			`read_data[RF_COUNTER_SIZE-1:0] <= sent_np_cnt;`
526			`invalid_address <= write_en;`
527			`access_complete <= read_en \|\| write_en;`
528			`end`
529			`4'h5:`
530			`begin`
531			`read_data <= {HMC_RF_RWIDTH{1'b0}};`
532			`read_data[RF_COUNTER_SIZE-1:0] <= sent_r_cnt;`
533			`invalid_address <= write_en;`
534			`access_complete <= read_en \|\| write_en;`
535			`end`
536			`4'h6:`
537			`begin`
538			`read_data <= {HMC_RF_RWIDTH{1'b0}};`
539			`read_data[RF_COUNTER_SIZE-1:0] <= poisoned_packets_cnt;`
540			`invalid_address <= write_en;`
541			`access_complete <= read_en \|\| write_en;`
542			`end`
543			`4'h7:`
544			`begin`
545			`read_data <= {HMC_RF_RWIDTH{1'b0}};`
546			`read_data[RF_COUNTER_SIZE-1:0] <= rcvd_rsp_cnt;`
547			`invalid_address <= write_en;`
548			`access_complete <= read_en \|\| write_en;`
549			`end`
550			`4'h8:`
551			`begin`
552			`read_data <= {HMC_RF_RWIDTH{1'b0}};`
553			`invalid_address <= read_en;`
554			`access_complete <= read_en \|\| write_en;`
555			`end`
556			`4'h9:`
557			`begin`
558			`read_data <= {HMC_RF_RWIDTH{1'b0}};`
559			`read_data[47:0] <= tx_link_retries_count;`
560			`invalid_address <= write_en;`
561			`access_complete <= read_en \|\| write_en;`
562			`end`
563			`4'ha:`
564			`begin`
565			`read_data <= {HMC_RF_RWIDTH{1'b0}};`
566			`read_data[47:0] <= errors_on_rx_count;`
567			`invalid_address <= write_en;`
568			`access_complete <= read_en \|\| write_en;`
569			`end`
570			`4'hb:`
571			`begin`
572			`read_data <= {HMC_RF_RWIDTH{1'b0}};`
573			`read_data[47:0] <= run_length_bit_flip_count;`
574			`invalid_address <= write_en;`
575			`access_complete <= read_en \|\| write_en;`
576			`end`
577			`4'hc:`
578			`begin`
579			`read_data <= {HMC_RF_RWIDTH{1'b0}};`
580			`read_data[47:0] <= error_abort_not_cleared_count;`
581			`invalid_address <= write_en;`
582			`access_complete <= read_en \|\| write_en;`
583			`end`
584			`default:`
585			`begin`
586			`read_data <= {HMC_RF_RWIDTH{1'b0}};`
587			`invalid_address <= read_en \|\| write_en;`
588			`access_complete <= read_en \|\| write_en;`
589			`end`
590
591			`endcase`
592			`end`
593
594			`end`
595
596			`endmodule`
597
598			`default_nettype wire