URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [clock_module_asic.s43] - Blame information for rev 134

Go to most recent revision | Details | Compare with Previous | View Log


/*===========================================================================*/
/* Copyright (C) 2001 Authors                                                */
/*                                                                           */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any   */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer.                                                               */
/*                                                                           */
/* This source file is free software; you can redistribute it and/or modify  */
/* it under the terms of the GNU Lesser General Public License as published  */
/* by the Free Software Foundation; either version 2.1 of the License, or    */
/* (at your option) any later version.                                       */
/*                                                                           */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
/* License for more details.                                                 */
/*                                                                           */
/* You should have received a copy of the GNU Lesser General Public License  */
/* along with this source; if not, write to the Free Software Foundation,    */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/*                                                                           */
/*===========================================================================*/
/*                               CLOCK MODULE                                */
/*---------------------------------------------------------------------------*/
/* Test the clock module:                                                    */
/*                        - Check the ACLK and SMCLK clock generation.       */
/*                                                                           */
/* Author(s):                                                                */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*                                                                           */
/*---------------------------------------------------------------------------*/
/* $Rev: 19 $                                                                */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $          */
/*===========================================================================*/
 
.global main
 
.set   DMEM_BASE, (__data_start     )
.set   DMEM_200,  (__data_start+0x00)
.set   DMEM_250,  (__data_start+0x50)
 
.set   BCSCTL1, 0x0057
.set   BCSCTL2, 0x0058
 
.set   WDTCTL,  0x0120
 
 
WAIT_FUNC:
        dec r14
        jnz WAIT_FUNC
        ret
 
main:
        mov #DMEM_250, r1       ; # Initialize stack pointer
        mov   #0x0000, &DMEM_200
        mov   #0x0000, r15
 
 
       /* --------------                MCLK GENERATION  - DCO_CLK INPUT   ----------------- */
 
        mov.b  #0x00, &BCSCTL2  ; # Div /1
        mov    #0x0001, r15
        mov    #0x0130, r14
        call   #WAIT_FUNC
 
        mov.b  #0x10, &BCSCTL2  ; # Div /2
        mov    #0x0002, r15
        mov    #0x0130, r14
        call   #WAIT_FUNC
 
        mov.b  #0x20, &BCSCTL2  ; # Div /4
        mov    #0x0003, r15
        mov    #0x0130, r14
        call   #WAIT_FUNC
 
        mov.b  #0x30, &BCSCTL2  ; # Div /8
        mov    #0x0004, r15
        mov    #0x0130, r14
        call   #WAIT_FUNC
 
        mov.b  #0x00, &BCSCTL2  ; # Div /1
        mov    #0x1000, r15
 
 
       /* --------------                MCLK GENERATION  - LFXT_CLK INPUT ----------------- */
 
#       mov.b  #0x80, &BCSCTL2  ; # Div /1
#       mov    #0x1001, r15
#       mov    #0x0130, r14
#        call   #WAIT_FUNC
 
#       mov.b  #0x90, &BCSCTL2  ; # Div /2
#       mov    #0x1002, r15
#       mov    #0x0130, r14
#        call   #WAIT_FUNC
 
#       mov.b  #0xA0, &BCSCTL2  ; # Div /4
#       mov    #0x1003, r15
#       mov    #0x0130, r14
#        call   #WAIT_FUNC
 
#       mov.b  #0xB0, &BCSCTL2  ; # Div /8
#       mov    #0x1004, r15
#       mov    #0x0130, r14
#        call   #WAIT_FUNC
 
        mov.b  #0x00, &BCSCTL2  ; # Div /1
        mov    #0x2000, r15
 
 
       /* --------------                ACLK GENERATION             ----------------- */
 
        mov.b  #0x00, &BCSCTL1  ; # Div /1
        mov    #0x2001, r15
        mov    #0x0230, r14
        call   #WAIT_FUNC
 
        mov.b  #0x10, &BCSCTL1  ; # Div /2
        mov    #0x2002, r15
        mov    #0x0230, r14
        call   #WAIT_FUNC
 
        mov.b  #0x20, &BCSCTL1  ; # Div /4
        mov    #0x2003, r15
        mov    #0x0230, r14
        call   #WAIT_FUNC
 
        mov.b  #0x30, &BCSCTL1  ; # Div /8
        mov    #0x2004, r15
        mov    #0x0230, r14
        call   #WAIT_FUNC
 
        mov.b  #0x00, &BCSCTL1  ; # Div /1
        mov    #0x3000, r15
 
 
       /* --------------      SMCLK GENERATION - DCO_CLK INPUT     ----------------- */
 
        mov.b  #0x00, &BCSCTL2  ; # Div /1
        mov    #0x3001, r15
        mov    #0x0130, r14
        call   #WAIT_FUNC
 
        mov.b  #0x02, &BCSCTL2  ; # Div /2
        mov    #0x3002, r15
        mov    #0x0130, r14
        call   #WAIT_FUNC
 
        mov.b  #0x04, &BCSCTL2  ; # Div /4
        mov    #0x3003, r15
        mov    #0x0130, r14
        call   #WAIT_FUNC
 
        mov.b  #0x06, &BCSCTL2  ; # Div /8
        mov    #0x3004, r15
        mov    #0x0130, r14
        call   #WAIT_FUNC
 
        mov.b  #0x00, &BCSCTL2  ; # Div /1
        mov    #0x4000, r15
 
 
       /* --------------      SMCLK GENERATION - LFXT_CLK INPUT    ----------------- */
 
#       mov.b  #0x08, &BCSCTL2  ; # Div /1
#       mov    #0x4001, r15
#       mov    #0x0130, r14
#        call   #WAIT_FUNC
 
#       mov.b  #0x0A, &BCSCTL2  ; # Div /2
#       mov    #0x4002, r15
#       mov    #0x0130, r14
#        call   #WAIT_FUNC
 
#       mov.b  #0x0C, &BCSCTL2  ; # Div /4
#       mov    #0x4003, r15
#       mov    #0x0130, r14
#        call   #WAIT_FUNC
 
#       mov.b  #0x0E, &BCSCTL2  ; # Div /8
#       mov    #0x4004, r15
#       mov    #0x0130, r14
#        call   #WAIT_FUNC
 
        mov.b  #0x00, &BCSCTL2  ; # Div /1
        mov    #0x5000, r15
 
 
        /* --------------  CPU ENABLE - CPU_EN INPUT / DBG ENABLE - DBG_EN INPUT  ----------------- */
 
        mov    #0x0800, r14     ; CPU ENABLE
        mov    #0x5001, r15
        call   #WAIT_FUNC
 
        mov    #0x0800, r14     ; DBG ENABLE
        mov    #0x5002, r15
        call   #WAIT_FUNC
 
        mov    #0x6000, r15
 
 
        /* --------------      RD/WR ACCESS TO REGISTERS     ----------------- */
 
        mov.b     #0x00, &BCSCTL1
        mov.b     #0x00, &BCSCTL2
        mov.b  &BCSCTL1, r4
        mov.b  &BCSCTL2, r5
 
        mov.b     #0xff, &BCSCTL1
        mov.b  &BCSCTL1, r6
        mov.b  &BCSCTL2, r7
 
        mov.b     #0x00, &BCSCTL1
        mov.b  &BCSCTL1, r8
        mov.b  &BCSCTL2, r9
 
        mov.b     #0xff, &BCSCTL2
        mov.b  &BCSCTL1, r10
        mov.b  &BCSCTL2, r11
 
        mov.b     #0x00, &BCSCTL2
        mov.b  &BCSCTL1, r12
        mov.b  &BCSCTL2, r13
 
 
        mov     #0x7000, r15
        mov     #0x0010, r14
        call    #WAIT_FUNC
 
 
        /* ----------------------         END OF TEST        --------------- */
end_of_test:
        nop
        br #0xffff
 
 
        /* ----------------------         INTERRUPT VECTORS  --------------- */
 
.section .vectors, "a"
.word end_of_test        ; Interrupt  0 (lowest priority)    
.word end_of_test        ; Interrupt  1                      
.word end_of_test        ; Interrupt  2                      
.word end_of_test        ; Interrupt  3                      
.word end_of_test        ; Interrupt  4                      
.word end_of_test        ; Interrupt  5                      
.word end_of_test        ; Interrupt  6                      
.word end_of_test        ; Interrupt  7                      
.word end_of_test        ; Interrupt  8                      
.word end_of_test        ; Interrupt  9                      
.word end_of_test        ; Interrupt 10                      Watchdog timer
.word end_of_test        ; Interrupt 11                      
.word end_of_test        ; Interrupt 12                      
.word end_of_test        ; Interrupt 13                      
.word end_of_test        ; Interrupt 14                      NMI
.word main               ; Interrupt 15 (highest priority)   RESET

Browse

Tools

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [clock_module_asic.s43] - Blame information for rev 134

Line No.	Rev	Author	Line
1	134	olivier.gi	`/===========================================================================/`
2			`/* Copyright (C) 2001 Authors */`
3			`/* */`
4			`/* This source file may be used and distributed without restriction provided */`
5			`/* that this copyright statement is not removed from the file and that any */`
6			`/* derivative work contains the original copyright notice and the associated */`
7			`/* disclaimer. */`
8			`/* */`
9			`/* This source file is free software; you can redistribute it and/or modify */`
10			`/* it under the terms of the GNU Lesser General Public License as published */`
11			`/* by the Free Software Foundation; either version 2.1 of the License, or */`
12			`/* (at your option) any later version. */`
13			`/* */`
14			`/* This source is distributed in the hope that it will be useful, but WITHOUT*/`
15			`/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */`
16			`/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */`
17			`/* License for more details. */`
18			`/* */`
19			`/* You should have received a copy of the GNU Lesser General Public License */`
20			`/* along with this source; if not, write to the Free Software Foundation, */`
21			`/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */`
22			`/* */`
23			`/===========================================================================/`
24			`/* CLOCK MODULE */`
25			`/---------------------------------------------------------------------------/`
26			`/* Test the clock module: */`
27			`/* - Check the ACLK and SMCLK clock generation. */`
28			`/* */`
29			`/* Author(s): */`
30			`/* - Olivier Girard, olgirard@gmail.com */`
31			`/* */`
32			`/---------------------------------------------------------------------------/`
33			`/* $Rev: 19 $ */`
34			`/* $LastChangedBy: olivier.girard $ */`
35			`/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */`
36			`/===========================================================================/`
37
38			`.global main`
39
40			`.set DMEM_BASE, (__data_start )`
41			`.set DMEM_200, (__data_start+0x00)`
42			`.set DMEM_250, (__data_start+0x50)`
43
44			`.set BCSCTL1, 0x0057`
45			`.set BCSCTL2, 0x0058`
46
47			`.set WDTCTL, 0x0120`
48
49
50			`WAIT_FUNC:`
51			`dec r14`
52			`jnz WAIT_FUNC`
53			`ret`
54
55			`main:`
56			`mov #DMEM_250, r1 ; # Initialize stack pointer`
57			`mov #0x0000, &DMEM_200`
58			`mov #0x0000, r15`
59
60
61			`/* -------------- MCLK GENERATION - DCO_CLK INPUT ----------------- */`
62
63			`mov.b #0x00, &BCSCTL2 ; # Div /1`
64			`mov #0x0001, r15`
65			`mov #0x0130, r14`
66			`call #WAIT_FUNC`
67
68			`mov.b #0x10, &BCSCTL2 ; # Div /2`
69			`mov #0x0002, r15`
70			`mov #0x0130, r14`
71			`call #WAIT_FUNC`
72
73			`mov.b #0x20, &BCSCTL2 ; # Div /4`
74			`mov #0x0003, r15`
75			`mov #0x0130, r14`
76			`call #WAIT_FUNC`
77
78			`mov.b #0x30, &BCSCTL2 ; # Div /8`
79			`mov #0x0004, r15`
80			`mov #0x0130, r14`
81			`call #WAIT_FUNC`
82
83			`mov.b #0x00, &BCSCTL2 ; # Div /1`
84			`mov #0x1000, r15`
85
86
87			`/* -------------- MCLK GENERATION - LFXT_CLK INPUT ----------------- */`
88
89			`# mov.b #0x80, &BCSCTL2 ; # Div /1`
90			`# mov #0x1001, r15`
91			`# mov #0x0130, r14`
92			`# call #WAIT_FUNC`
93
94			`# mov.b #0x90, &BCSCTL2 ; # Div /2`
95			`# mov #0x1002, r15`
96			`# mov #0x0130, r14`
97			`# call #WAIT_FUNC`
98
99			`# mov.b #0xA0, &BCSCTL2 ; # Div /4`
100			`# mov #0x1003, r15`
101			`# mov #0x0130, r14`
102			`# call #WAIT_FUNC`
103
104			`# mov.b #0xB0, &BCSCTL2 ; # Div /8`
105			`# mov #0x1004, r15`
106			`# mov #0x0130, r14`
107			`# call #WAIT_FUNC`
108
109			`mov.b #0x00, &BCSCTL2 ; # Div /1`
110			`mov #0x2000, r15`
111
112
113			`/* -------------- ACLK GENERATION ----------------- */`
114
115			`mov.b #0x00, &BCSCTL1 ; # Div /1`
116			`mov #0x2001, r15`
117			`mov #0x0230, r14`
118			`call #WAIT_FUNC`
119
120			`mov.b #0x10, &BCSCTL1 ; # Div /2`
121			`mov #0x2002, r15`
122			`mov #0x0230, r14`
123			`call #WAIT_FUNC`
124
125			`mov.b #0x20, &BCSCTL1 ; # Div /4`
126			`mov #0x2003, r15`
127			`mov #0x0230, r14`
128			`call #WAIT_FUNC`
129
130			`mov.b #0x30, &BCSCTL1 ; # Div /8`
131			`mov #0x2004, r15`
132			`mov #0x0230, r14`
133			`call #WAIT_FUNC`
134
135			`mov.b #0x00, &BCSCTL1 ; # Div /1`
136			`mov #0x3000, r15`
137
138
139			`/* -------------- SMCLK GENERATION - DCO_CLK INPUT ----------------- */`
140
141			`mov.b #0x00, &BCSCTL2 ; # Div /1`
142			`mov #0x3001, r15`
143			`mov #0x0130, r14`
144			`call #WAIT_FUNC`
145
146			`mov.b #0x02, &BCSCTL2 ; # Div /2`
147			`mov #0x3002, r15`
148			`mov #0x0130, r14`
149			`call #WAIT_FUNC`
150
151			`mov.b #0x04, &BCSCTL2 ; # Div /4`
152			`mov #0x3003, r15`
153			`mov #0x0130, r14`
154			`call #WAIT_FUNC`
155
156			`mov.b #0x06, &BCSCTL2 ; # Div /8`
157			`mov #0x3004, r15`
158			`mov #0x0130, r14`
159			`call #WAIT_FUNC`
160
161			`mov.b #0x00, &BCSCTL2 ; # Div /1`
162			`mov #0x4000, r15`
163
164
165			`/* -------------- SMCLK GENERATION - LFXT_CLK INPUT ----------------- */`
166
167			`# mov.b #0x08, &BCSCTL2 ; # Div /1`
168			`# mov #0x4001, r15`
169			`# mov #0x0130, r14`
170			`# call #WAIT_FUNC`
171
172			`# mov.b #0x0A, &BCSCTL2 ; # Div /2`
173			`# mov #0x4002, r15`
174			`# mov #0x0130, r14`
175			`# call #WAIT_FUNC`
176
177			`# mov.b #0x0C, &BCSCTL2 ; # Div /4`
178			`# mov #0x4003, r15`
179			`# mov #0x0130, r14`
180			`# call #WAIT_FUNC`
181
182			`# mov.b #0x0E, &BCSCTL2 ; # Div /8`
183			`# mov #0x4004, r15`
184			`# mov #0x0130, r14`
185			`# call #WAIT_FUNC`
186
187			`mov.b #0x00, &BCSCTL2 ; # Div /1`
188			`mov #0x5000, r15`
189
190
191			`/* -------------- CPU ENABLE - CPU_EN INPUT / DBG ENABLE - DBG_EN INPUT ----------------- */`
192
193			`mov #0x0800, r14 ; CPU ENABLE`
194			`mov #0x5001, r15`
195			`call #WAIT_FUNC`
196
197			`mov #0x0800, r14 ; DBG ENABLE`
198			`mov #0x5002, r15`
199			`call #WAIT_FUNC`
200
201			`mov #0x6000, r15`
202
203
204			`/* -------------- RD/WR ACCESS TO REGISTERS ----------------- */`
205
206			`mov.b #0x00, &BCSCTL1`
207			`mov.b #0x00, &BCSCTL2`
208			`mov.b &BCSCTL1, r4`
209			`mov.b &BCSCTL2, r5`
210
211			`mov.b #0xff, &BCSCTL1`
212			`mov.b &BCSCTL1, r6`
213			`mov.b &BCSCTL2, r7`
214
215			`mov.b #0x00, &BCSCTL1`
216			`mov.b &BCSCTL1, r8`
217			`mov.b &BCSCTL2, r9`
218
219			`mov.b #0xff, &BCSCTL2`
220			`mov.b &BCSCTL1, r10`
221			`mov.b &BCSCTL2, r11`
222
223			`mov.b #0x00, &BCSCTL2`
224			`mov.b &BCSCTL1, r12`
225			`mov.b &BCSCTL2, r13`
226
227
228			`mov #0x7000, r15`
229			`mov #0x0010, r14`
230			`call #WAIT_FUNC`
231
232
233			`/* ---------------------- END OF TEST --------------- */`
234			`end_of_test:`
235			`nop`
236			`br #0xffff`
237
238
239			`/* ---------------------- INTERRUPT VECTORS --------------- */`
240
241			`.section .vectors, "a"`
242			`.word end_of_test ; Interrupt 0 (lowest priority)`
243			`.word end_of_test ; Interrupt 1`
244			`.word end_of_test ; Interrupt 2`
245			`.word end_of_test ; Interrupt 3`
246			`.word end_of_test ; Interrupt 4`
247			`.word end_of_test ; Interrupt 5`
248			`.word end_of_test ; Interrupt 6`
249			`.word end_of_test ; Interrupt 7`
250			`.word end_of_test ; Interrupt 8`
251			`.word end_of_test ; Interrupt 9`
252			`.word end_of_test ; Interrupt 10 Watchdog timer`
253			`.word end_of_test ; Interrupt 11`
254			`.word end_of_test ; Interrupt 12`
255			`.word end_of_test ; Interrupt 13`
256			`.word end_of_test ; Interrupt 14 NMI`
257			`.word main ; Interrupt 15 (highest priority) RESET`