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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [dbg_i2c_halt_irq.s43] - Blame information for rev 154

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1 154 olivier.gi
/*===========================================================================*/
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/* Copyright (C) 2001 Authors                                                */
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/*                                                                           */
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/* This source file may be used and distributed without restriction provided */
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/* that this copyright statement is not removed from the file and that any   */
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/* derivative work contains the original copyright notice and the associated */
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/* disclaimer.                                                               */
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/*                                                                           */
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/* This source file is free software; you can redistribute it and/or modify  */
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/* it under the terms of the GNU Lesser General Public License as published  */
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/* by the Free Software Foundation; either version 2.1 of the License, or    */
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/* (at your option) any later version.                                       */
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/*                                                                           */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
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/* License for more details.                                                 */
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/*                                                                           */
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/* You should have received a copy of the GNU Lesser General Public License  */
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/* along with this source; if not, write to the Free Software Foundation,    */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
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/*                                                                           */
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/*===========================================================================*/
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/*                        SERIAL DEBUG INTERFACE                             */
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/*---------------------------------------------------------------------------*/
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/* Test the serial debug interface:                                          */
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/*                           - Interrupts when going out of halt mode.       */
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/*                                                                           */
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/* Author(s):                                                                */
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/*             - Olivier Girard,    olgirard@gmail.com                       */
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/*                                                                           */
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/*---------------------------------------------------------------------------*/
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/* $Rev: 19 $                                                                */
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/* $LastChangedBy: olivier.girard $                                          */
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/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $          */
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/*===========================================================================*/
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.include "pmem_defs.asm"
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.global main
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main:
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        ; Disable interrupts
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        dint
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        mov.b #0x00, &P1IE
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        /* -------------- PORT 1: TEST INTERRUPT VECTOR  --------------- */
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        mov   #DMEM_250, r1     ; Initialize stack
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        mov.b   #0x0001, &P1IE  ; Enable GPIO interrupt
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        eint                    ; Enable Global interrupts
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        mov     #0x0000, r13;
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        mov     #0x0000, r14;
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        mov   #DMEM_200, r15;
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infinite_loop:
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        inc     r13
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        bit     #0x0002, &P1IN
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        jz      infinite_loop
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        /* ----------------------         END OF TEST        --------------- */
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end_of_test:
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        nop
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        br #0xffff
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        /* ----------------------      INTERRUPT ROUTINES    --------------- */
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PORT1_VECTOR:
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        mov.b &P1IFG,   0(r15)
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        mov.b  #0x00,   &P1IFG
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        mov    #0xaaaa, r14;
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        reti
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        /* ----------------------         INTERRUPT VECTORS  --------------- */
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.section .vectors, "a"
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.word end_of_test  ; Interrupt  0 (lowest priority)    
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.word end_of_test  ; Interrupt  1                      
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.word PORT1_VECTOR ; Interrupt  2                      
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.word end_of_test  ; Interrupt  3                      
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.word end_of_test  ; Interrupt  4                      
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.word end_of_test  ; Interrupt  5                      
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.word end_of_test  ; Interrupt  6                      
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.word end_of_test  ; Interrupt  7                      
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.word end_of_test  ; Interrupt  8                      
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.word end_of_test  ; Interrupt  9                      
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.word end_of_test  ; Interrupt 10                      Watchdog timer
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.word end_of_test  ; Interrupt 11                      
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.word end_of_test  ; Interrupt 12                      
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.word end_of_test  ; Interrupt 13                      
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.word end_of_test  ; Interrupt 14                      NMI
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.word main         ; Interrupt 15 (highest priority)   RESET

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