OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [dbg_uart.v] - Blame information for rev 106

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 olivier.gi 
/*===========================================================================*/
2 
/* Copyright (C) 2001 Authors                                                */
3 
/*                                                                           */
4 
/* This source file may be used and distributed without restriction provided */
5 
/* that this copyright statement is not removed from the file and that any   */
6 
/* derivative work contains the original copyright notice and the associated */
7 
/* disclaimer.                                                               */
8 
/*                                                                           */
9 
/* This source file is free software; you can redistribute it and/or modify  */
10 
/* it under the terms of the GNU Lesser General Public License as published  */
11 
/* by the Free Software Foundation; either version 2.1 of the License, or    */
12 
/* (at your option) any later version.                                       */
13 
/*                                                                           */
14 
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
15 
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
16 
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
17 
/* License for more details.                                                 */
18 
/*                                                                           */
19 
/* You should have received a copy of the GNU Lesser General Public License  */
20 
/* along with this source; if not, write to the Free Software Foundation,    */
21 
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
22 
/*                                                                           */
23 
/*===========================================================================*/
24 
/*                            DEBUG INTERFACE:  UART                         */
25 
/*---------------------------------------------------------------------------*/
26 
/* Test the UART debug interface:                                            */
27 
/*                        - Check RD/WR access to debugg registers.          */
28 
/*                        - Check RD Bursts.                                 */
29 
/*                        - Check WR Bursts.                                 */
30 18 olivier.gi 
/*                                                                           */
31 
/* Author(s):                                                                */
32 
/*             - Olivier Girard,    olgirard@gmail.com                       */
33 
/*                                                                           */
34 
/*---------------------------------------------------------------------------*/
35 19 olivier.gi 
/* $Rev: 106 $                                                                */
36 
/* $LastChangedBy: olivier.girard $                                          */
37 
/* $LastChangedDate: 2011-03-25 23:01:03 +0100 (Fri, 25 Mar 2011) $          */
38 2 olivier.gi 
/*===========================================================================*/
39 
 
40 
`define LONG_TIMEOUT
41 
 
42 74 olivier.gi 
reg [15:0] dbg_id_pmem;
43 
reg [15:0] dbg_id_dmem;
44 2 olivier.gi 
reg [31:0] dbg_id;
45 
 
46 
initial
47 
   begin
48 
      $display(" ===============================================");
49 
      $display("|                 START SIMULATION              |");
50 
      $display(" ===============================================");
51 106 olivier.gi 
      #1 dbg_en = 1;
52 2 olivier.gi 
      repeat(30) @(posedge mclk);
53 
      stimulus_done = 0;
54 
 
55 
      // SEND UART SYNCHRONIZATION FRAME
56 
      dbg_uart_tx(DBG_SYNC);
57 
 
58 106 olivier.gi 
   `ifdef DBG_RST_BRK_EN
59 
      dbg_uart_wr(CPU_CTL,  16'h0002);  // RUN
60 
   `endif
61 
 
62 2 olivier.gi 
      // TEST CPU REGISTERS
63 
      //--------------------------------------------------------
64 74 olivier.gi 
      dbg_id_pmem = `PMEM_SIZE;
65 
      dbg_id_dmem = `DMEM_SIZE;
66 
      dbg_id      = {dbg_id_pmem, dbg_id_dmem};
67 2 olivier.gi 
 
68 
      dbg_uart_wr(CPU_ID_LO  ,  16'hffff);
69 
      dbg_uart_rd(CPU_ID_LO);
70 
      if (dbg_uart_buf !== dbg_id[15:0])  tb_error("====== CPU_ID_LO uncorrect =====");
71 
      dbg_uart_wr(CPU_ID_LO  ,  16'h0000);
72 
      dbg_uart_rd(CPU_ID_LO);
73 
      if (dbg_uart_buf !== dbg_id[15:0])  tb_error("====== CPU_ID_LO uncorrect =====");
74 
 
75 
      dbg_uart_wr(CPU_ID_HI  ,  16'hffff);
76 
      dbg_uart_rd(CPU_ID_HI);
77 
      if (dbg_uart_buf !== dbg_id[31:16]) tb_error("====== CPU_ID_HI uncorrect =====");
78 
      dbg_uart_wr(CPU_ID_HI  ,  16'h0000);
79 
      dbg_uart_rd(CPU_ID_HI);
80 
      if (dbg_uart_buf !== dbg_id[31:16]) tb_error("====== CPU_ID_HI uncorrect =====");
81 
 
82 
      dbg_uart_wr(CPU_STAT   ,  16'hffff);
83 
      dbg_uart_rd(CPU_STAT);
84 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== CPU_STAT uncorrect =====");
85 
      dbg_uart_wr(CPU_STAT   ,  16'h0000);
86 
      dbg_uart_rd(CPU_STAT);
87 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== CPU_STAT uncorrect =====");
88 
 
89 
      dbg_uart_wr(CPU_CTL    ,  16'hffff);
90 
      dbg_uart_rd(CPU_CTL);
91 
      if (dbg_uart_buf !== 16'h0078)      tb_error("====== CPU_CTL uncorrect =====");
92 
      dbg_uart_wr(CPU_CTL    ,  16'h0000);
93 
      dbg_uart_rd(CPU_CTL);
94 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== CPU_CTL uncorrect =====");
95 
 
96 
 
97 
      // TEST MEMORY CONTROL REGISTERS
98 
      //--------------------------------------------------------
99 
 
100 
      dbg_uart_wr(MEM_CTL    ,  16'hfffe);
101 
      dbg_uart_rd(MEM_CTL);
102 
      if (dbg_uart_buf !== 16'h000E)      tb_error("====== MEM_CTL uncorrect =====");
103 
      dbg_uart_wr(MEM_CTL    ,  16'h0000);
104 
      dbg_uart_rd(MEM_CTL);
105 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== MEM_CTL uncorrect =====");
106 
 
107 
      dbg_uart_wr(MEM_ADDR   ,  16'hffff);
108 
      dbg_uart_rd(MEM_ADDR);
109 
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== MEM_ADDR uncorrect =====");
110 
      dbg_uart_wr(MEM_ADDR   ,  16'h0000);
111 
      dbg_uart_rd(MEM_ADDR);
112 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== MEM_ADDR uncorrect =====");
113 
 
114 
      dbg_uart_wr(MEM_DATA   ,  16'hffff);
115 
      dbg_uart_rd(MEM_DATA);
116 
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== MEM_DATA uncorrect =====");
117 
      dbg_uart_wr(MEM_DATA   ,  16'h0000);
118 
      dbg_uart_rd(MEM_DATA);
119 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== MEM_DATA uncorrect =====");
120 
 
121 
      dbg_uart_wr(MEM_CNT    ,  16'hffff);
122 
      dbg_uart_rd(MEM_CNT);
123 
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== MEM_CNT uncorrect =====");
124 
      dbg_uart_wr(MEM_CNT    ,  16'h0000);
125 
      dbg_uart_rd(MEM_CNT);
126 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== MEM_CNT uncorrect =====");
127 
 
128 
 
129 
      // TEST HARDWARE BREAKPOINT 0 REGISTERS
130 
      //--------------------------------------------------------
131 
 
132 
      dbg_uart_wr(BRK0_CTL   ,  16'hffff);
133 
      dbg_uart_rd(BRK0_CTL);
134 58 olivier.gi 
      if (`HWBRK_RANGE)
135 
        begin
136 
           if (dbg_uart_buf !== 16'h001F)      tb_error("====== BRK0_CTL uncorrect =====");
137 
        end
138 
      else
139 
        begin
140 
           if (dbg_uart_buf !== 16'h000F)      tb_error("====== BRK0_CTL uncorrect =====");
141 
        end
142 2 olivier.gi 
      dbg_uart_wr(BRK0_CTL   ,  16'h0000);
143 
      dbg_uart_rd(BRK0_CTL);
144 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK0_CTL uncorrect =====");
145 
 
146 
      dbg_uart_wr(BRK0_STAT  ,  16'hffff);
147 
      dbg_uart_rd(BRK0_STAT);
148 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK0_STAT uncorrect =====");
149 
      dbg_uart_wr(BRK0_STAT  ,  16'h0000);
150 
      dbg_uart_rd(BRK0_STAT);
151 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK0_STAT uncorrect =====");
152 
 
153 
      dbg_uart_wr(BRK0_ADDR0 ,  16'hffff);
154 
      dbg_uart_rd(BRK0_ADDR0);
155 
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== BRK0_ADDR0 uncorrect =====");
156 
      dbg_uart_wr(BRK0_ADDR0 ,  16'h0000);
157 
      dbg_uart_rd(BRK0_ADDR0);
158 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK0_ADDR0 uncorrect =====");
159 
 
160 
      dbg_uart_wr(BRK0_ADDR1 ,  16'hffff);
161 
      dbg_uart_rd(BRK0_ADDR1);
162 
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== BRK0_ADDR1 uncorrect =====");
163 
      dbg_uart_wr(BRK0_ADDR1 ,  16'h0000);
164 
      dbg_uart_rd(BRK0_ADDR1);
165 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK0_ADDR1 uncorrect =====");
166 
 
167 
 
168 
      // TEST HARDWARE BREAKPOINT 1 REGISTERS
169 
      //--------------------------------------------------------
170 
 
171 
      dbg_uart_wr(BRK1_CTL   ,  16'hffff);
172 
      dbg_uart_rd(BRK1_CTL);
173 58 olivier.gi 
      if (`HWBRK_RANGE)
174 
        begin
175 
           if (dbg_uart_buf !== 16'h001F)      tb_error("====== BRK1_CTL uncorrect =====");
176 
        end
177 
      else
178 
        begin
179 
           if (dbg_uart_buf !== 16'h000F)      tb_error("====== BRK1_CTL uncorrect =====");
180 
        end
181 2 olivier.gi 
      dbg_uart_wr(BRK1_CTL   ,  16'h0000);
182 
      dbg_uart_rd(BRK1_CTL);
183 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK1_CTL uncorrect =====");
184 
 
185 
      dbg_uart_wr(BRK1_STAT  ,  16'hffff);
186 
      dbg_uart_rd(BRK1_STAT);
187 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK1_STAT uncorrect =====");
188 
      dbg_uart_wr(BRK1_STAT  ,  16'h0000);
189 
      dbg_uart_rd(BRK1_STAT);
190 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK1_STAT uncorrect =====");
191 
 
192 
      dbg_uart_wr(BRK1_ADDR0 ,  16'hffff);
193 
      dbg_uart_rd(BRK1_ADDR0);
194 
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== BRK1_ADDR0 uncorrect =====");
195 
      dbg_uart_wr(BRK1_ADDR0 ,  16'h0000);
196 
      dbg_uart_rd(BRK1_ADDR0);
197 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK1_ADDR0 uncorrect =====");
198 
 
199 
      dbg_uart_wr(BRK1_ADDR1 ,  16'hffff);
200 
      dbg_uart_rd(BRK1_ADDR1);
201 
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== BRK1_ADDR1 uncorrect =====");
202 
      dbg_uart_wr(BRK1_ADDR1 ,  16'h0000);
203 
      dbg_uart_rd(BRK1_ADDR1);
204 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK1_ADDR1 uncorrect =====");
205 
 
206 
 
207 
      // TEST HARDWARE BREAKPOINT 2 REGISTERS
208 
      //--------------------------------------------------------
209 
 
210 
      dbg_uart_wr(BRK2_CTL   ,  16'hffff);
211 
      dbg_uart_rd(BRK2_CTL);
212 58 olivier.gi 
      if (`HWBRK_RANGE)
213 
        begin
214 
           if (dbg_uart_buf !== 16'h001F)      tb_error("====== BRK2_CTL uncorrect =====");
215 
        end
216 
      else
217 
        begin
218 
           if (dbg_uart_buf !== 16'h000F)      tb_error("====== BRK2_CTL uncorrect =====");
219 
        end
220 2 olivier.gi 
      dbg_uart_wr(BRK2_CTL   ,  16'h0000);
221 
      dbg_uart_rd(BRK2_CTL);
222 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK2_CTL uncorrect =====");
223 
 
224 
      dbg_uart_wr(BRK2_STAT  ,  16'hffff);
225 
      dbg_uart_rd(BRK2_STAT);
226 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK2_STAT uncorrect =====");
227 
      dbg_uart_wr(BRK2_STAT  ,  16'h0000);
228 
      dbg_uart_rd(BRK2_STAT);
229 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK2_STAT uncorrect =====");
230 
 
231 
      dbg_uart_wr(BRK2_ADDR0 ,  16'hffff);
232 
      dbg_uart_rd(BRK2_ADDR0);
233 
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== BRK2_ADDR0 uncorrect =====");
234 
      dbg_uart_wr(BRK2_ADDR0 ,  16'h0000);
235 
      dbg_uart_rd(BRK2_ADDR0);
236 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK2_ADDR0 uncorrect =====");
237 
 
238 
      dbg_uart_wr(BRK2_ADDR1 ,  16'hffff);
239 
      dbg_uart_rd(BRK2_ADDR1);
240 
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== BRK2_ADDR1 uncorrect =====");
241 
      dbg_uart_wr(BRK2_ADDR1 ,  16'h0000);
242 
      dbg_uart_rd(BRK2_ADDR1);
243 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK2_ADDR1 uncorrect =====");
244 
 
245 
 
246 
      // TEST HARDWARE BREAKPOINT 3 REGISTERS
247 
      //--------------------------------------------------------
248 
 
249 
      dbg_uart_wr(BRK3_CTL   ,  16'hffff);
250 
      dbg_uart_rd(BRK3_CTL);
251 58 olivier.gi 
      if (`HWBRK_RANGE)
252 
        begin
253 
           if (dbg_uart_buf !== 16'h001F)      tb_error("====== BRK3_CTL uncorrect =====");
254 
        end
255 
      else
256 
        begin
257 
           if (dbg_uart_buf !== 16'h000F)      tb_error("====== BRK3_CTL uncorrect =====");
258 
        end
259 2 olivier.gi 
      dbg_uart_wr(BRK3_CTL   ,  16'h0000);
260 
      dbg_uart_rd(BRK3_CTL);
261 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK3_CTL uncorrect =====");
262 
 
263 
      dbg_uart_wr(BRK3_STAT  ,  16'hffff);
264 
      dbg_uart_rd(BRK3_STAT);
265 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK3_STAT uncorrect =====");
266 
      dbg_uart_wr(BRK3_STAT  ,  16'h0000);
267 
      dbg_uart_rd(BRK3_STAT);
268 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK3_STAT uncorrect =====");
269 
 
270 
      dbg_uart_wr(BRK3_ADDR0 ,  16'hffff);
271 
      dbg_uart_rd(BRK3_ADDR0);
272 
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== BRK3_ADDR0 uncorrect =====");
273 
      dbg_uart_wr(BRK3_ADDR0 ,  16'h0000);
274 
      dbg_uart_rd(BRK3_ADDR0);
275 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK3_ADDR0 uncorrect =====");
276 
 
277 
      dbg_uart_wr(BRK3_ADDR1 ,  16'hffff);
278 
      dbg_uart_rd(BRK3_ADDR1);
279 
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== BRK3_ADDR1 uncorrect =====");
280 
      dbg_uart_wr(BRK3_ADDR1 ,  16'h0000);
281 
      dbg_uart_rd(BRK3_ADDR1);
282 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK3_ADDR1 uncorrect =====");
283 
 
284 
 
285 
      // TEST 16B WRITE BURSTS (MEMORY)
286 
      //--------------------------------------------------------
287 
 
288 
      dbg_uart_wr(MEM_ADDR, 16'h0200); // select @0x0200
289 
      dbg_uart_wr(MEM_CNT,  16'h0004); // 5 consecutive access
290 
 
291 
      dbg_uart_wr(MEM_CTL,  16'h0003); // Start burst to 16 bit memory write
292 
      dbg_uart_tx16(16'h1234);         // write 1st data
293 95 olivier.gi 
      repeat(12) @(posedge mclk);
294 2 olivier.gi 
      if (mem200 !== 16'h1234)      tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 1st DATA =====");
295 
      dbg_uart_tx16(16'h5678);         // write 2nd data
296 95 olivier.gi 
      repeat(12) @(posedge mclk);
297 2 olivier.gi 
      if (mem202 !== 16'h5678)      tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 2nd DATA =====");
298 
      dbg_uart_tx16(16'h9abc);         // write 3rd data
299 95 olivier.gi 
      repeat(12) @(posedge mclk);
300 2 olivier.gi 
      if (mem204 !== 16'h9abc)      tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 3rd DATA =====");
301 
      dbg_uart_tx16(16'hdef0);         // write 4th data
302 95 olivier.gi 
      repeat(12) @(posedge mclk);
303 2 olivier.gi 
      if (mem206 !== 16'hdef0)      tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 4th DATA =====");
304 
      dbg_uart_tx16(16'h0fed);         // write 5th data
305 95 olivier.gi 
      repeat(12) @(posedge mclk);
306 2 olivier.gi 
      if (mem208 !== 16'h0fed)      tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 5th DATA =====");
307 
 
308 
      dbg_uart_wr(MEM_ADDR, 16'h0200); // select @0x0200
309 
      dbg_uart_wr(MEM_CNT,  16'h0004); // 5 consecutive access
310 
 
311 
      dbg_uart_wr(MEM_CTL,  16'h0001); // Start burst to 16 bit registers read
312 
      dbg_uart_rx16();                 // read 1st data
313 
      if (dbg_uart_buf !== 16'h1234)      tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 1st DATA =====");
314 
      dbg_uart_rx16();                 // read 2nd data
315 
      if (dbg_uart_buf !== 16'h5678)      tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 2nd DATA =====");
316 
      dbg_uart_rx16();                 // read 3rd data
317 
      if (dbg_uart_buf !== 16'h9abc)      tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 3rd DATA =====");
318 
      dbg_uart_rx16();                 // read 4th data
319 
      if (dbg_uart_buf !== 16'hdef0)      tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 4th DATA =====");
320 
      dbg_uart_rx16();                 // read 5th data
321 
      if (dbg_uart_buf !== 16'h0fed)      tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 5th DATA =====");
322 
 
323 
 
324 
      // TEST 16B WRITE BURSTS (CPU REGISTERS)
325 
      //--------------------------------------------------------
326 
 
327 
      dbg_uart_wr(MEM_ADDR, 16'h0005); // select R5
328 
      dbg_uart_wr(MEM_CNT,  16'h0004); // 5 consecutive access
329 
 
330 
      dbg_uart_wr(MEM_CTL,  16'h0007); // Start burst to 16 bit cpu register write
331 
      dbg_uart_tx16(16'hcba9);         // write 1st data
332 95 olivier.gi 
      repeat(12) @(posedge mclk);
333 2 olivier.gi 
      if (r5 !== 16'hcba9)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 1st DATA =====");
334 
      dbg_uart_tx16(16'h8765);         // write 2nd data
335 95 olivier.gi 
      repeat(12) @(posedge mclk);
336 2 olivier.gi 
      if (r6 !== 16'h8765)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 2nd DATA =====");
337 
      dbg_uart_tx16(16'h4321);         // write 3rd data
338 95 olivier.gi 
      repeat(12) @(posedge mclk);
339 2 olivier.gi 
      if (r7 !== 16'h4321)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 3rd DATA =====");
340 
      dbg_uart_tx16(16'h0123);         // write 4th data
341 95 olivier.gi 
      repeat(12) @(posedge mclk);
342 2 olivier.gi 
      if (r8 !== 16'h0123)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 4th DATA =====");
343 
      dbg_uart_tx16(16'h4567);         // write 5th data
344 95 olivier.gi 
      repeat(12) @(posedge mclk);
345 2 olivier.gi 
      if (r9 !== 16'h4567)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 5th DATA =====");
346 
 
347 
      dbg_uart_wr(MEM_ADDR, 16'h0005); // select @0x0200
348 
      dbg_uart_wr(MEM_CNT,  16'h0004); // 5 consecutive access
349 
 
350 
      dbg_uart_wr(MEM_CTL,  16'h0005); // Start burst to 16 bit cpu registers read
351 
      dbg_uart_rx16();                 // read 1st data
352 
      if (dbg_uart_buf !== 16'hcba9)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 1st DATA =====");
353 
      dbg_uart_rx16();                 // read 2nd data
354 
      if (dbg_uart_buf !== 16'h8765)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 2nd DATA =====");
355 
      dbg_uart_rx16();                 // read 3rd data
356 
      if (dbg_uart_buf !== 16'h4321)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 3rd DATA =====");
357 
      dbg_uart_rx16();                 // read 4th data
358 
      if (dbg_uart_buf !== 16'h0123)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 4th DATA =====");
359 
      dbg_uart_rx16();                 // read 5th data
360 
      if (dbg_uart_buf !== 16'h4567)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 5th DATA =====");
361 
 
362 
 
363 
      // TEST 8B WRITE BURSTS (MEMORY)
364 
      //--------------------------------------------------------
365 
 
366 
      dbg_uart_wr(MEM_ADDR, 16'h0200); // select @0x0210
367 
      dbg_uart_wr(MEM_CNT,  16'h0004); // 5 consecutive access
368 
 
369 
      dbg_uart_wr(MEM_CTL,  16'h000b); // Start burst to 8 bit memory write
370 
      dbg_uart_tx(8'h91);         // write 1st data
371 95 olivier.gi 
      repeat(12) @(posedge mclk);
372 2 olivier.gi 
      if (mem200 !== 16'h1291)      tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 1st DATA =====");
373 
      dbg_uart_tx(8'h82);         // write 2nd data
374 95 olivier.gi 
      repeat(12) @(posedge mclk);
375 2 olivier.gi 
      if (mem200 !== 16'h8291)      tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 2nd DATA =====");
376 
      dbg_uart_tx(8'h73);         // write 3rd data
377 95 olivier.gi 
      repeat(12) @(posedge mclk);
378 2 olivier.gi 
      if (mem202 !== 16'h5673)      tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 3rd DATA =====");
379 
      dbg_uart_tx(8'h64);         // write 4th data
380 95 olivier.gi 
      repeat(12) @(posedge mclk);
381 2 olivier.gi 
      if (mem202 !== 16'h6473)      tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 4th DATA =====");
382 
      dbg_uart_tx(8'h55);         // write 5th data
383 95 olivier.gi 
      repeat(12) @(posedge mclk);
384 2 olivier.gi 
      if (mem204 !== 16'h9a55)      tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 5th DATA =====");
385 
 
386 
      dbg_uart_wr(MEM_ADDR, 16'h0200); // select @0x0200
387 
      dbg_uart_wr(MEM_CNT,  16'h0004); // 5 consecutive access
388 
 
389 
      dbg_uart_wr(MEM_CTL,  16'h0009); // Start burst to 8 bit registers read
390 
      dbg_uart_rx8();                 // read 1st data
391 
      if (dbg_uart_buf !== 16'h0091)      tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 1st DATA =====");
392 
      dbg_uart_rx8();                 // read 2nd data
393 
      if (dbg_uart_buf !== 16'h0082)      tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 2nd DATA =====");
394 
      dbg_uart_rx8();                 // read 3rd data
395 
      if (dbg_uart_buf !== 16'h0073)      tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 3rd DATA =====");
396 
      dbg_uart_rx8();                 // read 4th data
397 
      if (dbg_uart_buf !== 16'h0064)      tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 4th DATA =====");
398 
      dbg_uart_rx8();                 // read 5th data
399 
      if (dbg_uart_buf !== 16'h0055)      tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 5th DATA =====");
400 
 
401 
 
402 
 
403 
 
404 
 
405 
      dbg_uart_wr(CPU_CTL    ,  16'h0002);
406 
      repeat(10) @(posedge mclk);
407 
 
408 
      stimulus_done = 1;
409 
   end
410 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.