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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [lp_modes_dbg_asic.s43] - Blame information for rev 134

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/*===========================================================================*/
/* Copyright (C) 2001 Authors                                                */
/*                                                                           */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any   */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer.                                                               */
/*                                                                           */
/* This source file is free software; you can redistribute it and/or modify  */
/* it under the terms of the GNU Lesser General Public License as published  */
/* by the Free Software Foundation; either version 2.1 of the License, or    */
/* (at your option) any later version.                                       */
/*                                                                           */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
/* License for more details.                                                 */
/*                                                                           */
/* You should have received a copy of the GNU Lesser General Public License  */
/* along with this source; if not, write to the Free Software Foundation,    */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/*                                                                           */
/*===========================================================================*/
/*                            CPU OPERATING MODES                            */
/*---------------------------------------------------------------------------*/
/* Test the CPU Low Power modes:                                             */
/*                              - LPM0    <=>  CPUOFF                        */
/*                              - LPM1    <=>  CPUOFF + SCG0                 */
/*                              - LPM2    <=>  CPUOFF +        SCG1          */
/*                              - LPM3    <=>  CPUOFF + SCG0 + SCG1          */
/*                              - LPM4    <=>  CPUOFF + SCG0 + SCG1 + OSCOFF */
/*                                                                           */
/* Reminder:                                                                 */
/*                              - CPUOFF  <=>  turns off CPU.                */
/*                              - SCG0    <=>  turns off DCO.                */
/*                              - SCG1    <=>  turns off SMCLK.              */
/*                              - OSCOFF  <=>  turns off LFXT_CLK.           */
/*                                                                           */
/* Author(s):                                                                */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*                                                                           */
/*---------------------------------------------------------------------------*/
/* $Rev: 19 $                                                                */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $          */
/*===========================================================================*/
 
.global main
 
.set   DMEM_BASE, (__data_start     )
.set   DMEM_200,  (__data_start+0x00)
.set   DMEM_250,  (__data_start+0x50)
 
.set   BCSCTL1, 0x0057
.set   BCSCTL2, 0x0058
 
.macro LPM0
 bis    #0x0010, r2
.endm
.macro LPM1
 bis    #0x0050, r2
.endm
.macro LPM2
 bis    #0x0090, r2
.endm
.macro LPM3
 bis    #0x00D0, r2
.endm
.macro LPM4
 bis    #0x00F0, r2
.endm
 
.macro LPM0_exit
 bic    #0x0010, @r1
.endm
.macro LPM1_exit
 bic    #0x0050, @r1
.endm
.macro LPM2_exit
 bic    #0x0090, @r1
.endm
.macro LPM3_exit
 bic    #0x00D0, @r1
.endm
.macro LPM4_exit
 bic    #0x00F0, @r1
.endm
 
 
WAIT_FUNC:
        dec r14
        jnz WAIT_FUNC
        ret
 
main:
 
        ; Initialize stack and enable global interrupts
        mov    #DMEM_250, r1
        eint
 
        ; Wait for a while to give enough time to ACLK
        mov    #0x0050, r14
        call   #WAIT_FUNC
        mov    #0x1000, r15
 
        /* --------------- ACTIVE ------------------------------------------ */
 
        mov    #0x1001, r15
        mov.b  #0x00, &BCSCTL2  ; # MCLK  = DCO_CLK
                                ; # SMCLK = DCO_CLK
        mov    #0x0080, r14
        call   #WAIT_FUNC
 
        mov    #0x2000, r15
 
 
        /* --------------- LPM0  ( CPUOFF ) -------------------------------- */
 
        mov    #0x2001, r15
        mov.b  #0x00, &BCSCTL2  ; # MCLK  = DCO_CLK
                                ; # SMCLK = DCO_CLK
 
        LPM0                    ; #                     MCLK off
        mov    #0x0090, r14
        call   #WAIT_FUNC
 
        mov    #0x3000, r15
 
 
        /* --------------- LPM1  ( CPUOFF + SCG0 ) ------------------------- */
 
        mov    #0x3001, r15
        mov.b  #0x08, &BCSCTL2  ; # MCLK  = DCO_CLK
                                ; # SMCLK = LFXT_CLK
 
        LPM1                    ; #                     MCLK off + DCO off
        mov    #0x0090, r14
        call   #WAIT_FUNC
 
        mov    #0x4000, r15
 
 
        /*---------------- LPM2  ( CPUOFF + SCG1 ) ------------------------- */
 
        mov    #0x4001, r15
        mov.b  #0x08, &BCSCTL2  ; # MCLK  = DCO_CLK
                                ; # SMCLK = LFXT_CLK
 
        LPM2                    ; #                     MCLK off + SMCLK off
        mov    #0x0190, r14
        call   #WAIT_FUNC
 
        mov    #0x5000, r15
 
 
        /*---------------- LPM3  ( CPUOFF + SCG0 + SCG1 ) ------------------ */
 
        mov    #0x5001, r15
        mov.b  #0x08, &BCSCTL2  ; # MCLK  = DCO_CLK
                                ; # SMCLK = LFXT_CLK
 
        LPM3                    ; #                     MCLK off + DCO off + SMCLK off
        mov    #0x0190, r14
        call   #WAIT_FUNC
 
        mov    #0x6000, r15
 
 
        /*---------------- LPM4  ( CPUOFF + SCG0 + SCG1 + OSCOFF ) --------- */
 
        mov    #0x6001, r15
        mov.b  #0x08, &BCSCTL2  ; # MCLK  = DCO_CLK
                                ; # SMCLK = LFXT_CLK
 
        LPM4                    ; #                     MCLK off + DCO off + SMCLK off + LFXT off
        mov    #0x0100, r14
        call   #WAIT_FUNC
 
        mov    #0x6000, r15
 
 
        /* ----------------------         END OF TEST        --------------- */
end_of_test:
        nop
        br #0xffff
 
 
        /* ----------------------      INTERRUPT ROUTINES    --------------- */
 
PORT1_VECTOR:
        push       r13
        push       r14
        mov    #0x0060, r14
        call   #WAIT_FUNC
        mov    #0xaaaa, r13
        pop        r14
        pop        r13
        reti
 
PORT2_VECTOR:
        push       r13
        push       r14
        mov    #0x0060, r14
        call   #WAIT_FUNC
        mov    #0xbbbb, r13
        pop        r14
        pop        r13
        bic    #0xf0, 0(r1) ;exit all lowpower mode
        reti
 
 
        /* ----------------------         INTERRUPT VECTORS  --------------- */
 
.section .vectors, "a"
.word end_of_test  ; Interrupt  0 (lowest priority)    
.word end_of_test  ; Interrupt  1                      
.word PORT1_VECTOR ; Interrupt  2                      
.word PORT2_VECTOR ; Interrupt  3                      
.word end_of_test  ; Interrupt  4                      
.word end_of_test  ; Interrupt  5                      
.word end_of_test  ; Interrupt  6                      
.word end_of_test  ; Interrupt  7                      
.word end_of_test  ; Interrupt  8                      
.word end_of_test  ; Interrupt  9                      
.word end_of_test  ; Interrupt 10                      Watchdog timer
.word end_of_test  ; Interrupt 11                      
.word end_of_test  ; Interrupt 12                      
.word end_of_test  ; Interrupt 13                      
.word end_of_test  ; Interrupt 14                      NMI
.word main         ; Interrupt 15 (highest priority)   RESET

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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [lp_modes_dbg_asic.s43] - Blame information for rev 134

Line No.	Rev	Author	Line
1	134	olivier.gi	`/===========================================================================/`
2			`/* Copyright (C) 2001 Authors */`
3			`/* */`
4			`/* This source file may be used and distributed without restriction provided */`
5			`/* that this copyright statement is not removed from the file and that any */`
6			`/* derivative work contains the original copyright notice and the associated */`
7			`/* disclaimer. */`
8			`/* */`
9			`/* This source file is free software; you can redistribute it and/or modify */`
10			`/* it under the terms of the GNU Lesser General Public License as published */`
11			`/* by the Free Software Foundation; either version 2.1 of the License, or */`
12			`/* (at your option) any later version. */`
13			`/* */`
14			`/* This source is distributed in the hope that it will be useful, but WITHOUT*/`
15			`/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */`
16			`/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */`
17			`/* License for more details. */`
18			`/* */`
19			`/* You should have received a copy of the GNU Lesser General Public License */`
20			`/* along with this source; if not, write to the Free Software Foundation, */`
21			`/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */`
22			`/* */`
23			`/===========================================================================/`
24			`/* CPU OPERATING MODES */`
25			`/---------------------------------------------------------------------------/`
26			`/* Test the CPU Low Power modes: */`
27			`/* - LPM0 <=> CPUOFF */`
28			`/* - LPM1 <=> CPUOFF + SCG0 */`
29			`/* - LPM2 <=> CPUOFF + SCG1 */`
30			`/* - LPM3 <=> CPUOFF + SCG0 + SCG1 */`
31			`/* - LPM4 <=> CPUOFF + SCG0 + SCG1 + OSCOFF */`
32			`/* */`
33			`/* Reminder: */`
34			`/* - CPUOFF <=> turns off CPU. */`
35			`/* - SCG0 <=> turns off DCO. */`
36			`/* - SCG1 <=> turns off SMCLK. */`
37			`/* - OSCOFF <=> turns off LFXT_CLK. */`
38			`/* */`
39			`/* Author(s): */`
40			`/* - Olivier Girard, olgirard@gmail.com */`
41			`/* */`
42			`/---------------------------------------------------------------------------/`
43			`/* $Rev: 19 $ */`
44			`/* $LastChangedBy: olivier.girard $ */`
45			`/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */`
46			`/===========================================================================/`
47
48			`.global main`
49
50			`.set DMEM_BASE, (__data_start )`
51			`.set DMEM_200, (__data_start+0x00)`
52			`.set DMEM_250, (__data_start+0x50)`
53
54			`.set BCSCTL1, 0x0057`
55			`.set BCSCTL2, 0x0058`
56
57			`.macro LPM0`
58			`bis #0x0010, r2`
59			`.endm`
60			`.macro LPM1`
61			`bis #0x0050, r2`
62			`.endm`
63			`.macro LPM2`
64			`bis #0x0090, r2`
65			`.endm`
66			`.macro LPM3`
67			`bis #0x00D0, r2`
68			`.endm`
69			`.macro LPM4`
70			`bis #0x00F0, r2`
71			`.endm`
72
73			`.macro LPM0_exit`
74			`bic #0x0010, @r1`
75			`.endm`
76			`.macro LPM1_exit`
77			`bic #0x0050, @r1`
78			`.endm`
79			`.macro LPM2_exit`
80			`bic #0x0090, @r1`
81			`.endm`
82			`.macro LPM3_exit`
83			`bic #0x00D0, @r1`
84			`.endm`
85			`.macro LPM4_exit`
86			`bic #0x00F0, @r1`
87			`.endm`
88
89
90			`WAIT_FUNC:`
91			`dec r14`
92			`jnz WAIT_FUNC`
93			`ret`
94
95			`main:`
96
97			`; Initialize stack and enable global interrupts`
98			`mov #DMEM_250, r1`
99			`eint`
100
101			`; Wait for a while to give enough time to ACLK`
102			`mov #0x0050, r14`
103			`call #WAIT_FUNC`
104			`mov #0x1000, r15`
105
106			`/* --------------- ACTIVE ------------------------------------------ */`
107
108			`mov #0x1001, r15`
109			`mov.b #0x00, &BCSCTL2 ; # MCLK = DCO_CLK`
110			`; # SMCLK = DCO_CLK`
111			`mov #0x0080, r14`
112			`call #WAIT_FUNC`
113
114			`mov #0x2000, r15`
115
116
117			`/* --------------- LPM0 ( CPUOFF ) -------------------------------- */`
118
119			`mov #0x2001, r15`
120			`mov.b #0x00, &BCSCTL2 ; # MCLK = DCO_CLK`
121			`; # SMCLK = DCO_CLK`
122
123			`LPM0 ; # MCLK off`
124			`mov #0x0090, r14`
125			`call #WAIT_FUNC`
126
127			`mov #0x3000, r15`
128
129
130			`/* --------------- LPM1 ( CPUOFF + SCG0 ) ------------------------- */`
131
132			`mov #0x3001, r15`
133			`mov.b #0x08, &BCSCTL2 ; # MCLK = DCO_CLK`
134			`; # SMCLK = LFXT_CLK`
135
136			`LPM1 ; # MCLK off + DCO off`
137			`mov #0x0090, r14`
138			`call #WAIT_FUNC`
139
140			`mov #0x4000, r15`
141
142
143			`/---------------- LPM2 ( CPUOFF + SCG1 ) ------------------------- /`
144
145			`mov #0x4001, r15`
146			`mov.b #0x08, &BCSCTL2 ; # MCLK = DCO_CLK`
147			`; # SMCLK = LFXT_CLK`
148
149			`LPM2 ; # MCLK off + SMCLK off`
150			`mov #0x0190, r14`
151			`call #WAIT_FUNC`
152
153			`mov #0x5000, r15`
154
155
156			`/---------------- LPM3 ( CPUOFF + SCG0 + SCG1 ) ------------------ /`
157
158			`mov #0x5001, r15`
159			`mov.b #0x08, &BCSCTL2 ; # MCLK = DCO_CLK`
160			`; # SMCLK = LFXT_CLK`
161
162			`LPM3 ; # MCLK off + DCO off + SMCLK off`
163			`mov #0x0190, r14`
164			`call #WAIT_FUNC`
165
166			`mov #0x6000, r15`
167
168
169			`/---------------- LPM4 ( CPUOFF + SCG0 + SCG1 + OSCOFF ) --------- /`
170
171			`mov #0x6001, r15`
172			`mov.b #0x08, &BCSCTL2 ; # MCLK = DCO_CLK`
173			`; # SMCLK = LFXT_CLK`
174
175			`LPM4 ; # MCLK off + DCO off + SMCLK off + LFXT off`
176			`mov #0x0100, r14`
177			`call #WAIT_FUNC`
178
179			`mov #0x6000, r15`
180
181
182			`/* ---------------------- END OF TEST --------------- */`
183			`end_of_test:`
184			`nop`
185			`br #0xffff`
186
187
188			`/* ---------------------- INTERRUPT ROUTINES --------------- */`
189
190			`PORT1_VECTOR:`
191			`push r13`
192			`push r14`
193			`mov #0x0060, r14`
194			`call #WAIT_FUNC`
195			`mov #0xaaaa, r13`
196			`pop r14`
197			`pop r13`
198			`reti`
199
200			`PORT2_VECTOR:`
201			`push r13`
202			`push r14`
203			`mov #0x0060, r14`
204			`call #WAIT_FUNC`
205			`mov #0xbbbb, r13`
206			`pop r14`
207			`pop r13`
208			`bic #0xf0, 0(r1) ;exit all lowpower mode`
209			`reti`
210
211
212			`/* ---------------------- INTERRUPT VECTORS --------------- */`
213
214			`.section .vectors, "a"`
215			`.word end_of_test ; Interrupt 0 (lowest priority)`
216			`.word end_of_test ; Interrupt 1`
217			`.word PORT1_VECTOR ; Interrupt 2`
218			`.word PORT2_VECTOR ; Interrupt 3`
219			`.word end_of_test ; Interrupt 4`
220			`.word end_of_test ; Interrupt 5`
221			`.word end_of_test ; Interrupt 6`
222			`.word end_of_test ; Interrupt 7`
223			`.word end_of_test ; Interrupt 8`
224			`.word end_of_test ; Interrupt 9`
225			`.word end_of_test ; Interrupt 10 Watchdog timer`
226			`.word end_of_test ; Interrupt 11`
227			`.word end_of_test ; Interrupt 12`
228			`.word end_of_test ; Interrupt 13`
229			`.word end_of_test ; Interrupt 14 NMI`
230			`.word main ; Interrupt 15 (highest priority) RESET`