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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [sfr.v] - Blame information for rev 134

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/*===========================================================================*/
/* Copyright (C) 2001 Authors                                                */
/*                                                                           */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any   */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer.                                                               */
/*                                                                           */
/* This source file is free software; you can redistribute it and/or modify  */
/* it under the terms of the GNU Lesser General Public License as published  */
/* by the Free Software Foundation; either version 2.1 of the License, or    */
/* (at your option) any later version.                                       */
/*                                                                           */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
/* License for more details.                                                 */
/*                                                                           */
/* You should have received a copy of the GNU Lesser General Public License  */
/* along with this source; if not, write to the Free Software Foundation,    */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/*                                                                           */
/*===========================================================================*/
/*                  Special Function Registers (SFRs)                        */
/*---------------------------------------------------------------------------*/
/* Test the SFR registers.                                                   */
/*                                                                           */
/* Author(s):                                                                */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*                                                                           */
/*---------------------------------------------------------------------------*/
/* $Rev: 85 $                                                                */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedDate: 2011-01-28 22:05:37 +0100 (Fri, 28 Jan 2011) $          */
/*===========================================================================*/
 
reg  [2:0] cpu_version;
reg        cpu_asic;
reg  [4:0] user_version;
reg  [6:0] per_space;
reg        mpy_info;
reg  [8:0] dmem_size;
reg  [5:0] pmem_size;
reg [31:0] dbg_id;
 
initial
   begin
      $display(" ===============================================");
      $display("|                 START SIMULATION              |");
      $display(" ===============================================");
      repeat(5) @(posedge mclk);
      stimulus_done = 0;
 
      //  NMI
      //------------------------------
      @(r15 === 16'h1000);
 
      // NMI feature is verified in the NMI.S43 test
 
      @(r15 === 16'h1001);
 
      //  WATCHDOG
      //------------------------------
      @(r15 === 16'h2000);
 
      // WATCHDOG feature is verified in the WDT_*.S43 tests
 
      @(r15 === 16'h2001);
 
 
      //  READ/WRITE IFG1
      //------------------------------
      @(r15 === 16'h3000);
 
      @(r15 === 16'h3001);
      if (r10 !== 16'h0000)   tb_error("====== IFG1 incorrect (test 1) =====");
 
      @(r15 === 16'h3002);
      `ifdef NMI
         `ifdef WATCHDOG
      if (r10 !== 16'h0011)   tb_error("====== IFG1 incorrect (test 2) =====");
         `else
      if (r10 !== 16'h0010)   tb_error("====== IFG1 incorrect (test 3) =====");
         `endif
      `else
         `ifdef WATCHDOG
      if (r10 !== 16'h0001)   tb_error("====== IFG1 incorrect (test 4) =====");
         `else
      if (r10 !== 16'h0000)   tb_error("====== IFG1 incorrect (test 5) =====");
         `endif
      `endif
 
      @(r15 === 16'h3003);
      if (r10 !== 16'h0000)   tb_error("====== IFG1 incorrect (test 6) =====");
 
      @(r15 === 16'h3004);
      `ifdef NMI
         `ifdef WATCHDOG
      if (r10 !== 16'h0011)   tb_error("====== IFG1 incorrect (test 7) =====");
         `else
      if (r10 !== 16'h0010)   tb_error("====== IFG1 incorrect (test 8) =====");
         `endif
      `else
         `ifdef WATCHDOG
      if (r10 !== 16'h0001)   tb_error("====== IFG1 incorrect (test 9) =====");
         `else
      if (r10 !== 16'h0000)   tb_error("====== IFG1 incorrect (test 10) =====");
         `endif
      `endif
 
      @(r15 === 16'h3005);
      if (r10 !== 16'h0000)   tb_error("====== IFG1 incorrect (test 11) =====");
 
      @(r15 === 16'h3006);
      if (r10 !== 16'h0000)   tb_error("====== IFG1 incorrect (test 12) =====");
 
 
      //  READ/WRITE IE1
      //------------------------------
      @(r15 === 16'h4000);
 
      @(r15 === 16'h4001);
      if (r10 !== 16'h0000)   tb_error("====== IE1 incorrect (test 1) =====");
 
      @(r15 === 16'h4002);
      `ifdef NMI
         `ifdef WATCHDOG
      if (r10 !== 16'h0011)   tb_error("====== IE1 incorrect (test 2) =====");
         `else
      if (r10 !== 16'h0010)   tb_error("====== IE1 incorrect (test 3) =====");
         `endif
      `else
         `ifdef WATCHDOG
      if (r10 !== 16'h0001)   tb_error("====== IE1 incorrect (test 4) =====");
         `else
      if (r10 !== 16'h0000)   tb_error("====== IE1 incorrect (test 5) =====");
         `endif
      `endif
 
      @(r15 === 16'h4003);
      if (r10 !== 16'h0000)   tb_error("====== IE1 incorrect (test 6) =====");
 
      @(r15 === 16'h4004);
      `ifdef NMI
         `ifdef WATCHDOG
      if (r10 !== 16'h0011)   tb_error("====== IE1 incorrect (test 7) =====");
         `else
      if (r10 !== 16'h0010)   tb_error("====== IE1 incorrect (test 8) =====");
         `endif
      `else
         `ifdef WATCHDOG
      if (r10 !== 16'h0001)   tb_error("====== IE1 incorrect (test 9) =====");
         `else
      if (r10 !== 16'h0000)   tb_error("====== IE1 incorrect (test 10) =====");
         `endif
      `endif
 
      @(r15 === 16'h4005);
      if (r10 !== 16'h0000)   tb_error("====== IE1 incorrect (test 11) =====");
 
      @(r15 === 16'h4006);
      if (r10 !== 16'h0000)   tb_error("====== IE1 incorrect (test 12) =====");
 
 
      // READ/WRITE CPU_ID
      //------------------------------
      @(r15 === 16'h5000);
 
      cpu_version  =  `CPU_VERSION;
`ifdef ASIC
      cpu_asic     =  1'b1;
`else
      cpu_asic     =  1'b0;
`endif
      user_version =  `USER_VERSION;
      per_space    = (`PER_SIZE  >> 9);
`ifdef MULTIPLIER
      mpy_info     =  1'b1;
`else
      mpy_info     =  1'b0;
`endif
      dmem_size    = (`DMEM_SIZE >> 7);
      pmem_size    = (`PMEM_SIZE >> 10);
 
      dbg_id       = {pmem_size,
                      dmem_size,
                      mpy_info,
                      per_space,
                      user_version,
                      cpu_asic,
                      cpu_version};
 
      @(r15 === 16'h5001);
      if (r10 !== dbg_id[15:0])   tb_error("====== CPU_ID_LO incorrect (test 1) =====");
      if (r11 !== dbg_id[31:16])  tb_error("====== CPU_ID_HI incorrect (test 2) =====");
 
      @(r15 === 16'h5002);
      if (r10 !== dbg_id[15:0])   tb_error("====== CPU_ID_LO incorrect (test 3) =====");
      if (r11 !== dbg_id[31:16])  tb_error("====== CPU_ID_HI incorrect (test 4) =====");
 
      @(r15 === 16'h5003);
      if (r10 !== dbg_id[15:0])   tb_error("====== CPU_ID_LO incorrect (test 5) =====");
      if (r11 !== dbg_id[31:16])  tb_error("====== CPU_ID_HI incorrect (test 6) =====");
 
      stimulus_done = 1;
   end
 

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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [sfr.v] - Blame information for rev 134

Line No.	Rev	Author	Line
1	134	olivier.gi	`/===========================================================================/`
2			`/* Copyright (C) 2001 Authors */`
3			`/* */`
4			`/* This source file may be used and distributed without restriction provided */`
5			`/* that this copyright statement is not removed from the file and that any */`
6			`/* derivative work contains the original copyright notice and the associated */`
7			`/* disclaimer. */`
8			`/* */`
9			`/* This source file is free software; you can redistribute it and/or modify */`
10			`/* it under the terms of the GNU Lesser General Public License as published */`
11			`/* by the Free Software Foundation; either version 2.1 of the License, or */`
12			`/* (at your option) any later version. */`
13			`/* */`
14			`/* This source is distributed in the hope that it will be useful, but WITHOUT*/`
15			`/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */`
16			`/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */`
17			`/* License for more details. */`
18			`/* */`
19			`/* You should have received a copy of the GNU Lesser General Public License */`
20			`/* along with this source; if not, write to the Free Software Foundation, */`
21			`/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */`
22			`/* */`
23			`/===========================================================================/`
24			`/* Special Function Registers (SFRs) */`
25			`/---------------------------------------------------------------------------/`
26			`/* Test the SFR registers. */`
27			`/* */`
28			`/* Author(s): */`
29			`/* - Olivier Girard, olgirard@gmail.com */`
30			`/* */`
31			`/---------------------------------------------------------------------------/`
32			`/* $Rev: 85 $ */`
33			`/* $LastChangedBy: olivier.girard $ */`
34			`/* $LastChangedDate: 2011-01-28 22:05:37 +0100 (Fri, 28 Jan 2011) $ */`
35			`/===========================================================================/`
36
37			`reg [2:0] cpu_version;`
38			`reg cpu_asic;`
39			`reg [4:0] user_version;`
40			`reg [6:0] per_space;`
41			`reg mpy_info;`
42			`reg [8:0] dmem_size;`
43			`reg [5:0] pmem_size;`
44			`reg [31:0] dbg_id;`
45
46			`initial`
47			`begin`
48			`$display(" ===============================================");`
49			`$display("\| START SIMULATION \|");`
50			`$display(" ===============================================");`
51			`repeat(5) @(posedge mclk);`
52			`stimulus_done = 0;`
53
54			`// NMI`
55			`//------------------------------`
56			`@(r15 === 16'h1000);`
57
58			`// NMI feature is verified in the NMI.S43 test`
59
60			`@(r15 === 16'h1001);`
61
62			`// WATCHDOG`
63			`//------------------------------`
64			`@(r15 === 16'h2000);`
65
66			`// WATCHDOG feature is verified in the WDT_*.S43 tests`
67
68			`@(r15 === 16'h2001);`
69
70
71			`// READ/WRITE IFG1`
72			`//------------------------------`
73			`@(r15 === 16'h3000);`
74
75			`@(r15 === 16'h3001);`
76			`if (r10 !== 16'h0000) tb_error("====== IFG1 incorrect (test 1) =====");`
77
78			`@(r15 === 16'h3002);`
79			`ifdef NMI
80			`ifdef WATCHDOG
81			`if (r10 !== 16'h0011) tb_error("====== IFG1 incorrect (test 2) =====");`
82			`else
83			`if (r10 !== 16'h0010) tb_error("====== IFG1 incorrect (test 3) =====");`
84			`endif
85			`else
86			`ifdef WATCHDOG
87			`if (r10 !== 16'h0001) tb_error("====== IFG1 incorrect (test 4) =====");`
88			`else
89			`if (r10 !== 16'h0000) tb_error("====== IFG1 incorrect (test 5) =====");`
90			`endif
91			`endif
92
93			`@(r15 === 16'h3003);`
94			`if (r10 !== 16'h0000) tb_error("====== IFG1 incorrect (test 6) =====");`
95
96			`@(r15 === 16'h3004);`
97			`ifdef NMI
98			`ifdef WATCHDOG
99			`if (r10 !== 16'h0011) tb_error("====== IFG1 incorrect (test 7) =====");`
100			`else
101			`if (r10 !== 16'h0010) tb_error("====== IFG1 incorrect (test 8) =====");`
102			`endif
103			`else
104			`ifdef WATCHDOG
105			`if (r10 !== 16'h0001) tb_error("====== IFG1 incorrect (test 9) =====");`
106			`else
107			`if (r10 !== 16'h0000) tb_error("====== IFG1 incorrect (test 10) =====");`
108			`endif
109			`endif
110
111			`@(r15 === 16'h3005);`
112			`if (r10 !== 16'h0000) tb_error("====== IFG1 incorrect (test 11) =====");`
113
114			`@(r15 === 16'h3006);`
115			`if (r10 !== 16'h0000) tb_error("====== IFG1 incorrect (test 12) =====");`
116
117
118			`// READ/WRITE IE1`
119			`//------------------------------`
120			`@(r15 === 16'h4000);`
121
122			`@(r15 === 16'h4001);`
123			`if (r10 !== 16'h0000) tb_error("====== IE1 incorrect (test 1) =====");`
124
125			`@(r15 === 16'h4002);`
126			`ifdef NMI
127			`ifdef WATCHDOG
128			`if (r10 !== 16'h0011) tb_error("====== IE1 incorrect (test 2) =====");`
129			`else
130			`if (r10 !== 16'h0010) tb_error("====== IE1 incorrect (test 3) =====");`
131			`endif
132			`else
133			`ifdef WATCHDOG
134			`if (r10 !== 16'h0001) tb_error("====== IE1 incorrect (test 4) =====");`
135			`else
136			`if (r10 !== 16'h0000) tb_error("====== IE1 incorrect (test 5) =====");`
137			`endif
138			`endif
139
140			`@(r15 === 16'h4003);`
141			`if (r10 !== 16'h0000) tb_error("====== IE1 incorrect (test 6) =====");`
142
143			`@(r15 === 16'h4004);`
144			`ifdef NMI
145			`ifdef WATCHDOG
146			`if (r10 !== 16'h0011) tb_error("====== IE1 incorrect (test 7) =====");`
147			`else
148			`if (r10 !== 16'h0010) tb_error("====== IE1 incorrect (test 8) =====");`
149			`endif
150			`else
151			`ifdef WATCHDOG
152			`if (r10 !== 16'h0001) tb_error("====== IE1 incorrect (test 9) =====");`
153			`else
154			`if (r10 !== 16'h0000) tb_error("====== IE1 incorrect (test 10) =====");`
155			`endif
156			`endif
157
158			`@(r15 === 16'h4005);`
159			`if (r10 !== 16'h0000) tb_error("====== IE1 incorrect (test 11) =====");`
160
161			`@(r15 === 16'h4006);`
162			`if (r10 !== 16'h0000) tb_error("====== IE1 incorrect (test 12) =====");`
163
164
165			`// READ/WRITE CPU_ID`
166			`//------------------------------`
167			`@(r15 === 16'h5000);`
168
169			cpu_version = `CPU_VERSION;
170			`ifdef ASIC
171			`cpu_asic = 1'b1;`
172			`else
173			`cpu_asic = 1'b0;`
174			`endif
175			user_version = `USER_VERSION;
176			per_space = (`PER_SIZE >> 9);
177			`ifdef MULTIPLIER
178			`mpy_info = 1'b1;`
179			`else
180			`mpy_info = 1'b0;`
181			`endif
182			dmem_size = (`DMEM_SIZE >> 7);
183			pmem_size = (`PMEM_SIZE >> 10);
184
185			`dbg_id = {pmem_size,`
186			`dmem_size,`
187			`mpy_info,`
188			`per_space,`
189			`user_version,`
190			`cpu_asic,`
191			`cpu_version};`
192
193			`@(r15 === 16'h5001);`
194			`if (r10 !== dbg_id[15:0]) tb_error("====== CPU_ID_LO incorrect (test 1) =====");`
195			`if (r11 !== dbg_id[31:16]) tb_error("====== CPU_ID_HI incorrect (test 2) =====");`
196
197			`@(r15 === 16'h5002);`
198			`if (r10 !== dbg_id[15:0]) tb_error("====== CPU_ID_LO incorrect (test 3) =====");`
199			`if (r11 !== dbg_id[31:16]) tb_error("====== CPU_ID_HI incorrect (test 4) =====");`
200
201			`@(r15 === 16'h5003);`
202			`if (r10 !== dbg_id[15:0]) tb_error("====== CPU_ID_LO incorrect (test 5) =====");`
203			`if (r11 !== dbg_id[31:16]) tb_error("====== CPU_ID_HI incorrect (test 6) =====");`
204
205			`stimulus_done = 1;`
206			`end`
207