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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [sing-op_reti.s43] - Blame information for rev 141

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/*===========================================================================*/
/* Copyright (C) 2001 Authors                                                */
/*                                                                           */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any   */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer.                                                               */
/*                                                                           */
/* This source file is free software; you can redistribute it and/or modify  */
/* it under the terms of the GNU Lesser General Public License as published  */
/* by the Free Software Foundation; either version 2.1 of the License, or    */
/* (at your option) any later version.                                       */
/*                                                                           */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
/* License for more details.                                                 */
/*                                                                           */
/* You should have received a copy of the GNU Lesser General Public License  */
/* along with this source; if not, write to the Free Software Foundation,    */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/*                                                                           */
/*===========================================================================*/
/*                 SINGLE-OPERAND ARITHMETIC: CALL  INSTRUCTION              */
/*---------------------------------------------------------------------------*/
/* Test the CALL  instruction.                                               */
/*                                                                           */
/* Author(s):                                                                */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*                                                                           */
/*---------------------------------------------------------------------------*/
/* $Rev: 141 $                                                                */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedDate: 2012-05-05 23:22:06 +0200 (Sat, 05 May 2012) $          */
/*===========================================================================*/
 
.include "pmem_defs.asm"
 
.global main
 
        mov     #0x1234, r3
        mov     #0x1234, r4
        mov     #0x1234, r5
        mov     #0x1234, r6
        mov     #0x1234, r7
        mov     #0x1234, r8
        mov     #0x1234, r9
        mov     #0x1234, r10
        mov     #0x1234, r11
        mov     #0x1234, r12
        mov     #0x1234, r13
        mov     #0x1234, r14
main:
        # Test RESET vector
        #------------------------
        mov     #0x1000, r15
 
 
        # Test RETI instruction
        #------------------------
 
        # Pre-initialize stack
        mov             #DMEM_252, r1
        push #RETI_ROUTINE
        push            #0x010f
        mov     #0x0000, &0x0200
 
        # Run RETI test
        mov     #0x0000, r2
        mov     #0x0000, r5
        reti
end_of_reti_test:
 
        mov     #0x2000, r15
 
 
        # Test IRQ  0
        #-------------------------
 
        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0x3000, r15
 
wait_irq00:
        cmp     #0x5678, r6
        jne     wait_irq00
 
        mov     #0x3001, r15
 
 
        # Test IRQ  1
        #-------------------------
 
        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0x4000, r15
 
wait_irq01:
        cmp     #0x9abc, r6
        jne     wait_irq01
 
        mov     #0x4001, r15
 
 
        # Test IRQ  2
        #-------------------------
 
        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0x5000, r15
 
wait_irq02:
        cmp     #0xdef1, r6
        jne     wait_irq02
 
        mov     #0x5001, r15
 
 
        # Test IRQ  3
        #-------------------------
 
        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0x6000, r15
 
wait_irq03:
        cmp     #0x2345, r6
        jne     wait_irq03
 
        mov     #0x6001, r15
 
 
        # Test IRQ  4
        #-------------------------
 
        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0x7000, r15
 
wait_irq04:
        cmp     #0x6789, r6
        jne     wait_irq04
 
        mov     #0x7001, r15
 
 
        # Test IRQ  5
        #-------------------------
 
        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0x8000, r15
 
wait_irq05:
        cmp     #0xabcd, r6
        jne     wait_irq05
 
        mov     #0x8001, r15
 
 
        # Test IRQ  6
        #-------------------------
 
        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0x9000, r15
 
wait_irq06:
        cmp     #0xef12, r6
        jne     wait_irq06
 
        mov     #0x9001, r15
 
 
        # Test IRQ  7
        #-------------------------
 
        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0xa000, r15
 
wait_irq07:
        cmp     #0x3456, r6
        jne     wait_irq07
 
        mov     #0xa001, r15
 
 
        # Test IRQ  8
        #-------------------------
 
        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0xb000, r15
 
wait_irq08:
        cmp     #0x789a, r6
        jne     wait_irq08
 
        mov     #0xb001, r15
 
 
        # Test IRQ  9
        #-------------------------
 
        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0xc000, r15
 
wait_irq09:
        cmp     #0xbcde, r6
        jne     wait_irq09
 
        mov     #0xc001, r15
 
 
        # Test IRQ 10
        #-------------------------
 
        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0xd000, r15
 
wait_irq10:
        cmp     #0xf123, r6
        jne     wait_irq10
 
        mov     #0xd001, r15
 
 
        # Test IRQ 11
        #-------------------------
 
        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0xe000, r15
 
wait_irq11:
        cmp     #0x4567, r6
        jne     wait_irq11
 
        mov     #0xe001, r15
 
 
        # Test IRQ 12
        #-------------------------
 
        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0xf000, r15
 
wait_irq12:
        cmp     #0x89ab, r6
        jne     wait_irq12
 
        mov     #0xf001, r15
 
 
        # Test IRQ 13
        #-------------------------
 
        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0xf100, r15
 
wait_irq13:
        cmp     #0xcdef, r6
        jne     wait_irq13
 
        mov     #0xf101, r15
 
 
        # Test IRQ NMI:  rising edge
        #----------------------------
 
.set   WDTCTL, 0x0120
.set   IE1,    0x0000
.set   IFG1,   0x0002
 
 
        mov     #0x5a00, &WDTCTL  ; NMI Edge selection: rising
        bic.b   #0x0010, &IFG1    ; Clear NMI flag
        bis.b   #0x0010, &IE1     ; Enable NMI
 
        bit     #0x0010, &IE1     ; skip this test if the NMI is not included
        jz      skip_nmi
 
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0xf200, r15
 
wait_nmi:
        mov     #0xa5a5, &0x0200
        cmp     #0x0123, r6
        jne    wait_nmi
 
        mov.b      &IE1,  r9
        mov.b     &IFG1, r10
        bic.b     #0x10, &IFG1    ; Clear NMI flag
        bis.b     #0x10, &IE1     ; Enable NMI
 
skip_nmi:
        mov     #0xf201, r15
 
 
 
        /* ----------------------    END OF TEST   --------------- */
end_of_test:
        nop
        br #0xffff
 
 
 
        /* ----------------------    FUNCTIONS    --------------- */
 
RETI_ROUTINE:
        mov #0x1234, r5
        jmp end_of_reti_test
 
 
IRQ00_ROUTINE:
        mov #0x5678, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti
 
IRQ01_ROUTINE:
        mov #0x9abc, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti
 
IRQ02_ROUTINE:
        mov #0xdef1, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti
 
IRQ03_ROUTINE:
        mov #0x2345, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti
 
IRQ04_ROUTINE:
        mov #0x6789, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti
 
IRQ05_ROUTINE:
        mov #0xabcd, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti
 
IRQ06_ROUTINE:
        mov #0xef12, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti
 
IRQ07_ROUTINE:
        mov #0x3456, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti
 
IRQ08_ROUTINE:
        mov #0x789a, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti
 
IRQ09_ROUTINE:
        mov #0xbcde, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti
 
IRQ10_ROUTINE:
        mov #0xf123, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti
 
IRQ11_ROUTINE:
        mov #0x4567, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti
 
IRQ12_ROUTINE:
        mov #0x89ab, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti
 
IRQ13_ROUTINE:
        mov #0xcdef, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti
 
NMI_ROUTINE:
        mov #0x0123, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti
 
        nop
        nop
        nop
        nop
        nop
 
 
 
        /* ----------------------         INTERRUPT VECTORS  --------------- */
 
.section .vectors, "a"
.word IRQ00_ROUTINE     ; Interrupt  0 (lowest priority)    
.word IRQ01_ROUTINE     ; Interrupt  1                      
.word IRQ02_ROUTINE     ; Interrupt  2                      
.word IRQ03_ROUTINE     ; Interrupt  3                      
.word IRQ04_ROUTINE     ; Interrupt  4                      
.word IRQ05_ROUTINE     ; Interrupt  5                      
.word IRQ06_ROUTINE     ; Interrupt  6                      
.word IRQ07_ROUTINE     ; Interrupt  7                      
.word IRQ08_ROUTINE     ; Interrupt  8                      
.word IRQ09_ROUTINE     ; Interrupt  9                      
.word IRQ10_ROUTINE     ; Interrupt 10                      Watchdog timer
.word IRQ11_ROUTINE     ; Interrupt 11                      
.word IRQ12_ROUTINE     ; Interrupt 12                      
.word IRQ13_ROUTINE     ; Interrupt 13                      
.word NMI_ROUTINE       ; Interrupt 14                      NMI
.word main              ; Interrupt 15 (highest priority)   RESET

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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [sing-op_reti.s43] - Blame information for rev 141

Line No.	Rev	Author	Line
1	2	olivier.gi	`/===========================================================================/`
2			`/* Copyright (C) 2001 Authors */`
3			`/* */`
4			`/* This source file may be used and distributed without restriction provided */`
5			`/* that this copyright statement is not removed from the file and that any */`
6			`/* derivative work contains the original copyright notice and the associated */`
7			`/* disclaimer. */`
8			`/* */`
9			`/* This source file is free software; you can redistribute it and/or modify */`
10			`/* it under the terms of the GNU Lesser General Public License as published */`
11			`/* by the Free Software Foundation; either version 2.1 of the License, or */`
12			`/* (at your option) any later version. */`
13			`/* */`
14			`/* This source is distributed in the hope that it will be useful, but WITHOUT*/`
15			`/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */`
16			`/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */`
17			`/* License for more details. */`
18			`/* */`
19			`/* You should have received a copy of the GNU Lesser General Public License */`
20			`/* along with this source; if not, write to the Free Software Foundation, */`
21			`/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */`
22			`/* */`
23			`/===========================================================================/`
24			`/* SINGLE-OPERAND ARITHMETIC: CALL INSTRUCTION */`
25			`/---------------------------------------------------------------------------/`
26			`/* Test the CALL instruction. */`
27	18	olivier.gi	`/* */`
28			`/* Author(s): */`
29			`/* - Olivier Girard, olgirard@gmail.com */`
30			`/* */`
31			`/---------------------------------------------------------------------------/`
32	19	olivier.gi	`/* $Rev: 141 $ */`
33			`/* $LastChangedBy: olivier.girard $ */`
34			`/* $LastChangedDate: 2012-05-05 23:22:06 +0200 (Sat, 05 May 2012) $ */`
35	2	olivier.gi	`/===========================================================================/`
36
37	141	olivier.gi	`.include "pmem_defs.asm"`
38	2	olivier.gi
39			`.global main`
40
41			`mov #0x1234, r3`
42			`mov #0x1234, r4`
43			`mov #0x1234, r5`
44			`mov #0x1234, r6`
45			`mov #0x1234, r7`
46			`mov #0x1234, r8`
47			`mov #0x1234, r9`
48			`mov #0x1234, r10`
49			`mov #0x1234, r11`
50			`mov #0x1234, r12`
51			`mov #0x1234, r13`
52			`mov #0x1234, r14`
53			`main:`
54			`# Test RESET vector`
55			`#------------------------`
56			`mov #0x1000, r15`
57
58
59			`# Test RETI instruction`
60			`#------------------------`
61
62			`# Pre-initialize stack`
63	111	olivier.gi	`mov #DMEM_252, r1`
64	2	olivier.gi	`push #RETI_ROUTINE`
65	134	olivier.gi	`push #0x010f`
66	2	olivier.gi	`mov #0x0000, &0x0200`
67
68			`# Run RETI test`
69			`mov #0x0000, r2`
70			`mov #0x0000, r5`
71			`reti`
72			`end_of_reti_test:`
73
74			`mov #0x2000, r15`
75
76
77			`# Test IRQ 0`
78			`#-------------------------`
79
80			`mov #0x0008, r2 ; Enable interrupts`
81			`mov #0x0000, r6`
82			`mov #0xaaaa, r7`
83			`mov #0x5555, r8`
84			`mov #0x3000, r15`
85
86			`wait_irq00:`
87			`cmp #0x5678, r6`
88			`jne wait_irq00`
89
90			`mov #0x3001, r15`
91
92
93			`# Test IRQ 1`
94			`#-------------------------`
95
96			`mov #0x0008, r2 ; Enable interrupts`
97			`mov #0x0000, r6`
98			`mov #0xaaaa, r7`
99			`mov #0x5555, r8`
100			`mov #0x4000, r15`
101
102			`wait_irq01:`
103			`cmp #0x9abc, r6`
104			`jne wait_irq01`
105
106			`mov #0x4001, r15`
107
108
109			`# Test IRQ 2`
110			`#-------------------------`
111
112			`mov #0x0008, r2 ; Enable interrupts`
113			`mov #0x0000, r6`
114			`mov #0xaaaa, r7`
115			`mov #0x5555, r8`
116			`mov #0x5000, r15`
117
118			`wait_irq02:`
119			`cmp #0xdef1, r6`
120			`jne wait_irq02`
121
122			`mov #0x5001, r15`
123
124
125			`# Test IRQ 3`
126			`#-------------------------`
127
128			`mov #0x0008, r2 ; Enable interrupts`
129			`mov #0x0000, r6`
130			`mov #0xaaaa, r7`
131			`mov #0x5555, r8`
132			`mov #0x6000, r15`
133
134			`wait_irq03:`
135			`cmp #0x2345, r6`
136			`jne wait_irq03`
137
138			`mov #0x6001, r15`
139
140
141			`# Test IRQ 4`
142			`#-------------------------`
143
144			`mov #0x0008, r2 ; Enable interrupts`
145			`mov #0x0000, r6`
146			`mov #0xaaaa, r7`
147			`mov #0x5555, r8`
148			`mov #0x7000, r15`
149
150			`wait_irq04:`
151			`cmp #0x6789, r6`
152			`jne wait_irq04`
153
154			`mov #0x7001, r15`
155
156
157			`# Test IRQ 5`
158			`#-------------------------`
159
160			`mov #0x0008, r2 ; Enable interrupts`
161			`mov #0x0000, r6`
162			`mov #0xaaaa, r7`
163			`mov #0x5555, r8`
164			`mov #0x8000, r15`
165
166			`wait_irq05:`
167			`cmp #0xabcd, r6`
168			`jne wait_irq05`
169
170			`mov #0x8001, r15`
171
172
173			`# Test IRQ 6`
174			`#-------------------------`
175
176			`mov #0x0008, r2 ; Enable interrupts`
177			`mov #0x0000, r6`
178			`mov #0xaaaa, r7`
179			`mov #0x5555, r8`
180			`mov #0x9000, r15`
181
182			`wait_irq06:`
183			`cmp #0xef12, r6`
184			`jne wait_irq06`
185
186			`mov #0x9001, r15`
187
188
189			`# Test IRQ 7`
190			`#-------------------------`
191
192			`mov #0x0008, r2 ; Enable interrupts`
193			`mov #0x0000, r6`
194			`mov #0xaaaa, r7`
195			`mov #0x5555, r8`
196			`mov #0xa000, r15`
197
198			`wait_irq07:`
199			`cmp #0x3456, r6`
200			`jne wait_irq07`
201
202			`mov #0xa001, r15`
203
204
205			`# Test IRQ 8`
206			`#-------------------------`
207
208			`mov #0x0008, r2 ; Enable interrupts`
209			`mov #0x0000, r6`
210			`mov #0xaaaa, r7`
211			`mov #0x5555, r8`
212			`mov #0xb000, r15`
213
214			`wait_irq08:`
215			`cmp #0x789a, r6`
216			`jne wait_irq08`
217
218			`mov #0xb001, r15`
219
220
221			`# Test IRQ 9`
222			`#-------------------------`
223
224			`mov #0x0008, r2 ; Enable interrupts`
225			`mov #0x0000, r6`
226			`mov #0xaaaa, r7`
227			`mov #0x5555, r8`
228			`mov #0xc000, r15`
229
230			`wait_irq09:`
231			`cmp #0xbcde, r6`
232			`jne wait_irq09`
233
234			`mov #0xc001, r15`
235
236
237			`# Test IRQ 10`
238			`#-------------------------`
239
240			`mov #0x0008, r2 ; Enable interrupts`
241			`mov #0x0000, r6`
242			`mov #0xaaaa, r7`
243			`mov #0x5555, r8`
244			`mov #0xd000, r15`
245
246			`wait_irq10:`
247			`cmp #0xf123, r6`
248			`jne wait_irq10`
249
250			`mov #0xd001, r15`
251
252
253			`# Test IRQ 11`
254			`#-------------------------`
255
256			`mov #0x0008, r2 ; Enable interrupts`
257			`mov #0x0000, r6`
258			`mov #0xaaaa, r7`
259			`mov #0x5555, r8`
260			`mov #0xe000, r15`
261
262			`wait_irq11:`
263			`cmp #0x4567, r6`
264			`jne wait_irq11`
265
266			`mov #0xe001, r15`
267
268
269			`# Test IRQ 12`
270			`#-------------------------`
271
272			`mov #0x0008, r2 ; Enable interrupts`
273			`mov #0x0000, r6`
274			`mov #0xaaaa, r7`
275			`mov #0x5555, r8`
276			`mov #0xf000, r15`
277
278			`wait_irq12:`
279			`cmp #0x89ab, r6`
280			`jne wait_irq12`
281
282			`mov #0xf001, r15`
283
284
285			`# Test IRQ 13`
286			`#-------------------------`
287
288			`mov #0x0008, r2 ; Enable interrupts`
289			`mov #0x0000, r6`
290			`mov #0xaaaa, r7`
291			`mov #0x5555, r8`
292			`mov #0xf100, r15`
293
294			`wait_irq13:`
295			`cmp #0xcdef, r6`
296			`jne wait_irq13`
297
298			`mov #0xf101, r15`
299
300
301			`# Test IRQ NMI: rising edge`
302			`#----------------------------`
303	134	olivier.gi
304	2	olivier.gi	`.set WDTCTL, 0x0120`
305			`.set IE1, 0x0000`
306			`.set IFG1, 0x0002`
307
308	134	olivier.gi
309	2	olivier.gi	`mov #0x5a00, &WDTCTL ; NMI Edge selection: rising`
310			`bic.b #0x0010, &IFG1 ; Clear NMI flag`
311			`bis.b #0x0010, &IE1 ; Enable NMI`
312
313	134	olivier.gi	`bit #0x0010, &IE1 ; skip this test if the NMI is not included`
314			`jz skip_nmi`
315
316	2	olivier.gi	`mov #0x0000, r6`
317			`mov #0xaaaa, r7`
318			`mov #0x5555, r8`
319			`mov #0xf200, r15`
320
321			`wait_nmi:`
322			`mov #0xa5a5, &0x0200`
323			`cmp #0x0123, r6`
324			`jne wait_nmi`
325
326			`mov.b &IE1, r9`
327	134	olivier.gi	`mov.b &IFG1, r10`
328			`bic.b #0x10, &IFG1 ; Clear NMI flag`
329			`bis.b #0x10, &IE1 ; Enable NMI`
330	2	olivier.gi
331	134	olivier.gi	`skip_nmi:`
332	2	olivier.gi	`mov #0xf201, r15`
333
334
335
336			`/* ---------------------- END OF TEST --------------- */`
337			`end_of_test:`
338			`nop`
339			`br #0xffff`
340
341
342
343			`/* ---------------------- FUNCTIONS --------------- */`
344
345			`RETI_ROUTINE:`
346			`mov #0x1234, r5`
347			`jmp end_of_reti_test`
348
349
350			`IRQ00_ROUTINE:`
351			`mov #0x5678, r6`
352			`mov r2, r7 ; Save Status register`
353			`mov r1, r8 ; Save Stack register`
354			`reti`
355
356			`IRQ01_ROUTINE:`
357			`mov #0x9abc, r6`
358			`mov r2, r7 ; Save Status register`
359			`mov r1, r8 ; Save Stack register`
360			`reti`
361
362			`IRQ02_ROUTINE:`
363			`mov #0xdef1, r6`
364			`mov r2, r7 ; Save Status register`
365			`mov r1, r8 ; Save Stack register`
366			`reti`
367
368			`IRQ03_ROUTINE:`
369			`mov #0x2345, r6`
370			`mov r2, r7 ; Save Status register`
371			`mov r1, r8 ; Save Stack register`
372			`reti`
373
374			`IRQ04_ROUTINE:`
375			`mov #0x6789, r6`
376			`mov r2, r7 ; Save Status register`
377			`mov r1, r8 ; Save Stack register`
378			`reti`
379
380			`IRQ05_ROUTINE:`
381			`mov #0xabcd, r6`
382			`mov r2, r7 ; Save Status register`
383			`mov r1, r8 ; Save Stack register`
384			`reti`
385
386			`IRQ06_ROUTINE:`
387			`mov #0xef12, r6`
388			`mov r2, r7 ; Save Status register`
389			`mov r1, r8 ; Save Stack register`
390			`reti`
391
392			`IRQ07_ROUTINE:`
393			`mov #0x3456, r6`
394			`mov r2, r7 ; Save Status register`
395			`mov r1, r8 ; Save Stack register`
396			`reti`
397
398			`IRQ08_ROUTINE:`
399			`mov #0x789a, r6`
400			`mov r2, r7 ; Save Status register`
401			`mov r1, r8 ; Save Stack register`
402			`reti`
403
404			`IRQ09_ROUTINE:`
405			`mov #0xbcde, r6`
406			`mov r2, r7 ; Save Status register`
407			`mov r1, r8 ; Save Stack register`
408			`reti`
409
410			`IRQ10_ROUTINE:`
411			`mov #0xf123, r6`
412			`mov r2, r7 ; Save Status register`
413			`mov r1, r8 ; Save Stack register`
414			`reti`
415
416			`IRQ11_ROUTINE:`
417			`mov #0x4567, r6`
418			`mov r2, r7 ; Save Status register`
419			`mov r1, r8 ; Save Stack register`
420			`reti`
421
422			`IRQ12_ROUTINE:`
423			`mov #0x89ab, r6`
424			`mov r2, r7 ; Save Status register`
425			`mov r1, r8 ; Save Stack register`
426			`reti`
427
428			`IRQ13_ROUTINE:`
429			`mov #0xcdef, r6`
430			`mov r2, r7 ; Save Status register`
431			`mov r1, r8 ; Save Stack register`
432			`reti`
433
434			`NMI_ROUTINE:`
435			`mov #0x0123, r6`
436			`mov r2, r7 ; Save Status register`
437			`mov r1, r8 ; Save Stack register`
438			`reti`
439
440			`nop`
441			`nop`
442			`nop`
443			`nop`
444			`nop`
445
446
447
448			`/* ---------------------- INTERRUPT VECTORS --------------- */`
449
450			`.section .vectors, "a"`
451			`.word IRQ00_ROUTINE ; Interrupt 0 (lowest priority)`
452			`.word IRQ01_ROUTINE ; Interrupt 1`
453			`.word IRQ02_ROUTINE ; Interrupt 2`
454			`.word IRQ03_ROUTINE ; Interrupt 3`
455			`.word IRQ04_ROUTINE ; Interrupt 4`
456			`.word IRQ05_ROUTINE ; Interrupt 5`
457			`.word IRQ06_ROUTINE ; Interrupt 6`
458			`.word IRQ07_ROUTINE ; Interrupt 7`
459			`.word IRQ08_ROUTINE ; Interrupt 8`
460			`.word IRQ09_ROUTINE ; Interrupt 9`
461			`.word IRQ10_ROUTINE ; Interrupt 10 Watchdog timer`
462			`.word IRQ11_ROUTINE ; Interrupt 11`
463			`.word IRQ12_ROUTINE ; Interrupt 12`
464			`.word IRQ13_ROUTINE ; Interrupt 13`
465			`.word NMI_ROUTINE ; Interrupt 14 NMI`
466			`.word main ; Interrupt 15 (highest priority) RESET`