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//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200's ALU                                                ////
4
////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
6 185 julius
////  http://www.opencores.org/project,or1k                       ////
7 10 unneback
////                                                              ////
8
////  Description                                                 ////
9
////  ALU                                                         ////
10
////                                                              ////
11
////  To Do:                                                      ////
12
////   - make it smaller and faster                               ////
13
////                                                              ////
14
////  Author(s):                                                  ////
15
////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44 141 marcus.erl
// $Log: or1200_alu.v,v $
45
// Revision 2.0  2010/06/30 11:00:00  ORSoC
46
// Minor update: 
47
// Defines added, flags are corrected. 
48 10 unneback
 
49
// synopsys translate_off
50
`include "timescale.v"
51
// synopsys translate_on
52
`include "or1200_defines.v"
53
 
54
module or1200_alu(
55
        a, b, mult_mac_result, macrc_op,
56 640 julius
        alu_op, alu_op2, comp_op,
57 10 unneback
        cust5_op, cust5_limm,
58
        result, flagforw, flag_we,
59 642 julius
        ovforw, ov_we,
60 10 unneback
        cyforw, cy_we, carry, flag
61
);
62
 
63
parameter width = `OR1200_OPERAND_WIDTH;
64
 
65
//
66
// I/O
67
//
68
input   [width-1:0]              a;
69
input   [width-1:0]              b;
70
input   [width-1:0]              mult_mac_result;
71
input                           macrc_op;
72
input   [`OR1200_ALUOP_WIDTH-1:0]        alu_op;
73 401 julius
input   [`OR1200_ALUOP2_WIDTH-1:0]       alu_op2;
74 10 unneback
input   [`OR1200_COMPOP_WIDTH-1:0]       comp_op;
75
input   [4:0]                    cust5_op;
76
input   [5:0]                    cust5_limm;
77
output  [width-1:0]              result;
78
output                          flagforw;
79
output                          flag_we;
80
output                          cyforw;
81
output                          cy_we;
82 642 julius
output                          ovforw;
83
output                          ov_we;
84 10 unneback
input                           carry;
85
input         flag;
86
 
87
//
88
// Internal wires and regs
89
//
90
reg     [width-1:0]              result;
91
reg     [width-1:0]              shifted_rotated;
92 640 julius
reg     [width-1:0]              extended;
93 10 unneback
reg     [width-1:0]              result_cust5;
94
reg                             flagforw;
95
reg                             flagcomp;
96
reg                             flag_we;
97 642 julius
reg                             cyforw;
98 10 unneback
reg                             cy_we;
99 642 julius
reg                             ovforw;
100
reg                             ov_we;
101 10 unneback
wire    [width-1:0]              comp_a;
102
wire    [width-1:0]              comp_b;
103
wire                            a_eq_b;
104
wire                            a_lt_b;
105
wire    [width-1:0]              result_sum;
106
wire    [width-1:0]              result_and;
107
wire                            cy_sum;
108 141 marcus.erl
`ifdef OR1200_IMPL_SUB
109
wire                            cy_sub;
110
`endif
111 642 julius
wire                            ov_sum;
112
wire    [width-1:0]              carry_in;
113 10 unneback
 
114 642 julius
wire    [width-1:0]              b_mux;
115
 
116
 
117
 
118 10 unneback
//
119
// Combinatorial logic
120
//
121 643 julius
 
122 10 unneback
assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};
123
assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};
124
`ifdef OR1200_IMPL_ALU_COMP1
125
assign a_eq_b = (comp_a == comp_b);
126
assign a_lt_b = (comp_a < comp_b);
127
`endif
128 643 julius
`ifdef OR1200_IMPL_ALU_COMP3
129
assign a_eq_b = !(|result_sum);
130
// signed compare when comp_op[3] is set
131
assign a_lt_b = comp_op[3] ? ((a[width-1] & !b[width-1]) |
132
                              (!a[width-1] & !b[width-1] & result_sum[width-1])|
133
                              (a[width-1] & b[width-1] & result_sum[width-1])):
134 674 julius
                (a < b);
135
 
136 643 julius
`endif
137
 
138 141 marcus.erl
`ifdef OR1200_IMPL_SUB
139 643 julius
 `ifdef OR1200_IMPL_ALU_COMP3
140
assign cy_sub = a_lt_b;
141
 `else
142 642 julius
assign cy_sub = (comp_a < comp_b);
143 643 julius
 `endif
144 141 marcus.erl
`endif
145 643 julius
 
146 642 julius
`ifdef OR1200_IMPL_ADDC
147
assign carry_in = (alu_op==`OR1200_ALUOP_ADDC) ?
148
                  {{width-1{1'b0}},carry} : {width{1'b0}};
149
`else
150
assign carry_in = {width-1{1'b0}};
151 10 unneback
`endif
152 643 julius
 
153
`ifdef OR1200_IMPL_ALU_COMP3
154 642 julius
`ifdef OR1200_IMPL_SUB
155 643 julius
assign b_mux = ((alu_op==`OR1200_ALUOP_SUB) | (alu_op==`OR1200_ALUOP_COMP)) ?
156
                (~b)+1 : b;
157
`else
158
assign b_mux = (alu_op==`OR1200_ALUOP_COMP) ? (~b)+1 : b;
159
`endif
160
`else // ! `ifdef OR1200_IMPL_ALU_COMP3
161
`ifdef OR1200_IMPL_SUB
162 642 julius
assign b_mux = (alu_op==`OR1200_ALUOP_SUB) ? (~b)+1 : b;
163
`else
164
assign b_mux = b;
165 643 julius
`endif
166
`endif
167 642 julius
assign {cy_sum, result_sum} = (a + b_mux) + carry_in;
168
// Numbers either both +ve and bit 31 of result set
169
assign ov_sum = ((!a[width-1] & !b_mux[width-1]) & result_sum[width-1]) |
170
// or both -ve and bit 31 of result clear
171
                ((a[width-1] & b_mux[width-1]) & !result_sum[width-1]);
172 10 unneback
assign result_and = a & b;
173
 
174
//
175
// Simulation check for bad ALU behavior
176
//
177
`ifdef OR1200_WARNINGS
178
// synopsys translate_off
179
always @(result) begin
180
        if (result === 32'bx)
181
                $display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);
182
end
183
// synopsys translate_on
184
`endif
185
 
186
//
187
// Central part of the ALU
188
//
189 401 julius
always @(alu_op or alu_op2 or a or b or result_sum or result_and or macrc_op
190
         or shifted_rotated or mult_mac_result or flag or result_cust5 or carry
191 640 julius
`ifdef OR1200_IMPL_ALU_EXT
192
         or extended
193
`endif
194 141 marcus.erl
) begin
195 10 unneback
`ifdef OR1200_CASE_DEFAULT
196 364 julius
        casez (alu_op)          // synopsys parallel_case
197 10 unneback
`else
198 364 julius
        casez (alu_op)          // synopsys full_case parallel_case
199 10 unneback
`endif
200 401 julius
`ifdef OR1200_IMPL_ALU_FFL1
201
                `OR1200_ALUOP_FFL1: begin
202
`ifdef OR1200_CASE_DEFAULT
203
                   casez (alu_op2) // synopsys parallel_case
204
`else
205
                   casez (alu_op2) // synopsys full_case parallel_case
206
`endif
207
                     0: begin // FF1
208 141 marcus.erl
                        result = a[0] ? 1 : a[1] ? 2 : a[2] ? 3 : a[3] ? 4 : a[4] ? 5 : a[5] ? 6 : a[6] ? 7 : a[7] ? 8 : a[8] ? 9 : a[9] ? 10 : a[10] ? 11 : a[11] ? 12 : a[12] ? 13 : a[13] ? 14 : a[14] ? 15 : a[15] ? 16 : a[16] ? 17 : a[17] ? 18 : a[18] ? 19 : a[19] ? 20 : a[20] ? 21 : a[21] ? 22 : a[22] ? 23 : a[23] ? 24 : a[24] ? 25 : a[25] ? 26 : a[26] ? 27 : a[27] ? 28 : a[28] ? 29 : a[29] ? 30 : a[30] ? 31 : a[31] ? 32 : 0;
209 401 julius
                     end
210
                     default: begin // FL1
211
                        result = a[31] ? 32 : a[30] ? 31 : a[29] ? 30 : a[28] ? 29 : a[27] ? 28 : a[26] ? 27 : a[25] ? 26 : a[24] ? 25 : a[23] ? 24 : a[22] ? 23 : a[21] ? 22 : a[20] ? 21 : a[19] ? 20 : a[18] ? 19 : a[17] ? 18 : a[16] ? 17 : a[15] ? 16 : a[14] ? 15 : a[13] ? 14 : a[12] ? 13 : a[11] ? 12 : a[10] ? 11 : a[9] ? 10 : a[8] ? 9 : a[7] ? 8 : a[6] ? 7 : a[5] ? 6 : a[4] ? 5 : a[3] ? 4 : a[2] ? 3 : a[1] ? 2 : a[0] ? 1 : 0 ;
212
                     end
213
                   endcase // casez (alu_op2)
214
                end // case: `OR1200_ALUOP_FFL1
215 640 julius
`endif //  `ifdef OR1200_IMPL_ALU_FFL1
216
`ifdef OR1200_IMPL_ALU_CUST5
217
 
218 10 unneback
                `OR1200_ALUOP_CUST5 : begin
219
                                result = result_cust5;
220
                end
221 640 julius
`endif
222 10 unneback
                `OR1200_ALUOP_SHROT : begin
223
                                result = shifted_rotated;
224
                end
225
`ifdef OR1200_IMPL_ADDC
226 642 julius
                `OR1200_ALUOP_ADDC,
227 10 unneback
`endif
228 141 marcus.erl
`ifdef OR1200_IMPL_SUB
229 642 julius
                `OR1200_ALUOP_SUB,
230
`endif
231
                `OR1200_ALUOP_ADD : begin
232
                                result = result_sum;
233 10 unneback
                end
234
                `OR1200_ALUOP_XOR : begin
235
                                result = a ^ b;
236
                end
237
                `OR1200_ALUOP_OR  : begin
238
                                result = a | b;
239
                end
240 640 julius
`ifdef OR1200_IMPL_ALU_EXT
241
                `OR1200_ALUOP_EXTHB  : begin
242
                                result = extended;
243
                end
244
                `OR1200_ALUOP_EXTW  : begin
245
                                result = extended;
246
                end
247
`endif
248 10 unneback
                `OR1200_ALUOP_MOVHI : begin
249
                                if (macrc_op) begin
250
                                        result = mult_mac_result;
251
                                end
252
                                else begin
253
                                        result = b << 16;
254
                                end
255
                end
256
`ifdef OR1200_MULT_IMPLEMENTED
257 258 julius
`ifdef OR1200_DIV_IMPLEMENTED
258 10 unneback
                `OR1200_ALUOP_DIV,
259
                `OR1200_ALUOP_DIVU,
260
`endif
261 481 julius
                `OR1200_ALUOP_MUL,
262
                `OR1200_ALUOP_MULU : begin
263 10 unneback
                                result = mult_mac_result;
264
                end
265
`endif
266 141 marcus.erl
                `OR1200_ALUOP_CMOV: begin
267
                        result = flag ? a : b;
268
                end
269 10 unneback
 
270
`ifdef OR1200_CASE_DEFAULT
271 141 marcus.erl
                default: begin
272 10 unneback
`else
273 141 marcus.erl
                `OR1200_ALUOP_COMP, `OR1200_ALUOP_AND: begin
274 10 unneback
`endif
275 141 marcus.erl
                        result=result_and;
276
                end
277 10 unneback
        endcase
278
end
279
 
280
//
281
// Generate flag and flag write enable
282
//
283 141 marcus.erl
always @(alu_op or result_sum or result_and or flagcomp
284
) begin
285 364 julius
        casez (alu_op)          // synopsys parallel_case
286 10 unneback
`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
287 642 julius
`ifdef OR1200_IMPL_ADDC
288
                `OR1200_ALUOP_ADDC,
289
`endif
290 10 unneback
                `OR1200_ALUOP_ADD : begin
291
                        flagforw = (result_sum == 32'h0000_0000);
292
                        flag_we = 1'b1;
293
                end
294
                `OR1200_ALUOP_AND: begin
295
                        flagforw = (result_and == 32'h0000_0000);
296
                        flag_we = 1'b1;
297
                end
298
`endif
299
                `OR1200_ALUOP_COMP: begin
300
                        flagforw = flagcomp;
301
                        flag_we = 1'b1;
302
                end
303
                default: begin
304 141 marcus.erl
                        flagforw = flagcomp;
305 10 unneback
                        flag_we = 1'b0;
306
                end
307
        endcase
308
end
309
 
310
//
311
// Generate SR[CY] write enable
312
//
313
always @(alu_op or cy_sum
314 141 marcus.erl
`ifdef OR1200_IMPL_CY
315
`ifdef OR1200_IMPL_SUB
316
        or cy_sub
317
`endif
318
`endif
319
) begin
320 364 julius
        casez (alu_op)          // synopsys parallel_case
321 10 unneback
`ifdef OR1200_IMPL_CY
322 642 julius
`ifdef OR1200_IMPL_ADDC
323
                `OR1200_ALUOP_ADDC,
324
`endif
325 10 unneback
                `OR1200_ALUOP_ADD : begin
326
                        cyforw = cy_sum;
327
                        cy_we = 1'b1;
328
                end
329 141 marcus.erl
`ifdef OR1200_IMPL_SUB
330
                `OR1200_ALUOP_SUB: begin
331
                        cyforw = cy_sub;
332
                        cy_we = 1'b1;
333
                end
334 10 unneback
`endif
335 141 marcus.erl
`endif
336 10 unneback
                default: begin
337
                        cyforw = 1'b0;
338
                        cy_we = 1'b0;
339
                end
340
        endcase
341
end
342
 
343 642 julius
 
344 10 unneback
//
345 642 julius
// Generate SR[OV] write enable
346
//
347
always @(alu_op or ov_sum) begin
348
        casez (alu_op)          // synopsys parallel_case
349
`ifdef OR1200_IMPL_OV
350
`ifdef OR1200_IMPL_ADDC
351
                `OR1200_ALUOP_ADDC,
352
`endif
353
`ifdef OR1200_IMPL_SUB
354
                `OR1200_ALUOP_SUB,
355
`endif
356
                `OR1200_ALUOP_ADD : begin
357
                        ovforw = ov_sum;
358
                        ov_we = 1'b1;
359
                end
360
`endif
361
                default: begin
362
                        ovforw = 1'b0;
363
                        ov_we = 1'b0;
364
                end
365
        endcase
366
end
367
 
368
//
369 10 unneback
// Shifts and rotation
370
//
371 640 julius
always @(alu_op2 or a or b) begin
372
        case (alu_op2)          // synopsys parallel_case
373
          `OR1200_SHROTOP_SLL :
374 10 unneback
                                shifted_rotated = (a << b[4:0]);
375 640 julius
          `OR1200_SHROTOP_SRL :
376 10 unneback
                                shifted_rotated = (a >> b[4:0]);
377
 
378
`ifdef OR1200_IMPL_ALU_ROTATE
379 640 julius
          `OR1200_SHROTOP_ROR :
380
                                shifted_rotated = (a << (6'd32-{1'b0,b[4:0]})) |
381
                                                  (a >> b[4:0]);
382 10 unneback
`endif
383 640 julius
          default:
384
                                shifted_rotated = ({32{a[31]}} <<
385
                                                   (6'd32-{1'b0, b[4:0]})) |
386
                                                  a >> b[4:0];
387 10 unneback
        endcase
388
end
389
 
390
//
391
// First type of compare implementation
392
//
393
`ifdef OR1200_IMPL_ALU_COMP1
394
always @(comp_op or a_eq_b or a_lt_b) begin
395
        case(comp_op[2:0])       // synopsys parallel_case
396
                `OR1200_COP_SFEQ:
397
                        flagcomp = a_eq_b;
398
                `OR1200_COP_SFNE:
399
                        flagcomp = ~a_eq_b;
400
                `OR1200_COP_SFGT:
401
                        flagcomp = ~(a_eq_b | a_lt_b);
402
                `OR1200_COP_SFGE:
403
                        flagcomp = ~a_lt_b;
404
                `OR1200_COP_SFLT:
405
                        flagcomp = a_lt_b;
406
                `OR1200_COP_SFLE:
407
                        flagcomp = a_eq_b | a_lt_b;
408
                default:
409
                        flagcomp = 1'b0;
410
        endcase
411
end
412
`endif
413
 
414
//
415
// Second type of compare implementation
416
//
417
`ifdef OR1200_IMPL_ALU_COMP2
418
always @(comp_op or comp_a or comp_b) begin
419
        case(comp_op[2:0])       // synopsys parallel_case
420
                `OR1200_COP_SFEQ:
421
                        flagcomp = (comp_a == comp_b);
422
                `OR1200_COP_SFNE:
423
                        flagcomp = (comp_a != comp_b);
424
                `OR1200_COP_SFGT:
425
                        flagcomp = (comp_a > comp_b);
426
                `OR1200_COP_SFGE:
427
                        flagcomp = (comp_a >= comp_b);
428
                `OR1200_COP_SFLT:
429
                        flagcomp = (comp_a < comp_b);
430
                `OR1200_COP_SFLE:
431
                        flagcomp = (comp_a <= comp_b);
432
                default:
433
                        flagcomp = 1'b0;
434
        endcase
435
end
436 643 julius
`endif //  `ifdef OR1200_IMPL_ALU_COMP2
437
 
438
`ifdef OR1200_IMPL_ALU_COMP3
439
always @(comp_op or a_eq_b or a_lt_b) begin
440
        case(comp_op[2:0])       // synopsys parallel_case
441
                `OR1200_COP_SFEQ:
442
                        flagcomp = a_eq_b;
443
                `OR1200_COP_SFNE:
444
                        flagcomp = ~a_eq_b;
445
                `OR1200_COP_SFGT:
446
                        flagcomp = ~(a_eq_b | a_lt_b);
447
                `OR1200_COP_SFGE:
448
                        flagcomp = ~a_lt_b;
449
                `OR1200_COP_SFLT:
450
                        flagcomp = a_lt_b;
451
                `OR1200_COP_SFLE:
452
                        flagcomp = a_eq_b | a_lt_b;
453
                default:
454
                        flagcomp = 1'b0;
455
        endcase
456
end
457 10 unneback
`endif
458 643 julius
 
459 10 unneback
 
460 640 julius
`ifdef OR1200_IMPL_ALU_EXT
461
   always @(alu_op or alu_op2 or a) begin
462
      casez (alu_op2)
463
        `OR1200_EXTHBOP_HS : extended = {{16{a[15]}},a[15:0]};
464
        `OR1200_EXTHBOP_BS : extended = {{24{a[7]}},a[7:0]};
465
        `OR1200_EXTHBOP_HZ : extended = {16'd0,a[15:0]};
466
        `OR1200_EXTHBOP_BZ : extended = {24'd0,a[7:0]};
467
        default: extended = a; // Used for l.extw instructions
468
      endcase // casez (alu_op2)
469
   end
470
`endif
471
 
472
 
473
//
474
// l.cust5 custom instructions
475
//
476
`ifdef OR1200_IMPL_ALU_CUST5
477
// Examples for move byte, set bit and clear bit
478
//
479
always @(cust5_op or cust5_limm or a or b) begin
480
        casez (cust5_op)                // synopsys parallel_case
481
                5'h1 : begin
482
                        casez (cust5_limm[1:0])
483
                          2'h0: result_cust5 = {a[31:8], b[7:0]};
484
                          2'h1: result_cust5 = {a[31:16], b[7:0], a[7:0]};
485
                          2'h2: result_cust5 = {a[31:24], b[7:0], a[15:0]};
486
                          2'h3: result_cust5 = {b[7:0], a[23:0]};
487
                        endcase
488
                end
489
                5'h2 :
490
                        result_cust5 = a | (1 << cust5_limm);
491
                5'h3 :
492
                        result_cust5 = a & (32'hffffffff ^ (1 << cust5_limm));
493
//
494
// *** Put here new l.cust5 custom instructions ***
495
//
496
                default: begin
497
                        result_cust5 = a;
498
                end
499
        endcase
500
end // always @ (cust5_op or cust5_limm or a or b)
501
`endif
502
 
503 10 unneback
endmodule

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