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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's ALU                                                ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/project,or1k                       ////
////                                                              ////
////  Description                                                 ////
////  ALU                                                         ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// $Log: or1200_alu.v,v $
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Minor update: 
// Defines added, flags are corrected. 
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_alu(
        a, b, mult_mac_result, macrc_op,
        alu_op, alu_op2, comp_op,
        cust5_op, cust5_limm,
        result, flagforw, flag_we,
        cyforw, cy_we, carry, flag
);
 
parameter width = `OR1200_OPERAND_WIDTH;
 
//
// I/O
//
input   [width-1:0]              a;
input   [width-1:0]              b;
input   [width-1:0]              mult_mac_result;
input                           macrc_op;
input   [`OR1200_ALUOP_WIDTH-1:0]        alu_op;
input   [`OR1200_ALUOP2_WIDTH-1:0]       alu_op2;
input   [`OR1200_COMPOP_WIDTH-1:0]       comp_op;
input   [4:0]                    cust5_op;
input   [5:0]                    cust5_limm;
output  [width-1:0]              result;
output                          flagforw;
output                          flag_we;
output                          cyforw;
output                          cy_we;
input                           carry;
input         flag;
 
//
// Internal wires and regs
//
reg     [width-1:0]              result;
reg     [width-1:0]              shifted_rotated;
reg     [width-1:0]              extended;
reg     [width-1:0]              result_cust5;
reg                             flagforw;
reg                             flagcomp;
reg                             flag_we;
reg                             cy_we;
wire    [width-1:0]              comp_a;
wire    [width-1:0]              comp_b;
`ifdef OR1200_IMPL_ALU_COMP1
wire                            a_eq_b;
wire                            a_lt_b;
`endif
wire    [width-1:0]              result_sum;
`ifdef OR1200_IMPL_ADDC
wire    [width-1:0]              result_csum;
wire                            cy_csum;
`endif
wire    [width-1:0]              result_and;
wire                            cy_sum;
`ifdef OR1200_IMPL_SUB
wire                            cy_sub;
`endif
reg                             cyforw;
 
//
// Combinatorial logic
//
assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};
assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};
`ifdef OR1200_IMPL_ALU_COMP1
assign a_eq_b = (comp_a == comp_b);
assign a_lt_b = (comp_a < comp_b);
`endif
`ifdef OR1200_IMPL_SUB
assign cy_sub = a < b;
`endif
assign {cy_sum, result_sum} = a + b;
`ifdef OR1200_IMPL_ADDC
assign {cy_csum, result_csum} = a + b + {`OR1200_OPERAND_WIDTH'd0, carry};
`endif
assign result_and = a & b;
 
//
// Simulation check for bad ALU behavior
//
`ifdef OR1200_WARNINGS
// synopsys translate_off
always @(result) begin
        if (result === 32'bx)
                $display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);
end
// synopsys translate_on
`endif
 
//
// Central part of the ALU
//
always @(alu_op or alu_op2 or a or b or result_sum or result_and or macrc_op
         or shifted_rotated or mult_mac_result or flag or result_cust5 or carry
`ifdef OR1200_IMPL_ADDC
         or result_csum
`endif
`ifdef OR1200_IMPL_ALU_EXT
         or extended
`endif
) begin
`ifdef OR1200_CASE_DEFAULT
        casez (alu_op)          // synopsys parallel_case
`else
        casez (alu_op)          // synopsys full_case parallel_case
`endif
`ifdef OR1200_IMPL_ALU_FFL1
                `OR1200_ALUOP_FFL1: begin
`ifdef OR1200_CASE_DEFAULT
                   casez (alu_op2) // synopsys parallel_case
`else
                   casez (alu_op2) // synopsys full_case parallel_case
`endif
                     0: begin // FF1
                        result = a[0] ? 1 : a[1] ? 2 : a[2] ? 3 : a[3] ? 4 : a[4] ? 5 : a[5] ? 6 : a[6] ? 7 : a[7] ? 8 : a[8] ? 9 : a[9] ? 10 : a[10] ? 11 : a[11] ? 12 : a[12] ? 13 : a[13] ? 14 : a[14] ? 15 : a[15] ? 16 : a[16] ? 17 : a[17] ? 18 : a[18] ? 19 : a[19] ? 20 : a[20] ? 21 : a[21] ? 22 : a[22] ? 23 : a[23] ? 24 : a[24] ? 25 : a[25] ? 26 : a[26] ? 27 : a[27] ? 28 : a[28] ? 29 : a[29] ? 30 : a[30] ? 31 : a[31] ? 32 : 0;
                     end
                     default: begin // FL1
                        result = a[31] ? 32 : a[30] ? 31 : a[29] ? 30 : a[28] ? 29 : a[27] ? 28 : a[26] ? 27 : a[25] ? 26 : a[24] ? 25 : a[23] ? 24 : a[22] ? 23 : a[21] ? 22 : a[20] ? 21 : a[19] ? 20 : a[18] ? 19 : a[17] ? 18 : a[16] ? 17 : a[15] ? 16 : a[14] ? 15 : a[13] ? 14 : a[12] ? 13 : a[11] ? 12 : a[10] ? 11 : a[9] ? 10 : a[8] ? 9 : a[7] ? 8 : a[6] ? 7 : a[5] ? 6 : a[4] ? 5 : a[3] ? 4 : a[2] ? 3 : a[1] ? 2 : a[0] ? 1 : 0 ;
                     end
                   endcase // casez (alu_op2)
                end // case: `OR1200_ALUOP_FFL1
`endif //  `ifdef OR1200_IMPL_ALU_FFL1
`ifdef OR1200_IMPL_ALU_CUST5
 
                `OR1200_ALUOP_CUST5 : begin
                                result = result_cust5;
                end
`endif
                `OR1200_ALUOP_SHROT : begin
                                result = shifted_rotated;
                end
                `OR1200_ALUOP_ADD : begin
                                result = result_sum;
                end
`ifdef OR1200_IMPL_ADDC
                `OR1200_ALUOP_ADDC : begin
                                result = result_csum;
                end
`endif
`ifdef OR1200_IMPL_SUB
                `OR1200_ALUOP_SUB : begin
                                result = a - b;
                end
`endif
                `OR1200_ALUOP_XOR : begin
                                result = a ^ b;
                end
                `OR1200_ALUOP_OR  : begin
                                result = a | b;
                end
`ifdef OR1200_IMPL_ALU_EXT
                `OR1200_ALUOP_EXTHB  : begin
                                result = extended;
                end
                `OR1200_ALUOP_EXTW  : begin
                                result = extended;
                end
`endif
                `OR1200_ALUOP_MOVHI : begin
                                if (macrc_op) begin
                                        result = mult_mac_result;
                                end
                                else begin
                                        result = b << 16;
                                end
                end
`ifdef OR1200_MULT_IMPLEMENTED
`ifdef OR1200_DIV_IMPLEMENTED
                `OR1200_ALUOP_DIV,
                `OR1200_ALUOP_DIVU,
`endif
                `OR1200_ALUOP_MUL,
                `OR1200_ALUOP_MULU : begin
                                result = mult_mac_result;
                end
`endif
                `OR1200_ALUOP_CMOV: begin
                        result = flag ? a : b;
                end
 
`ifdef OR1200_CASE_DEFAULT
                default: begin
`else
                `OR1200_ALUOP_COMP, `OR1200_ALUOP_AND: begin
`endif
                        result=result_and;
                end
        endcase
end
 
//
// Generate flag and flag write enable
//
always @(alu_op or result_sum or result_and or flagcomp
`ifdef OR1200_IMPL_ADDC
         or result_csum
`endif
) begin
        casez (alu_op)          // synopsys parallel_case
`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
                `OR1200_ALUOP_ADD : begin
                        flagforw = (result_sum == 32'h0000_0000);
                        flag_we = 1'b1;
                end
`ifdef OR1200_IMPL_ADDC
                `OR1200_ALUOP_ADDC : begin
                        flagforw = (result_csum == 32'h0000_0000);
                        flag_we = 1'b1;
                end
`endif
                `OR1200_ALUOP_AND: begin
                        flagforw = (result_and == 32'h0000_0000);
                        flag_we = 1'b1;
                end
`endif
                `OR1200_ALUOP_COMP: begin
                        flagforw = flagcomp;
                        flag_we = 1'b1;
                end
                default: begin
                        flagforw = flagcomp;
                        flag_we = 1'b0;
                end
        endcase
end
 
//
// Generate SR[CY] write enable
//
always @(alu_op or cy_sum
`ifdef OR1200_IMPL_CY
`ifdef OR1200_IMPL_ADDC
        or cy_csum
`endif
`ifdef OR1200_IMPL_SUB
        or cy_sub
`endif
`endif
) begin
        casez (alu_op)          // synopsys parallel_case
`ifdef OR1200_IMPL_CY
                `OR1200_ALUOP_ADD : begin
                        cyforw = cy_sum;
                        cy_we = 1'b1;
                end
`ifdef OR1200_IMPL_ADDC
                `OR1200_ALUOP_ADDC: begin
                        cyforw = cy_csum;
                        cy_we = 1'b1;
                end
`endif
`ifdef OR1200_IMPL_SUB
                `OR1200_ALUOP_SUB: begin
                        cyforw = cy_sub;
                        cy_we = 1'b1;
                end
`endif
`endif
                default: begin
                        cyforw = 1'b0;
                        cy_we = 1'b0;
                end
        endcase
end
 
//
// Shifts and rotation
//
always @(alu_op2 or a or b) begin
        case (alu_op2)          // synopsys parallel_case
          `OR1200_SHROTOP_SLL :
                                shifted_rotated = (a << b[4:0]);
          `OR1200_SHROTOP_SRL :
                                shifted_rotated = (a >> b[4:0]);
 
`ifdef OR1200_IMPL_ALU_ROTATE
          `OR1200_SHROTOP_ROR :
                                shifted_rotated = (a << (6'd32-{1'b0,b[4:0]})) |
                                                  (a >> b[4:0]);
`endif
          default:
                                shifted_rotated = ({32{a[31]}} <<
                                                   (6'd32-{1'b0, b[4:0]})) |
                                                  a >> b[4:0];
        endcase
end
 
//
// First type of compare implementation
//
`ifdef OR1200_IMPL_ALU_COMP1
always @(comp_op or a_eq_b or a_lt_b) begin
        case(comp_op[2:0])       // synopsys parallel_case
                `OR1200_COP_SFEQ:
                        flagcomp = a_eq_b;
                `OR1200_COP_SFNE:
                        flagcomp = ~a_eq_b;
                `OR1200_COP_SFGT:
                        flagcomp = ~(a_eq_b | a_lt_b);
                `OR1200_COP_SFGE:
                        flagcomp = ~a_lt_b;
                `OR1200_COP_SFLT:
                        flagcomp = a_lt_b;
                `OR1200_COP_SFLE:
                        flagcomp = a_eq_b | a_lt_b;
                default:
                        flagcomp = 1'b0;
        endcase
end
`endif
 
//
// Second type of compare implementation
//
`ifdef OR1200_IMPL_ALU_COMP2
always @(comp_op or comp_a or comp_b) begin
        case(comp_op[2:0])       // synopsys parallel_case
                `OR1200_COP_SFEQ:
                        flagcomp = (comp_a == comp_b);
                `OR1200_COP_SFNE:
                        flagcomp = (comp_a != comp_b);
                `OR1200_COP_SFGT:
                        flagcomp = (comp_a > comp_b);
                `OR1200_COP_SFGE:
                        flagcomp = (comp_a >= comp_b);
                `OR1200_COP_SFLT:
                        flagcomp = (comp_a < comp_b);
                `OR1200_COP_SFLE:
                        flagcomp = (comp_a <= comp_b);
                default:
                        flagcomp = 1'b0;
        endcase
end
`endif
 
`ifdef OR1200_IMPL_ALU_EXT
   always @(alu_op or alu_op2 or a) begin
      casez (alu_op2)
        `OR1200_EXTHBOP_HS : extended = {{16{a[15]}},a[15:0]};
        `OR1200_EXTHBOP_BS : extended = {{24{a[7]}},a[7:0]};
        `OR1200_EXTHBOP_HZ : extended = {16'd0,a[15:0]};
        `OR1200_EXTHBOP_BZ : extended = {24'd0,a[7:0]};
        default: extended = a; // Used for l.extw instructions
      endcase // casez (alu_op2)
   end
`endif
 
 
//
// l.cust5 custom instructions
//
`ifdef OR1200_IMPL_ALU_CUST5
// Examples for move byte, set bit and clear bit
//
always @(cust5_op or cust5_limm or a or b) begin
        casez (cust5_op)                // synopsys parallel_case
                5'h1 : begin
                        casez (cust5_limm[1:0])
                          2'h0: result_cust5 = {a[31:8], b[7:0]};
                          2'h1: result_cust5 = {a[31:16], b[7:0], a[7:0]};
                          2'h2: result_cust5 = {a[31:24], b[7:0], a[15:0]};
                          2'h3: result_cust5 = {b[7:0], a[23:0]};
                        endcase
                end
                5'h2 :
                        result_cust5 = a | (1 << cust5_limm);
                5'h3 :
                        result_cust5 = a & (32'hffffffff ^ (1 << cust5_limm));
//
// *** Put here new l.cust5 custom instructions ***
//
                default: begin
                        result_cust5 = a;
                end
        endcase
end // always @ (cust5_op or cust5_limm or a or b)
`endif
 
endmodule

Line No.	Rev	Author	Line
1	10	unneback	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's ALU ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6	185	julius	`//// http://www.opencores.org/project,or1k ////`
7	10	unneback	`//// ////`
8			`//// Description ////`
9			`//// ALU ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44	141	marcus.erl	`// $Log: or1200_alu.v,v $`
45			`// Revision 2.0 2010/06/30 11:00:00 ORSoC`
46			`// Minor update:`
47			`// Defines added, flags are corrected.`
48	10	unneback
49			`// synopsys translate_off`
50			`include "timescale.v"
51			`// synopsys translate_on`
52			`include "or1200_defines.v"
53
54			`module or1200_alu(`
55			`a, b, mult_mac_result, macrc_op,`
56	640	julius	`alu_op, alu_op2, comp_op,`
57	10	unneback	`cust5_op, cust5_limm,`
58			`result, flagforw, flag_we,`
59			`cyforw, cy_we, carry, flag`
60			`);`
61
62			parameter width = `OR1200_OPERAND_WIDTH;
63
64			`//`
65			`// I/O`
66			`//`
67			`input [width-1:0] a;`
68			`input [width-1:0] b;`
69			`input [width-1:0] mult_mac_result;`
70			`input macrc_op;`
71			input [`OR1200_ALUOP_WIDTH-1:0] alu_op;
72	401	julius	input [`OR1200_ALUOP2_WIDTH-1:0] alu_op2;
73	10	unneback	input [`OR1200_COMPOP_WIDTH-1:0] comp_op;
74			`input [4:0] cust5_op;`
75			`input [5:0] cust5_limm;`
76			`output [width-1:0] result;`
77			`output flagforw;`
78			`output flag_we;`
79			`output cyforw;`
80			`output cy_we;`
81			`input carry;`
82			`input flag;`
83
84			`//`
85			`// Internal wires and regs`
86			`//`
87			`reg [width-1:0] result;`
88			`reg [width-1:0] shifted_rotated;`
89	640	julius	`reg [width-1:0] extended;`
90	10	unneback	`reg [width-1:0] result_cust5;`
91			`reg flagforw;`
92			`reg flagcomp;`
93			`reg flag_we;`
94			`reg cy_we;`
95			`wire [width-1:0] comp_a;`
96			`wire [width-1:0] comp_b;`
97			`ifdef OR1200_IMPL_ALU_COMP1
98			`wire a_eq_b;`
99			`wire a_lt_b;`
100			`endif
101			`wire [width-1:0] result_sum;`
102			`ifdef OR1200_IMPL_ADDC
103			`wire [width-1:0] result_csum;`
104			`wire cy_csum;`
105			`endif
106			`wire [width-1:0] result_and;`
107			`wire cy_sum;`
108	141	marcus.erl	`ifdef OR1200_IMPL_SUB
109			`wire cy_sub;`
110			`endif
111	10	unneback	`reg cyforw;`
112
113			`//`
114			`// Combinatorial logic`
115			`//`
116			`assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};`
117			`assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};`
118			`ifdef OR1200_IMPL_ALU_COMP1
119			`assign a_eq_b = (comp_a == comp_b);`
120			`assign a_lt_b = (comp_a < comp_b);`
121			`endif
122	141	marcus.erl	`ifdef OR1200_IMPL_SUB
123			`assign cy_sub = a < b;`
124			`endif
125	10	unneback	`assign {cy_sum, result_sum} = a + b;`
126			`ifdef OR1200_IMPL_ADDC
127	141	marcus.erl	assign {cy_csum, result_csum} = a + b + {`OR1200_OPERAND_WIDTH'd0, carry};
128	10	unneback	`endif
129			`assign result_and = a & b;`
130
131			`//`
132			`// Simulation check for bad ALU behavior`
133			`//`
134			`ifdef OR1200_WARNINGS
135			`// synopsys translate_off`
136			`always @(result) begin`
137			`if (result === 32'bx)`
138			`$display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);`
139			`end`
140			`// synopsys translate_on`
141			`endif
142
143			`//`
144			`// Central part of the ALU`
145			`//`
146	401	julius	`always @(alu_op or alu_op2 or a or b or result_sum or result_and or macrc_op`
147			`or shifted_rotated or mult_mac_result or flag or result_cust5 or carry`
148	141	marcus.erl	`ifdef OR1200_IMPL_ADDC
149			`or result_csum`
150			`endif
151	640	julius	`ifdef OR1200_IMPL_ALU_EXT
152			`or extended`
153			`endif
154	141	marcus.erl	`) begin`
155	10	unneback	`ifdef OR1200_CASE_DEFAULT
156	364	julius	`casez (alu_op) // synopsys parallel_case`
157	10	unneback	`else
158	364	julius	`casez (alu_op) // synopsys full_case parallel_case`
159	10	unneback	`endif
160	401	julius	`ifdef OR1200_IMPL_ALU_FFL1
161			`OR1200_ALUOP_FFL1: begin
162			`ifdef OR1200_CASE_DEFAULT
163			`casez (alu_op2) // synopsys parallel_case`
164			`else
165			`casez (alu_op2) // synopsys full_case parallel_case`
166			`endif
167			`0: begin // FF1`
168	141	marcus.erl	`result = a[0] ? 1 : a[1] ? 2 : a[2] ? 3 : a[3] ? 4 : a[4] ? 5 : a[5] ? 6 : a[6] ? 7 : a[7] ? 8 : a[8] ? 9 : a[9] ? 10 : a[10] ? 11 : a[11] ? 12 : a[12] ? 13 : a[13] ? 14 : a[14] ? 15 : a[15] ? 16 : a[16] ? 17 : a[17] ? 18 : a[18] ? 19 : a[19] ? 20 : a[20] ? 21 : a[21] ? 22 : a[22] ? 23 : a[23] ? 24 : a[24] ? 25 : a[25] ? 26 : a[26] ? 27 : a[27] ? 28 : a[28] ? 29 : a[29] ? 30 : a[30] ? 31 : a[31] ? 32 : 0;`
169	401	julius	`end`
170			`default: begin // FL1`
171			`result = a[31] ? 32 : a[30] ? 31 : a[29] ? 30 : a[28] ? 29 : a[27] ? 28 : a[26] ? 27 : a[25] ? 26 : a[24] ? 25 : a[23] ? 24 : a[22] ? 23 : a[21] ? 22 : a[20] ? 21 : a[19] ? 20 : a[18] ? 19 : a[17] ? 18 : a[16] ? 17 : a[15] ? 16 : a[14] ? 15 : a[13] ? 14 : a[12] ? 13 : a[11] ? 12 : a[10] ? 11 : a[9] ? 10 : a[8] ? 9 : a[7] ? 8 : a[6] ? 7 : a[5] ? 6 : a[4] ? 5 : a[3] ? 4 : a[2] ? 3 : a[1] ? 2 : a[0] ? 1 : 0 ;`
172			`end`
173			`endcase // casez (alu_op2)`
174			end // case: `OR1200_ALUOP_FFL1
175	640	julius	`endif // `ifdef OR1200_IMPL_ALU_FFL1
176			`ifdef OR1200_IMPL_ALU_CUST5
177
178	10	unneback	`OR1200_ALUOP_CUST5 : begin
179			`result = result_cust5;`
180			`end`
181	640	julius	`endif
182	10	unneback	`OR1200_ALUOP_SHROT : begin
183			`result = shifted_rotated;`
184			`end`
185			`OR1200_ALUOP_ADD : begin
186			`result = result_sum;`
187			`end`
188			`ifdef OR1200_IMPL_ADDC
189			`OR1200_ALUOP_ADDC : begin
190			`result = result_csum;`
191			`end`
192			`endif
193	141	marcus.erl	`ifdef OR1200_IMPL_SUB
194	10	unneback	`OR1200_ALUOP_SUB : begin
195			`result = a - b;`
196			`end`
197	141	marcus.erl	`endif
198	10	unneback	`OR1200_ALUOP_XOR : begin
199			`result = a ^ b;`
200			`end`
201			`OR1200_ALUOP_OR : begin
202			`result = a \| b;`
203			`end`
204	640	julius	`ifdef OR1200_IMPL_ALU_EXT
205			`OR1200_ALUOP_EXTHB : begin
206			`result = extended;`
207			`end`
208			`OR1200_ALUOP_EXTW : begin
209			`result = extended;`
210			`end`
211			`endif
212	10	unneback	`OR1200_ALUOP_MOVHI : begin
213			`if (macrc_op) begin`
214			`result = mult_mac_result;`
215			`end`
216			`else begin`
217			`result = b << 16;`
218			`end`
219			`end`
220			`ifdef OR1200_MULT_IMPLEMENTED
221	258	julius	`ifdef OR1200_DIV_IMPLEMENTED
222	10	unneback	`OR1200_ALUOP_DIV,
223			`OR1200_ALUOP_DIVU,
224			`endif
225	481	julius	`OR1200_ALUOP_MUL,
226			`OR1200_ALUOP_MULU : begin
227	10	unneback	`result = mult_mac_result;`
228			`end`
229			`endif
230	141	marcus.erl	`OR1200_ALUOP_CMOV: begin
231			`result = flag ? a : b;`
232			`end`
233	10	unneback
234			`ifdef OR1200_CASE_DEFAULT
235	141	marcus.erl	`default: begin`
236	10	unneback	`else
237	141	marcus.erl	`OR1200_ALUOP_COMP, `OR1200_ALUOP_AND: begin
238	10	unneback	`endif
239	141	marcus.erl	`result=result_and;`
240			`end`
241	10	unneback	`endcase`
242			`end`
243
244			`//`
245			`// Generate flag and flag write enable`
246			`//`
247	141	marcus.erl	`always @(alu_op or result_sum or result_and or flagcomp`
248			`ifdef OR1200_IMPL_ADDC
249			`or result_csum`
250			`endif
251			`) begin`
252	364	julius	`casez (alu_op) // synopsys parallel_case`
253	10	unneback	`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
254			`OR1200_ALUOP_ADD : begin
255			`flagforw = (result_sum == 32'h0000_0000);`
256			`flag_we = 1'b1;`
257			`end`
258			`ifdef OR1200_IMPL_ADDC
259			`OR1200_ALUOP_ADDC : begin
260			`flagforw = (result_csum == 32'h0000_0000);`
261			`flag_we = 1'b1;`
262			`end`
263			`endif
264			`OR1200_ALUOP_AND: begin
265			`flagforw = (result_and == 32'h0000_0000);`
266			`flag_we = 1'b1;`
267			`end`
268			`endif
269			`OR1200_ALUOP_COMP: begin
270			`flagforw = flagcomp;`
271			`flag_we = 1'b1;`
272			`end`
273			`default: begin`
274	141	marcus.erl	`flagforw = flagcomp;`
275	10	unneback	`flag_we = 1'b0;`
276			`end`
277			`endcase`
278			`end`
279
280			`//`
281			`// Generate SR[CY] write enable`
282			`//`
283			`always @(alu_op or cy_sum`
284	141	marcus.erl	`ifdef OR1200_IMPL_CY
285	10	unneback	`ifdef OR1200_IMPL_ADDC
286			`or cy_csum`
287			`endif
288	141	marcus.erl	`ifdef OR1200_IMPL_SUB
289			`or cy_sub`
290			`endif
291			`endif
292			`) begin`
293	364	julius	`casez (alu_op) // synopsys parallel_case`
294	10	unneback	`ifdef OR1200_IMPL_CY
295			`OR1200_ALUOP_ADD : begin
296			`cyforw = cy_sum;`
297			`cy_we = 1'b1;`
298			`end`
299			`ifdef OR1200_IMPL_ADDC
300			`OR1200_ALUOP_ADDC: begin
301			`cyforw = cy_csum;`
302			`cy_we = 1'b1;`
303			`end`
304			`endif
305	141	marcus.erl	`ifdef OR1200_IMPL_SUB
306			`OR1200_ALUOP_SUB: begin
307			`cyforw = cy_sub;`
308			`cy_we = 1'b1;`
309			`end`
310	10	unneback	`endif
311	141	marcus.erl	`endif
312	10	unneback	`default: begin`
313			`cyforw = 1'b0;`
314			`cy_we = 1'b0;`
315			`end`
316			`endcase`
317			`end`
318
319			`//`
320			`// Shifts and rotation`
321			`//`
322	640	julius	`always @(alu_op2 or a or b) begin`
323			`case (alu_op2) // synopsys parallel_case`
324			`OR1200_SHROTOP_SLL :
325	10	unneback	`shifted_rotated = (a << b[4:0]);`
326	640	julius	`OR1200_SHROTOP_SRL :
327	10	unneback	`shifted_rotated = (a >> b[4:0]);`
328
329			`ifdef OR1200_IMPL_ALU_ROTATE
330	640	julius	`OR1200_SHROTOP_ROR :
331			`shifted_rotated = (a << (6'd32-{1'b0,b[4:0]})) \|`
332			`(a >> b[4:0]);`
333	10	unneback	`endif
334	640	julius	`default:`
335			`shifted_rotated = ({32{a[31]}} <<`
336			`(6'd32-{1'b0, b[4:0]})) \|`
337			`a >> b[4:0];`
338	10	unneback	`endcase`
339			`end`
340
341			`//`
342			`// First type of compare implementation`
343			`//`
344			`ifdef OR1200_IMPL_ALU_COMP1
345			`always @(comp_op or a_eq_b or a_lt_b) begin`
346			`case(comp_op[2:0]) // synopsys parallel_case`
347			`OR1200_COP_SFEQ:
348			`flagcomp = a_eq_b;`
349			`OR1200_COP_SFNE:
350			`flagcomp = ~a_eq_b;`
351			`OR1200_COP_SFGT:
352			`flagcomp = ~(a_eq_b \| a_lt_b);`
353			`OR1200_COP_SFGE:
354			`flagcomp = ~a_lt_b;`
355			`OR1200_COP_SFLT:
356			`flagcomp = a_lt_b;`
357			`OR1200_COP_SFLE:
358			`flagcomp = a_eq_b \| a_lt_b;`
359			`default:`
360			`flagcomp = 1'b0;`
361			`endcase`
362			`end`
363			`endif
364
365			`//`
366			`// Second type of compare implementation`
367			`//`
368			`ifdef OR1200_IMPL_ALU_COMP2
369			`always @(comp_op or comp_a or comp_b) begin`
370			`case(comp_op[2:0]) // synopsys parallel_case`
371			`OR1200_COP_SFEQ:
372			`flagcomp = (comp_a == comp_b);`
373			`OR1200_COP_SFNE:
374			`flagcomp = (comp_a != comp_b);`
375			`OR1200_COP_SFGT:
376			`flagcomp = (comp_a > comp_b);`
377			`OR1200_COP_SFGE:
378			`flagcomp = (comp_a >= comp_b);`
379			`OR1200_COP_SFLT:
380			`flagcomp = (comp_a < comp_b);`
381			`OR1200_COP_SFLE:
382			`flagcomp = (comp_a <= comp_b);`
383			`default:`
384			`flagcomp = 1'b0;`
385			`endcase`
386			`end`
387			`endif
388
389	640	julius	`ifdef OR1200_IMPL_ALU_EXT
390			`always @(alu_op or alu_op2 or a) begin`
391			`casez (alu_op2)`
392			`OR1200_EXTHBOP_HS : extended = {{16{a[15]}},a[15:0]};
393			`OR1200_EXTHBOP_BS : extended = {{24{a[7]}},a[7:0]};
394			`OR1200_EXTHBOP_HZ : extended = {16'd0,a[15:0]};
395			`OR1200_EXTHBOP_BZ : extended = {24'd0,a[7:0]};
396			`default: extended = a; // Used for l.extw instructions`
397			`endcase // casez (alu_op2)`
398			`end`
399			`endif
400
401
402			`//`
403			`// l.cust5 custom instructions`
404			`//`
405			`ifdef OR1200_IMPL_ALU_CUST5
406			`// Examples for move byte, set bit and clear bit`
407			`//`
408			`always @(cust5_op or cust5_limm or a or b) begin`
409			`casez (cust5_op) // synopsys parallel_case`
410			`5'h1 : begin`
411			`casez (cust5_limm[1:0])`
412			`2'h0: result_cust5 = {a[31:8], b[7:0]};`
413			`2'h1: result_cust5 = {a[31:16], b[7:0], a[7:0]};`
414			`2'h2: result_cust5 = {a[31:24], b[7:0], a[15:0]};`
415			`2'h3: result_cust5 = {b[7:0], a[23:0]};`
416			`endcase`
417			`end`
418			`5'h2 :`
419			`result_cust5 = a \| (1 << cust5_limm);`
420			`5'h3 :`
421			`result_cust5 = a & (32'hffffffff ^ (1 << cust5_limm));`
422			`//`
423			`// * Put here new l.cust5 custom instructions *`
424			`//`
425			`default: begin`
426			`result_cust5 = a;`
427			`end`
428			`endcase`
429			`end // always @ (cust5_op or cust5_limm or a or b)`
430			`endif
431
432	10	unneback	`endmodule`

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