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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_fpu_intfloat_conv_except.v] - Blame information for rev 794

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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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////  or1200_fpu_intfloat_conv_except                            ////
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////                                                             ////
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////  Author: Rudolf Usselmann                                   ////
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////          rudi@asics.ws                                      ////
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////                                                             ////
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//// Modified by Julius Baxter, July, 2010                       ////
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////             julius.baxter@orsoc.se                          ////
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////                                                             ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2000 Rudolf Usselmann                         ////
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////                    rudi@asics.ws                            ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
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//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
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//// POSSIBILITY OF SUCH DAMAGE.                                 ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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`timescale 1ns / 100ps
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module or1200_fpu_intfloat_conv_except
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  (
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        clk, opa, opb, inf, ind, qnan, snan, opa_nan, opb_nan,
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        opa_00, opb_00, opa_inf, opb_inf, opa_dn, opb_dn
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        );
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   input                clk;
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   input [31:0]  opa, opb;
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   output               inf, ind, qnan, snan, opa_nan, opb_nan;
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   output               opa_00, opb_00;
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   output               opa_inf, opb_inf;
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   output               opa_dn;
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   output               opb_dn;
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   ////////////////////////////////////////////////////////////////////////
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   //
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   // Local Wires and registers
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   //
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   wire [7:0]            expa, expb;             // alias to opX exponent
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   wire [22:0]           fracta, fractb;         // alias to opX fraction
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   reg                  expa_ff, infa_f_r, qnan_r_a, snan_r_a;
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   reg                  expb_ff, infb_f_r, qnan_r_b, snan_r_b;
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   reg                  inf, ind, qnan, snan;   // Output registers
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   reg                  opa_nan, opb_nan;
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   reg                  expa_00, expb_00, fracta_00, fractb_00;
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   reg                  opa_00, opb_00;
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   reg                  opa_inf, opb_inf;
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   reg                  opa_dn, opb_dn;
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   ////////////////////////////////////////////////////////////////////////
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   //
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   // Aliases
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   //
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   assign   expa = opa[30:23];
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   assign   expb = opb[30:23];
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   assign fracta = opa[22:0];
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   assign fractb = opb[22:0];
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   ////////////////////////////////////////////////////////////////////////
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   //
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   // Determine if any of the input operators is a INF or NAN or any other 
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   // special number
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   //
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   always @(posedge clk)
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     expa_ff <=  &expa;
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   always @(posedge clk)
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     expb_ff <=  &expb;
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   always @(posedge clk)
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     infa_f_r <=  !(|fracta);
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   always @(posedge clk)
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     infb_f_r <=  !(|fractb);
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   always @(posedge clk)
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     qnan_r_a <=   fracta[22];
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   always @(posedge clk)
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     snan_r_a <=  !fracta[22] & |fracta[21:0];
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   always @(posedge clk)
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     qnan_r_b <=   fractb[22];
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   always @(posedge clk)
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     snan_r_b <=  !fractb[22]; // & |fractb[21:0];
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   always @(posedge clk)
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     ind  <=  (expa_ff & infa_f_r); // & (expb_ff & infb_f_r);
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   always @(posedge clk)
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     inf  <=  (expa_ff & infa_f_r); // | (expb_ff & infb_f_r);
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   always @(posedge clk)
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     qnan <=  (expa_ff & qnan_r_a); // | (expb_ff & qnan_r_b);
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   always @(posedge clk)
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     snan <=  (expa_ff & snan_r_a); // | (expb_ff & snan_r_b);
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   always @(posedge clk)
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     opa_nan <=  &expa & (|fracta[22:0]);
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   always @(posedge clk)
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     opb_nan <=  &expb & (|fractb[22:0]);
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   always @(posedge clk)
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     opa_inf <=  (expa_ff & infa_f_r);
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   always @(posedge clk)
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     opb_inf <=  (expb_ff & infb_f_r);
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   always @(posedge clk)
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     expa_00 <=  !(|expa);
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   always @(posedge clk)
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     expb_00 <=  !(|expb);
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   always @(posedge clk)
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     fracta_00 <=  !(|fracta);
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   always @(posedge clk)
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     fractb_00 <=  !(|fractb);
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   always @(posedge clk)
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     opa_00 <=  expa_00 & fracta_00;
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   always @(posedge clk)
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     opb_00 <=  expb_00 & fractb_00;
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   always @(posedge clk)
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     opa_dn <=  expa_00;
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   always @(posedge clk)
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     opb_dn <=  expb_00;
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endmodule // or1200_fpu_intfloat_conv_except

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