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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_freeze.v] - Blame information for rev 640

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  OR1200's Freeze logic                                       ////
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////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
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////  http://www.opencores.org/project,or1k                       ////
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////                                                              ////
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////  Description                                                 ////
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////  Generates all freezes and stalls inside RISC                ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - make it smaller and faster                               ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
44 141 marcus.erl
// $Log: or1200_freeze.v,v $
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// Revision 2.0  2010/06/30 11:00:00  ORSoC
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// Minor update: 
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// Bugs fixed. 
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "or1200_defines.v"
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`define OR1200_NO_FREEZE        3'd0
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`define OR1200_FREEZE_BYDC      3'd1
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`define OR1200_FREEZE_BYMULTICYCLE      3'd2
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`define OR1200_WAIT_LSU_TO_FINISH       3'd3
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`define OR1200_WAIT_IC                  3'd4
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//
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// Freeze logic (stalls CPU pipeline, ifetcher etc.)
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//
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module or1200_freeze
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  (
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   // Clock and reset
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   clk, rst,
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   // Internal i/f
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   multicycle, wait_on, flushpipe, extend_flush, lsu_stall, if_stall,
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   lsu_unstall, du_stall, mac_stall,
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   force_dslot_fetch, abort_ex,
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   genpc_freeze, if_freeze, id_freeze, ex_freeze, wb_freeze, saving_if_insn,
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   fpu_done, mtspr_done,
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   icpu_ack_i, icpu_err_i
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   );
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//
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// I/O
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//
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input                           clk;
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input                           rst;
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input   [`OR1200_MULTICYCLE_WIDTH-1:0]   multicycle;
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input   [`OR1200_WAIT_ON_WIDTH-1:0]      wait_on;
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input                           flushpipe;
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input                           extend_flush;
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input                           lsu_stall;
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input                           if_stall;
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input                           lsu_unstall;
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input                           force_dslot_fetch;
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input                           abort_ex;
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input                           du_stall;
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input                           mac_stall;
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output                          genpc_freeze;
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output                          if_freeze;
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output                          id_freeze;
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output                          ex_freeze;
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output                          wb_freeze;
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input                           saving_if_insn;
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input                           fpu_done;
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input                           mtspr_done;
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input                           icpu_ack_i;
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input                           icpu_err_i;
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//
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// Internal wires and regs
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//
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wire                            multicycle_freeze;
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reg     [`OR1200_MULTICYCLE_WIDTH-1:0]   multicycle_cnt;
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reg                             flushpipe_r;
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reg [`OR1200_WAIT_ON_WIDTH-1:0]  waiting_on;
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//
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// Pipeline freeze
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//
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// Rules how to create freeze signals:
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// 1. Not overwriting pipeline stages:
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// Freeze signals at the beginning of pipeline (such as if_freeze) can be 
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// asserted more often than freeze signals at the of pipeline (such as 
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// wb_freeze). In other words, wb_freeze must never be asserted when ex_freeze 
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// is not. ex_freeze must never be asserted when id_freeze is not etc.
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//
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// 2. Inserting NOPs in the middle of pipeline only if supported:
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// At this time, only ex_freeze (and wb_freeze) can be deassrted when id_freeze
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// (and if_freeze) are asserted.
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// This way NOP is asserted from stage ID into EX stage.
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//
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129 141 marcus.erl
assign genpc_freeze = (du_stall & !saving_if_insn) | flushpipe_r;
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assign if_freeze = id_freeze | extend_flush;
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assign id_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze
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                    | (|waiting_on) | force_dslot_fetch) | du_stall;
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assign ex_freeze = wb_freeze;
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assign wb_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze
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                    | (|waiting_on)) | du_stall | abort_ex;
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//
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// registered flushpipe
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//
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always @(posedge clk or `OR1200_RST_EVENT rst)
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        if (rst == `OR1200_RST_VALUE)
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                flushpipe_r <=  1'b0;
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        else if (icpu_ack_i | icpu_err_i)
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//      else if (!if_stall)
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                flushpipe_r <=  flushpipe;
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        else if (!flushpipe)
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                flushpipe_r <=  1'b0;
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//
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// Multicycle freeze
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//
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assign multicycle_freeze = |multicycle_cnt;
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//
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// Multicycle counter
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//
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always @(posedge clk or `OR1200_RST_EVENT rst)
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        if (rst == `OR1200_RST_VALUE)
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                multicycle_cnt <=  `OR1200_MULTICYCLE_WIDTH'd0;
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        else if (|multicycle_cnt)
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                multicycle_cnt <=  multicycle_cnt - `OR1200_MULTICYCLE_WIDTH'd1;
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        else if (|multicycle & !ex_freeze)
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                multicycle_cnt <=  multicycle;
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//
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// Waiting on generation
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//
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always @(posedge clk or `OR1200_RST_EVENT rst)
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  if (rst == `OR1200_RST_VALUE)
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    waiting_on <= 0;
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  else if ((waiting_on == `OR1200_WAIT_ON_MULTMAC) & !mac_stall)
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    waiting_on <= 0;
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  else if ((waiting_on == `OR1200_WAIT_ON_FPU) & fpu_done)
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    waiting_on <= 0;
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  else if ((waiting_on == `OR1200_WAIT_ON_MTSPR) & mtspr_done)
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    waiting_on <= 0;
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  else if (!ex_freeze)
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    waiting_on <= wait_on;
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endmodule

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