OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [NEWS] - Blame information for rev 118

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 85 jeremybenn
              Or1ksim: The OpenRISC 1000 Architectural Simulator
2
              ==================================================
3
 
4
 
5 107 jeremybenn
New in top of tree
6
==================
7
 
8
No new features are provided, pending full release of 0.4.0.
9
 
10
The following bugs are fixed.
11
* Bug 1770: l.div does not set carry or give correct exception.
12 114 jeremybenn
* Bug 1771: l.add* do not correctly set the overflow flag.
13 115 jeremybenn
* Bug 1772: l.fl1 not implemented.
14 116 jeremybenn
* Bug 1773: l.maci not correctly implemented.
15 118 jeremybenn
* Bug 1774: l.mulu not implemented.
16 114 jeremybenn
* Bug 1776: l.addic is not implemented.
17 107 jeremybenn
 
18
The following bugs are either cannot be reproduced or will not be fixed.
19
 
20
The following bugs are outstanding
21 114 jeremybenn
* Bug 1758: Memory controller issues. Workaround in the user guide.
22 107 jeremybenn
 
23
 
24 104 jeremybenn
New in release 0.4.0rc1
25
=======================
26 85 jeremybenn
 
27 86 jeremybenn
The following new features are provided.
28 85 jeremybenn
* testbench now renamed testsuite and fully integrated using DejaGNU.
29
  "make check" now works correctly if the OpenRISC toolchain is installed.
30 86 jeremybenn
* New configuration flag --enable-all-tests to enable building of incomplete
31
  tests with "make check".
32 104 jeremybenn
* The library offers an interface via modelled JTAG
33
* Single precision floating point is available.
34 85 jeremybenn
 
35 86 jeremybenn
The user guide is updated.
36
 
37
The following feature requests have been accepted.
38 104 jeremybenn
* Feature  413: ORFPX32 single precision floating point now supported.
39 85 jeremybenn
* Feature  469: Icache tags now intialized as invalid.
40
* Feature 1673: Or1ksim now builds on Mac OS X.
41
* Feature 1678: download, patch and build dirs removed from SVN.
42
 
43 86 jeremybenn
The following feature requests have been rejected.
44 85 jeremybenn
* Feature  399: Writeable SR_LEE bit will not be provided.
45
* Feature  409: Separate ELF loader library already exists in binutils.
46
* Feature  586: Ignoring HW breakpoints is already possible.
47
 
48 89 jeremybenn
The following bugs are fixed.
49
* Bug  534: Test suite fixed (see above).
50
* Bug 1710: mprofile now handles mode args correctly.
51
* Bug 1723: PS2 keyboard error message clearer if RX file won't open.
52 104 jeremybenn
* Bug 1733: Or1ksim now accepts ELF image when working through RSP.
53
* Bug 1767: l.lws is not recognized as an opcode.
54 85 jeremybenn
 
55 89 jeremybenn
The following bugs are either cannot be reproduced or will not be fixed.
56
 
57 104 jeremybenn
The following bugs are outstanding
58
* Bug 1758: Memory controller issues. Workaround in the user guide.
59 89 jeremybenn
 
60 104 jeremybenn
 
61 19 jeremybenn
New in release 0.3.0
62 85 jeremybenn
====================
63
 
64 19 jeremybenn
* No new features or bugs. This is the full release based on rc3.
65
 
66
New in release 0.3.0rc3
67 85 jeremybenn
=======================
68
 
69 19 jeremybenn
* Bug 376 fixed: 32 interrupts now supported
70
* Bug 377 fixed: Level triggered interrupts now work correctly
71
* Bug 378 fixed: xterm UART now works with RSP
72
* Bug 379 fixed: RSP performance improved
73
* Bug 380 fixed: GDB 6.8 stepi now works through Or1ksim JTAG interface
74
* Bug 398 fixed: Lack of support for LEE bit in SR documented
75
* Bug 415 fixed: NPC behavior on writing optionally matches real HW
76
* Bug 418 fixed: All library up calls are host-endian
77
 
78
* Feature 395 added: Boot from 0xf0000000 now enabled.
79
* Feature 408 added: Image file may be NULL for or1ksim_init.
80
* Feature 410 added: RSP now clears sigval on unstalling the processor.
81
* Feature 417 added: Or1ksim prints out its version on startup.
82
 
83
New in release 0.3.0rc2
84 85 jeremybenn
=======================
85
 
86 19 jeremybenn
* A number of bug fixes
87
* Updates to user guide
88
 
89
New in release 0.3.0rc1
90 85 jeremybenn
=======================
91
 
92 19 jeremybenn
* Numerous bug fixes (see the OpenRISC tracker and the ChangeLog file)
93
* User Guide
94
* Consistent coding style and file naming throughout
95
* Support for external SystemC models
96
 
97 85 jeremybenn
New in release 1.9 (old style numbering)
98
========================================
99 19 jeremybenn
 
100
* support for binary COFF
101
* generation of verilog memory models (used when you want to run simulation
102
of OpenRISC processor cores)
103
 
104 85 jeremybenn
New in release 1.2 (old style numbering)
105
========================================
106 19 jeremybenn
 
107
* support for OR16 ISA
108
 
109 85 jeremybenn
New in release 1.1 (old style numbering)
110
========================================
111 19 jeremybenn
 
112
 * First release

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.