OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [NEWS] - Blame information for rev 432

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 85 jeremybenn
              Or1ksim: The OpenRISC 1000 Architectural Simulator
2
              ==================================================
3
 
4
 
5 420 jeremybenn
New in top of tree
6
==================
7
 
8
New features (shouldn't be there during a release cycle, but prompted by debug
9
needs elsewhere in the tool chain).
10
 
11
New option --trace provides a one line dump of instruction executed and any
12
register or memory location changed after each instruction.
13
 
14 432 jeremybenn
A new configuration option "use_nmi" is added to the programmable interrupt
15
controller (PIC). This causes interrupt lines 0 and 1 to be non-maskable, but
16
only in the sense that the corresponding bits in PICMR are hard-wired to 1.
17
 
18 420 jeremybenn
New config setting for memory initialization "exitnops" fills memory with
19
"l.nop 1", which will cause the simulator to exit. Good for tracking pointer
20
corruption.
21
 
22
 
23 385 jeremybenn
New in release 0.5.0rc2
24
=======================
25
 
26
No new features. This is purely bug fixes post-0.5.0rc1.
27
 
28
The following bugs are fixed.
29 420 jeremybenn
* Bug 1847: Build issues with RSP server (duplicate of 1815).
30
* Bug 1846: Casting errors.
31 385 jeremybenn
* Bug 1824: Memory controller issue (marked as duplicate of Bug 1758).
32 420 jeremybenn
* Bug 1816: Error message when target not set is obscure (duplicate of 1813).
33
* Bug 1815: Build errors with RSP server.
34 385 jeremybenn
* Bug 1813: "make check" fails before installation.
35
 
36
The following bugs are outstanding
37
* Bug 1823: Configuration file error line numbers are wrong.
38
* Bug 1822: ATA configuration is broken. Documented in user guide.
39
* Bug 1758: Memory controller issues. Workaround in the user guide.
40
 
41
 
42 346 jeremybenn
New in release 0.5.0rc1
43
=======================
44 143 jeremybenn
 
45 346 jeremybenn
The floating point implementation is now based on John Hauser's "softfloat"
46
package, ensuring rigorous compliance with the IEEE 754-2008 standard.
47
 
48 143 jeremybenn
The library interface is extended to allow registers and memory to be written
49 346 jeremybenn
directly and processor stalled and unstalled. This is to allow direct
50
integration as a simulator in GDB.
51 143 jeremybenn
 
52 346 jeremybenn
Some of the existing library interface functions have different prototypes.
53
 
54 224 jeremybenn
The "include" feature of configuration files (which never worked, but no one
55
ever noticed) is dropped.
56
 
57
If the configuration file is not found in the local directory, it is searched
58
for in the ${HOME}/.or1ksim directory, then (for backwards compatibility) the
59
${HOME}/.or1k directory.
60
 
61 346 jeremybenn
If no simulation file is specified, then sim.cfg is not searched for as a
62
default.
63 224 jeremybenn
 
64 346 jeremybenn
New options are added -q|--quiet, -V|--verbose, -m|--memory and
65
--report-memory-errors. The semantics of --nosrv and --src otpions are changed.
66 224 jeremybenn
 
67 346 jeremybenn
There is a configuration option to collect statistics on instruction execution
68
in binary form.
69
 
70
In previous versions, Bus exceptions were unique in that they produced an
71
error message on standard output. The default is now for this exception to be
72
handled silently, unless requested by --report-memory-errors.
73
 
74
The following feature requests have been accepted.
75
* Feature  393: Integrate Or1ksim in GDB.
76
 
77 143 jeremybenn
The following bugs are fixed.
78 346 jeremybenn
* Bug 1821: Reference configuration file has defective debug section.
79
* Bug 1817: Reference configuration file missing from distribution.
80
* Bug 1795: GDB breakpoints do not work with the instruction cache.
81 143 jeremybenn
 
82 346 jeremybenn
The following bugs are either cannot be reproduced or will not be fixed.
83
 
84
The following bugs are outstanding
85
* Bug 1824: Memory controller issue (probably the same as Bug 1758).
86
* Bug 1823: Configuration file error line numbers are wrong.
87
* Bug 1822: ATA section in configuration file is broken.
88
* Bug 1816: Error message when target not set is obscure.
89
* Bug 1813: "make check" fails before installation.
90
* Bug 1758: Memory controller issues. Workaround in the user guide.
91
 
92
 
93 134 jeremybenn
New in release 0.4.0
94
====================
95
 
96
No new features or bugs. This is the full release based on 0.4.0rc2.
97
 
98
 
99 127 jeremybenn
New in release 0.4.0rc2
100
=======================
101 107 jeremybenn
 
102
No new features are provided, pending full release of 0.4.0.
103
 
104 124 jeremybenn
The configuration options --enable-arith-flag and --enable-ov-flag have been
105
removed, since they were the source of bugs, notably Bugs 1782, 1783 and 1784.
106
 
107 127 jeremybenn
The configuration option --enable-unsigned-xori has been added to allow a
108
conditional solution to Bug 1790.
109
 
110 107 jeremybenn
The following bugs are fixed.
111
* Bug 1770: l.div does not set carry or give correct exception.
112 114 jeremybenn
* Bug 1771: l.add* do not correctly set the overflow flag.
113 115 jeremybenn
* Bug 1772: l.fl1 not implemented.
114 116 jeremybenn
* Bug 1773: l.maci not correctly implemented.
115 118 jeremybenn
* Bug 1774: l.mulu not implemented.
116 121 jeremybenn
* Bug 1775: l.jalr and l.jr don't trigger alignment exceptions.
117 114 jeremybenn
* Bug 1776: l.addic is not implemented.
118 122 jeremybenn
* Bug 1777: l.macrc not correctly implemented.
119
* Bug 1778: l.ror and l.rori are not implemented.
120 123 jeremybenn
* Bug 1779: l.mtspr implementation is incorrect.
121 124 jeremybenn
* Bug 1782: Or1ksim setting of overflow flag is wrong.
122
* Bug 1783: Or1ksim definition of overflow is wrong.
123
* Bug 1784: Or1ksim does not trigger overflow exceptions.
124 127 jeremybenn
* Bug 1790: l.xori implementation is incorrect.
125 107 jeremybenn
 
126
The following bugs are either cannot be reproduced or will not be fixed.
127
 
128
The following bugs are outstanding
129 114 jeremybenn
* Bug 1758: Memory controller issues. Workaround in the user guide.
130 107 jeremybenn
 
131
 
132 104 jeremybenn
New in release 0.4.0rc1
133
=======================
134 85 jeremybenn
 
135 86 jeremybenn
The following new features are provided.
136 85 jeremybenn
* testbench now renamed testsuite and fully integrated using DejaGNU.
137
  "make check" now works correctly if the OpenRISC toolchain is installed.
138 86 jeremybenn
* New configuration flag --enable-all-tests to enable building of incomplete
139
  tests with "make check".
140 104 jeremybenn
* The library offers an interface via modelled JTAG
141
* Single precision floating point is available.
142 85 jeremybenn
 
143 86 jeremybenn
The user guide is updated.
144
 
145
The following feature requests have been accepted.
146 104 jeremybenn
* Feature  413: ORFPX32 single precision floating point now supported.
147 85 jeremybenn
* Feature  469: Icache tags now intialized as invalid.
148
* Feature 1673: Or1ksim now builds on Mac OS X.
149
* Feature 1678: download, patch and build dirs removed from SVN.
150
 
151 86 jeremybenn
The following feature requests have been rejected.
152 85 jeremybenn
* Feature  399: Writeable SR_LEE bit will not be provided.
153
* Feature  409: Separate ELF loader library already exists in binutils.
154
* Feature  586: Ignoring HW breakpoints is already possible.
155
 
156 89 jeremybenn
The following bugs are fixed.
157
* Bug  534: Test suite fixed (see above).
158
* Bug 1710: mprofile now handles mode args correctly.
159
* Bug 1723: PS2 keyboard error message clearer if RX file won't open.
160 104 jeremybenn
* Bug 1733: Or1ksim now accepts ELF image when working through RSP.
161
* Bug 1767: l.lws is not recognized as an opcode.
162 85 jeremybenn
 
163 89 jeremybenn
The following bugs are either cannot be reproduced or will not be fixed.
164
 
165 104 jeremybenn
The following bugs are outstanding
166
* Bug 1758: Memory controller issues. Workaround in the user guide.
167 89 jeremybenn
 
168 104 jeremybenn
 
169 19 jeremybenn
New in release 0.3.0
170 85 jeremybenn
====================
171
 
172 19 jeremybenn
* No new features or bugs. This is the full release based on rc3.
173
 
174
New in release 0.3.0rc3
175 85 jeremybenn
=======================
176
 
177 19 jeremybenn
* Bug 376 fixed: 32 interrupts now supported
178
* Bug 377 fixed: Level triggered interrupts now work correctly
179
* Bug 378 fixed: xterm UART now works with RSP
180
* Bug 379 fixed: RSP performance improved
181
* Bug 380 fixed: GDB 6.8 stepi now works through Or1ksim JTAG interface
182
* Bug 398 fixed: Lack of support for LEE bit in SR documented
183
* Bug 415 fixed: NPC behavior on writing optionally matches real HW
184
* Bug 418 fixed: All library up calls are host-endian
185
 
186
* Feature 395 added: Boot from 0xf0000000 now enabled.
187
* Feature 408 added: Image file may be NULL for or1ksim_init.
188
* Feature 410 added: RSP now clears sigval on unstalling the processor.
189
* Feature 417 added: Or1ksim prints out its version on startup.
190
 
191
New in release 0.3.0rc2
192 85 jeremybenn
=======================
193
 
194 19 jeremybenn
* A number of bug fixes
195
* Updates to user guide
196
 
197
New in release 0.3.0rc1
198 85 jeremybenn
=======================
199
 
200 19 jeremybenn
* Numerous bug fixes (see the OpenRISC tracker and the ChangeLog file)
201
* User Guide
202
* Consistent coding style and file naming throughout
203
* Support for external SystemC models
204
 
205 85 jeremybenn
New in release 1.9 (old style numbering)
206
========================================
207 19 jeremybenn
 
208
* support for binary COFF
209
* generation of verilog memory models (used when you want to run simulation
210
of OpenRISC processor cores)
211
 
212 85 jeremybenn
New in release 1.2 (old style numbering)
213
========================================
214 19 jeremybenn
 
215
* support for OR16 ISA
216
 
217 85 jeremybenn
New in release 1.1 (old style numbering)
218
========================================
219 19 jeremybenn
 
220
 * First release

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.