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1 82 jeremybenn
/* jtag.c -- JTAG modeling
2
 
3
   Copyright (C) 2008 Embecosm Limited
4
 
5
   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
6
 
7
   This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
8
 
9
   This program is free software; you can redistribute it and/or modify it
10
   under the terms of the GNU General Public License as published by the Free
11
   Software Foundation; either version 3 of the License, or (at your option)
12
   any later version.
13
 
14
   This program is distributed in the hope that it will be useful, but WITHOUT
15
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
17
   more details.
18
 
19
   You should have received a copy of the GNU General Public License along
20
   with this program.  If not, see <http://www.gnu.org/licenses/>.  */
21
 
22
/* This program is commented throughout in a fashion suitable for processing
23
   with Doxygen. */
24
 
25
 
26
/* Autoconf and/or portability configuration */
27
#include "config.h"
28
#include "port.h"
29
 
30
/* System includes */
31
#include <stdlib.h>
32
#include <unistd.h>
33
#include <stddef.h>
34
#include <stdint.h>
35
#include <string.h>
36
 
37
/* Package includes */
38
#include "sim-config.h"
39
#include "sprs.h"
40
#include "debug-unit.h"
41
#include "spr-defs.h"
42
#include "jtag.h"
43
#include "abstract.h"
44
#include "toplevel-support.h"
45
 
46
 
47
/*---------------------------------------------------------------------------*/
48
/*!Calculate an ongoing 32-bit CRC for a value
49
 
50
   Utility function. This is for a CRC, where the value is presented in normal
51
   order (i.e its most significant bit is at the most significant positions,
52
   it has not been reversed for incorporating ina JTAG register).
53
 
54
   The function can be used for values with more than 64 bits, but will treat
55
   the supplied value as the most-significant 64 bits, with all other bits
56
   zero. In practice this is only of use when shifting in a large number of
57
   zeros.
58
 
59
   The CRC used is the IEEE 802.3 32-bit CRC using the polynomial:
60
 
61
   x^32 + x^26 + x^23 +x^22 +x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 +
62
   x^4 + x^2 + x^1 + 1
63
 
64
   In this implementation, the CRC is initialized to all ones (outside this
65
   function), to catch leading zeros.
66
 
67
   The function is designed to be used in a continuing calculation if
68
   desired. It takes a partially computed CRC and shifts in the appropriate
69
   new bits for the value supplied. For a new calculation, this value should
70
   be 0xffffffff.
71
 
72
  @param[in] value     The number whose CRC is wanted (MSB first)
73
  @param[in] num_bits  The number of bits to use from value
74
  @param[in] crc_in    The value of the CRC computed so far
75
 
76
  @return  The updated CRC value                                             */
77
/*---------------------------------------------------------------------------*/
78
static uint32_t
79
crc32 (uint64_t  value,
80
       int       num_bits,
81
       uint32_t  crc_in)
82
{
83
  static const uint32_t  CRC32_POLY = 0x04c11db7;
84
 
85
  /* Incorporate the bits, MS bit first. */
86
  int  i;
87
 
88
  for (i = num_bits - 1; i >= 0; i--)
89
    {
90
      uint32_t  d = (1 == ((value >> i) & 1))   ? 0xfffffff : 0x0000000;
91
      uint32_t  t = (1 == ((crc_in >> 31) & 1)) ? 0xfffffff : 0x0000000;
92
 
93
      crc_in <<= 1;
94
      crc_in  ^= (d ^ t) & CRC32_POLY;
95
    }
96
 
97
  return  crc_in;
98
 
99
}       /* crc32 () */
100
 
101
 
102
/*---------------------------------------------------------------------------*/
103
/*!Reverse up to 64 bits in a word
104
 
105
   Utility function. Uses the "reverse" algorithm from the University of
106
   Kentucky Aggregate Magic Algorithms.
107
 
108
   @param[in] val      The long word to reverse
109
   @param[in] numBits  Number of bits to reverse
110
 
111
   @return  The reversed word.                                               */
112
/*---------------------------------------------------------------------------*/
113
static uint64_t
114
reverse_bits (uint64_t  val,
115
              int       numBits)
116
{
117
  val = (((val & 0xaaaaaaaaaaaaaaaaULL) >>  1) |
118
         ((val & 0x5555555555555555ULL) <<  1));
119
  val = (((val & 0xccccccccccccccccULL) >>  2) |
120
         ((val & 0x3333333333333333ULL) <<  2));
121
  val = (((val & 0xf0f0f0f0f0f0f0f0ULL) >>  4) |
122
         ((val & 0x0f0f0f0f0f0f0f0fULL) <<  4));
123
  val = (((val & 0xff00ff00ff00ff00ULL) >>  8) |
124
         ((val & 0x00ff00ff00ff00ffULL) <<  8));
125
  val = (((val & 0xffff0000ffff0000ULL) >> 16) |
126
         ((val & 0x00000fff0000ffffULL) << 16));
127
  val = ((val >> 32) | (val << 32));
128
 
129
  return  val >> (64 - numBits);        /* Only the bits we want */
130
 
131
}       /* reverse_bits () */
132
 
133
 
134
/*---------------------------------------------------------------------------*/
135
/*!Reverse a byte
136
 
137
   Utility function. Uses the "reverse" algorithm from the University of
138
   Kentucky Aggregate Magic Algorithms.
139
 
140
   @param[in] byte  The byte to reverse
141
 
142
   @return  The reversed byte.                                               */
143
/*---------------------------------------------------------------------------*/
144
static uint8_t
145
reverse_byte (uint8_t  byte)
146
{
147
  byte = (((byte & 0xaa) >> 1) | ((byte & 0x55) << 1));
148
  byte = (((byte & 0xcc) >> 2) | ((byte & 0x33) << 2));
149
 
150
  return ((byte >> 4) | (byte << 4));
151
 
152
}       /* reverse_byte () */
153
 
154
 
155
/*---------------------------------------------------------------------------*/
156
/*!Construct a response register to shift out.
157
 
158
   The generic format is:
159
 
160
          +-------+--------+---------+---------+
161
          |       |        |         |         |
162
   TDI -> |  CRC  | Status |  XX..XX |  00..00 | -> TDO
163
          |       |        |         |         |
164
          +-------+--------+---------+---------+
165
              32       4    "ignored"   "zero"
166
             bits    bits      bits      bits
167
 
168
 
169
   Fields are always shifted in MS bit first, so must be reversed. The CRC is
170
   on the 4 status bits. Only the "zero" bits are zeroed. This allows for
171
   other fields to be specified in the "ignored" bits region, which are
172
   guaranteed to be left untouched.
173
 
174
   @param[out] jreg       The buffer for the constructed register
175
   @param[in]  status     The status bits
176
   @param[in]  crc_in     CRC computed so far (set to 0xffffffff if none)
177
   @param[in]  ign_bits   The number of bits to ignore
178
   @param[in]  zero_bits  The number of bits to zero
179
 
180
   @return  The register length in bits                                      */
181
/*---------------------------------------------------------------------------*/
182
static int
183
construct_response (unsigned char *jreg,
184
                    uint8_t        status,
185
                    uint32_t       crc_in,
186
                    unsigned int   ign_bits,
187
                    unsigned int   zero_bits)
188
{
189
  /* Construct the outgoing CRC */
190
  uint32_t  crc_out = crc32 (status, 4, crc_in);
191
 
192
  /* Reversed versions of fields ready for insertion */
193
  uint8_t   status_r  = reverse_bits (status, 4);
194
  uint32_t  crc_out_r = reverse_bits (crc_out, 32);
195
 
196
  /* Construct the response register */
197
  unsigned int  zero_bytes = zero_bits / 8;
198
  unsigned int  zero_off   = zero_bits % 8;
199
 
200
  /* Clear the zero bits */
201
  if (zero_bytes > 0)
202
    {
203
      memset (jreg, 0, zero_bytes);
204
    }
205
 
206
  jreg[zero_bytes] >>= zero_off;
207
  jreg[zero_bytes] <<= zero_off;
208
 
209
  /* Determine how much to skip in total */
210
  unsigned int  skip_bytes = ign_bits + zero_bits / 8;
211
  unsigned int  bit_off    = ign_bits + zero_bits % 8;
212
 
213
  /* Simplify by dealing separately with two cases:
214
     - the bit offset is less than or equal to 4, so the status goes in the
215
       first free byte, with some CRC.
216
     - the bit offset is greater than 4 but less than 8, so the status goes in
217
       the first and second free bytes.
218
 
219
     For completeness we deal with what should be the impossible case of
220
     bit_off > 7. */
221
  if (bit_off <= 4)
222
    {
223
      /* Note that this works even if bit_off == 4, since there will be no CRC
224
         remaining to OR into the first byte. */
225
      jreg[skip_bytes]     |=  ((status_r & 0xf) << bit_off) |
226
                              ((crc_out_r << (4 + bit_off)) & 0xff);
227
      jreg[skip_bytes + 1]  =  (crc_out_r >> ( 4 - bit_off)) & 0xff;
228
      jreg[skip_bytes + 2]  =  (crc_out_r >> (12 - bit_off)) & 0xff;
229
      jreg[skip_bytes + 3]  =  (crc_out_r >> (20 - bit_off)) & 0xff;
230
      jreg[skip_bytes + 4]  =  (crc_out_r >> (28 - bit_off)) & 0xff;
231
    }
232
  else if (bit_off < 8)
233
    {
234
      jreg[skip_bytes]     |=   status_r << bit_off;
235
      jreg[skip_bytes + 1]  =  (status_r >> (8 - bit_off)) |
236
                              ((crc_out_r << (bit_off - 4)) & 0xff);
237
      jreg[skip_bytes + 2]  =  (crc_out_r >> (12 - bit_off)) & 0xff;
238
      jreg[skip_bytes + 3]  =  (crc_out_r >> (20 - bit_off)) & 0xff;
239
      jreg[skip_bytes + 4]  =  (crc_out_r >> (28 - bit_off)) & 0xff;
240
      jreg[skip_bytes + 5]  =  (crc_out_r >> (36 - bit_off)) & 0xff;
241
    }
242
  else
243
    {
244
      fprintf (stderr, "*** ABORT ***: construct_response: impossible bit "
245
               "offset: %u\n", bit_off);
246
      abort ();
247
    }
248
 
249
  /* Result is the register length in bits */
250
  return  32 + 4 + skip_bytes;
251
 
252
}       /* construct_response () */
253
 
254
 
255
/*---------------------------------------------------------------------------*/
256
/*!Select a module for debug
257
 
258
   Process a module selection register. The format is:
259
 
260
          +---------+-------+--------+---+
261
          |         |       |        |   |
262
   TDI -> | Ignored |  CRC  | Module | 1 | -> TDO
263
          |         |       |   ID   |   |
264
          +---------+-------+--------+---+
265
              36        32       4
266
             bits      bits    bits
267
 
268
   The returned register has the format:
269
 
270
          +-------+--------+---------+
271
          |       |        |         |
272
   TDI -> |  CRC  | Status |  00..00 | -> TDO
273
          |       |        |         |
274
          +-------+--------+---------+
275
              32       4        37
276
             bits    bits      bits
277
 
278
 
279
   Fields are always shifted in MS bit first, so must be reversed. The CRC in
280
   is computed on the first 5 bits, the CRC out on the 4 status bits.
281
 
282
   @param[in,out] jreg  The register to shift in, and the register shifted
283
                        back out.
284
 
285
   @return  The number of cycles the shift took, which in turn is the number
286
            of bits in the register                                          */
287
/*---------------------------------------------------------------------------*/
288
static int
289
module_select (unsigned char *jreg)
290
{
291
  /* Break out the fields */
292
  uint8_t   mod_id = reverse_bits ((jreg[0] >> 1) & 0xf, 4);
293
  uint32_t  crc_in = reverse_bits (((uint32_t )  jreg[0] & 0xe0  >>  5) |
294
                                   ((uint32_t )  jreg[1]         <<  3) |
295
                                   ((uint32_t )  jreg[2]         << 11) |
296
                                   ((uint32_t )  jreg[3]         << 19) |
297
                                   ((uint32_t ) (jreg[4] & 0x1f) << 27), 32);
298
 
299
  /* Compute the expected CRC */
300
  uint32_t  crc_computed;
301
 
302
  crc_computed = crc32 (1,      1, 0xffffffff);
303
  crc_computed = crc32 (mod_id, 4, crc_computed);
304
 
305
  /* Status flags */
306
  enum jtag_status  status = JS_OK;
307
 
308
  /* Validate the CRC */
309
  if (crc_computed != crc_in)
310
    {
311
      /* Mismatch: record the error */
312
      status |= JS_CRC_IN_ERROR;
313
    }
314
  else
315
    {
316
      /* Is it a valid module? */
317
      switch (mod_id)
318
        {
319
        case JM_WISHBONE:
320
        case JM_CPU0:
321
        case JM_CPU1:
322
          /* All valid. Record the module */
323
          runtime.debug.mod_id = mod_id;
324
 
325
          break;
326
 
327
        default:
328
          /* Bad module: record the error */
329
          status |= JS_MODULE_MISSING;
330
          break;
331
        }
332
    }
333
 
334
  /* Construct the outgoing register and return the JTAG cycles taken (the
335
     register length) */
336
  return  construct_response (jreg, status, 0xffffffff, 0, 37);
337
 
338
}       /* module_select */
339
 
340
 
341
/*---------------------------------------------------------------------------*/
342
/*!Validate WRITE_COMMAND fields for WishBone
343
 
344
   Check that a WRITE_COMMAND's fields are valid for WishBone access.
345
 
346
   - 16 and 32-bit access must be correctly aligned. If not a warning is
347
     printed and validation fails.
348
 
349
   - size must be a multiple of 2 for 16-bit access, and a multiple of 4 for
350
     32-bit access
351
 
352
   Validation is carried out when executing a GO_COMMAND, rather than when
353
   setting the WRITE_COMMAND, because only the GO_COMMAND can set the status
354
   error if there is a problem.
355
 
356
   Warning messages are printed to explain any validation problems.
357
 
358
   @todo Should multiple SPR accesses be allowed in a single access?
359
 
360
   @note The size of the data is one greater than the length specified in the
361
         original WRITE_COMMAND.
362
 
363
   @return  1 (TRUE) if validation is OK, 0 (FALSE) if validation fails.     */
364
/*---------------------------------------------------------------------------*/
365
static int
366
validate_wb_fields ()
367
{
368
  /* Determine the size of the access */
369
  uint32_t  access_bits;
370
 
371
  switch (runtime.debug.acc_type)
372
    {
373
    case JAT_WRITE8:
374
    case JAT_READ8:
375
      access_bits =  8;
376
      break;
377
 
378
    case JAT_WRITE16:
379
    case JAT_READ16:
380
      access_bits = 16;
381
      break;
382
 
383
    case JAT_WRITE32:
384
    case JAT_READ32:
385
      access_bits = 32;
386
      break;
387
 
388
    default:
389
      fprintf (stderr, "*** ABORT ***: validate_wb_fields: unknown access "
390
               "type %u\n", runtime.debug.acc_type);
391
      abort ();
392
    }
393
 
394
  /* Check for validity. This works for 8-bit, although the tests will always
395
     pass. */
396
  uint32_t  access_bytes = access_bits / 8;
397
 
398
  if (0 != (runtime.debug.addr % access_bytes))
399
    {
400
      fprintf (stderr, "Warning: JTAG WishBone %d-bit access must be %d-byte "
401
               "aligned\n", access_bits, access_bytes);
402
      return  0;
403
    }
404
  else if (0 != (runtime.debug.size % access_bytes))
405
    {
406
      fprintf (stderr, "Warning: JTAG %d-bit WishBone access must be multiple "
407
               "of %d bytes in length\n", access_bits, access_bytes);
408
      return  0;
409
    }
410
  else
411
    {
412
      return  1;                        /* No problems */
413
    }
414
}       /* validate_wb_fields () */
415
 
416
 
417
/*---------------------------------------------------------------------------*/
418
/*!Read WishBone data
419
 
420
   Read memory from WishBone. The WRITE_COMMAND address is updated to reflect
421
   the completed read if successful.
422
 
423
   The result is the CRC of the data read. The status flag is supplied as a
424
   pointer, since this can also be updated if there is a problem reading the
425
   data.
426
 
427
   @note The size of the data is one greater than the length specified in the
428
         original WRITE_COMMAND.
429
 
430
   @todo For now we always read a byte a time. In the future, we ought to use
431
         16 and 32-bit accesses for greater efficiency.
432
 
433
   @todo  The algorithm for ensuring we only set the bits of interest in the
434
          register is inefficient. We should instead clear the whole area
435
          before starting.
436
 
437
   @param[out] jreg        The JTAG register buffer where data is to be
438
                           stored.
439
   @param[in]  skip_bits   Bits to skip before storing data in jreg.
440
   @param[in]  status_ptr  Pointer to the status register.
441
 
442
   @return  The CRC of the data read                                         */
443
/*---------------------------------------------------------------------------*/
444
static uint32_t
445
wishbone_read (unsigned char    *jreg,
446
               unsigned int      skip_bits,
447
               enum jtag_status *status_ptr)
448
{
449
  /* Compute the CRC as we go */
450
  uint32_t  crc_out  = 0xffffffff;
451
 
452
  /* Validate the fields for the wishbone read. If this fails we stop here,
453
     setting an error in the status_ptr. */
454
  if (!validate_wb_fields())
455
    {
456
      *status_ptr |= JS_WISHBONE_ERROR;
457
      return  crc_out;
458
    }
459
 
460
  /* Transfer each byte in turn, computing the CRC as we go */
461
  unsigned  byte_off = skip_bits / 8;
462
  unsigned  bit_off  = skip_bits % 8;
463
 
464
  uint32_t  i;                          /* Index into the data being read */
465
 
466
  for (i = 0; i < runtime.debug.size; i++)
467
    {
468
      /* Error if we can't access this byte */
469
      if (NULL == verify_memoryarea (runtime.debug.addr + i))
470
        {
471
          *status_ptr |= JS_WISHBONE_ERROR;
472
          return  crc_out;
473
        }
474
 
475
      /* Get the data with no cache or VM translation and update the CRC */
476
      unsigned char  byte = eval_direct8 (runtime.debug.addr + i, 0, 0);
477
      crc_out = crc32 (byte, 8, crc_out);
478
 
479
      /* Store the byte in the register, without trampling adjacent
480
         bits. Simplified version when the bit offset is zero. */
481
      if (0 == bit_off)
482
        {
483
          jreg[byte_off + i] = byte;
484
        }
485
      else
486
        {
487
          /* Clear the bits (only) we are setting */
488
          jreg[byte_off + i]     <<= bit_off;
489
          jreg[byte_off + i]     >>= bit_off;
490
          jreg[byte_off + i + 1] >>= 8 - bit_off;
491
          jreg[byte_off + i + 1] <<= 8 - bit_off;
492
 
493
          /* OR in the bits */
494
          jreg[byte_off + i]     |= (byte <<      bit_off)  & 0xff;
495
          jreg[byte_off + i + 1] |= (byte >> (8 - bit_off)) & 0xff;
496
        }
497
    }
498
 
499
    runtime.debug.addr += runtime.debug.size;
500
 
501
  return  crc_out;
502
 
503
}       /* wishbone_read () */
504
 
505
 
506
/*---------------------------------------------------------------------------*/
507
/*!Validate WRITE_COMMAND fields for SPR
508
 
509
   Check that a WRITE_COMMAND's fields are valid for SPR access. Only prints
510
   messages, since the protocol does not allow for any errors.
511
 
512
   - 8 and 16-bit access is only permitted for WishBone. If they are specified
513
     for SPR, they are treated as their 32 bit equivalent. A warning is
514
     printed.
515
 
516
   - size must be 1 word. If a larger value is specified that is treated as 1
517
     with a warning.
518
 
519
   - address must be less than MAX_SPRS. If a larger value is specified, it is
520
     reduced module MAX_SPRS (which is hopefully a power of 2).
521
 
522
   Where errors are found, the data is updated.
523
 
524
   Validation is carried out with the GO_COMMAND, rather than with the
525
   WRITE_COMMAND, for consistency with WishBone error checking, for which
526
   only the GO_COMMAND can set the status error if there is a problem.
527
 
528
   Warning messages are printed to explain any validation problems.
529
 
530
   @todo Should multiple SPR accesses be allowed in a single access?
531
 
532
   @note The size of the data is one greater than the length specified in the
533
         original WRITE_COMMAND.                                             */
534
/*---------------------------------------------------------------------------*/
535
static void
536
validate_spr_fields ()
537
{
538
  int  access_bits;
539
  int  is_read_p;
540
 
541
  switch (runtime.debug.acc_type)
542
    {
543
    case JAT_WRITE8:  access_bits =  8; is_read_p = 0;
544
    case JAT_READ8:   access_bits =  8; is_read_p = 1;
545
    case JAT_WRITE16: access_bits = 16; is_read_p = 0;
546
    case JAT_READ16:  access_bits = 16; is_read_p = 1;
547
    case JAT_WRITE32: access_bits = 32; is_read_p = 0;
548
    case JAT_READ32:  access_bits = 32; is_read_p = 1;
549
 
550
    default:
551
      fprintf (stderr, "*** ABORT ***: validate_spr_fields: unknown access "
552
               "type %u\n", runtime.debug.acc_type);
553
      abort ();
554
    }
555
 
556
  /* Validate and correct if necessary access width */
557
  if (32 != access_bits)
558
    {
559
      fprintf (stderr, "Warning: JTAG %d-bit access not permitted for SPR: "
560
               "corrected\n", access_bits);
561
      runtime.debug.acc_type = is_read_p ? JAT_READ32 : JAT_WRITE32;
562
    }
563
 
564
  /* Validate and correct if necessary access size */
565
  if (1 != runtime.debug.size)
566
    {
567
      fprintf (stderr, "warning: JTAG SPR access must be 1 word in length: "
568
               "corrected\n");
569
      runtime.debug.size = 1;
570
    }
571
  /* Validate and correct if necessary access size */
572
  if (runtime.debug.addr >= MAX_SPRS)
573
    {
574
      fprintf (stderr, "warning: JTAG SPR address exceeds MAX_SPRS: "
575
               "truncated\n");
576
      runtime.debug.addr %= MAX_SPRS;
577
    }
578
}       /* validate_spr_fields () */
579
 
580
 
581
/*---------------------------------------------------------------------------*/
582
/*!Read SPR data
583
 
584
   Read memory from WishBone. The WRITE_COMMAND address is updated to reflect
585
   the completed read if successful.
586
 
587
   The result is the CRC of the data read.
588
 
589
   Unlike with Wishbone, there is no concept of any errors possible when
590
   reading an SPR.
591
 
592
   @todo The algorithm for ensuring we only set the bits of interest in the
593
         register is inefficient. We should instead clear the whole area
594
         before starting.
595
 
596
   @note The address is treated as a word address of the SPR.
597
 
598
   @note The debug unit is documented as being explicitly Big Endian. However
599
         that seems to be a poor basis for modeling, and more to do with the
600
         debug unit only ever being used with big-endian architectures. We
601
         transfer the bytes in the endianness of the OR1K.
602
 
603
   @param[out] jreg       The JTAG register buffer where data is to be stored.
604
   @param[in]  skip_bits  Bits to skip before storing data in jreg.
605
 
606
   @return  The CRC of the data read                                         */
607
/*---------------------------------------------------------------------------*/
608
static uint32_t
609
spr_read (unsigned char *jreg,
610
          unsigned int   skip_bits)
611
{
612
  /* Compute the CRC as we go */
613
  uint32_t  crc_out  = 0xffffffff;
614
 
615
  /* Validate the fields for the SPR read. This doesn't stop us - just prints
616
     out warnings and corrects the problems. */
617
  validate_spr_fields();
618
 
619
  /* Transfer the SPR */
620
  uint32_t  spr = mfspr (runtime.debug.addr);
621
 
622
  runtime.debug.addr++;
623
 
624
  /* Store the SPR in the register, without trampling adjacent
625
     bits. Simplified version when the bit offset is zero. Compute the CRC as
626
     we go. */
627
  unsigned  byte_off = skip_bits / 8;
628
  unsigned  bit_off  = skip_bits % 8;
629
 
630
  if (0 == bit_off)
631
    {
632
      /* Each byte in turn */
633
      int  i;
634
 
635
      for (i = 0; i < 4; i++)
636
        {
637
#ifdef OR32_BIG_ENDIAN
638
          uint8_t byte = (spr >> 8 * i) & 0xff;
639
#else /* !OR32_BIG_ENDIAN */
640
          uint8_t byte = (spr >> (24 - (8 * i))) & 0xff;
641
#endif /* OR32_BIG_ENDIAN */
642
 
643
          jreg[byte_off + i] =  byte;
644
          crc_out = crc32 (byte, 8, crc_out);
645
        }
646
    }
647
  else
648
    {
649
      /* Each byte in turn */
650
      int  i;
651
 
652
      for (i = 0; i < 4; i++)
653
        {
654
#ifdef OR32_BIG_ENDIAN
655
          uint8_t byte = (spr >> 8 * i) & 0xff;
656
#else /* !OR32_BIG_ENDIAN */
657
          uint8_t byte = (spr >> (24 - (8 * i))) & 0xff;
658
#endif /* OR32_BIG_ENDIAN */
659
 
660
          /* Clear the bits (only) we are setting */
661
          jreg[byte_off + i]     <<= bit_off;
662
          jreg[byte_off + i]     >>= bit_off;
663
          jreg[byte_off + i + 1] >>= 8 - bit_off;
664
          jreg[byte_off + i + 1] <<= 8 - bit_off;
665
 
666
          /* OR in the bits */
667
          jreg[byte_off + i]     |= (byte <<      bit_off)  & 0xff;
668
          jreg[byte_off + i + 1] |= (byte >> (8 - bit_off)) & 0xff;
669
 
670
          crc_out = crc32 (byte, 8, crc_out);
671
        }
672
    }
673
 
674
  return  crc_out;
675
 
676
}       /* spr_read () */
677
 
678
 
679
/*---------------------------------------------------------------------------*/
680
/*!Carry out a read from WishBone or SPR
681
 
682
   Process a GO_COMMAND register for read. The format is:
683
 
684
          +-------------+-------+---------+---+
685
          |             |       |    GO   |   |
686
   TDI -> |   Ignored   |  CRC  | COMMAND | 0 | -> TDO
687
          |             |       |  (0x0)  |   |
688
          +-------------+-------+---------+---+
689
           36 + 8 * size    32       4
690
               bits        bits    bits
691
 
692
   The returned register has the format:
693
 
694
          +-------+--------+------------+---------+
695
          |       |        |            |         |
696
   TDI -> |  CRC  | Status |    Data    |  00..00 | -> TDO
697
          |       |        |            |         |
698
          +-------+--------+------------+---------+
699
              32       4      8 * size       37
700
             bits    bits       bits        bits
701
 
702
   Fields are always shifted in MS bit first, so must be reversed. The CRC in
703
   is computed on the first 5 bits, the CRC out on the 4 + 8 * size status and
704
   data bits.
705
 
706
   @note The size of the data is one greater than the length specified in the
707
         original WRITE_COMMAND.
708
 
709
   @param[in,out] jreg  The register to shift in, and the register shifted
710
                        back out.
711
 
712
   @return  The number of cycles the shift took, which in turn is the number
713
            of bits in the register                                          */
714
/*---------------------------------------------------------------------------*/
715
static int
716
go_command_read (unsigned char *jreg)
717
{
718
  /* Break out the fields */
719
  uint32_t  crc_in   = reverse_bits (((uint32_t) (jreg[0] & 0xe0) >>  5) |
720
                                     ((uint32_t)  jreg[1]         <<  3) |
721
                                     ((uint32_t)  jreg[2]         << 11) |
722
                                     ((uint32_t)  jreg[3]         << 19) |
723
                                     ((uint32_t) (jreg[4] & 0x1f) << 27), 32);
724
 
725
  /* Compute the expected CRC */
726
  uint32_t  crc_computed;
727
 
728
  crc_computed = crc32 (0,                1, 0xffffffff);
729
  crc_computed = crc32 (JCMD_GO_COMMAND,  4, crc_computed);
730
 
731
  /* Status flags */
732
  enum jtag_status  status = JS_OK;
733
 
734
  /* CRC to go out */
735 96 jeremybenn
  uint32_t  crc_out = 0;
736 82 jeremybenn
 
737
  /* Validate the CRC */
738
  if (crc_computed == crc_in)
739
    {
740
      /* Read the data. */
741
      switch (runtime.debug.mod_id)
742
        {
743
        case JM_WISHBONE:
744
          crc_out = wishbone_read (jreg, 37, &status);
745
          break;
746
 
747
        case JM_CPU0:
748
          crc_out = spr_read (jreg, 37);
749
          break;
750
 
751
        case JM_CPU1:
752
          fprintf (stderr, "Warning: JTAG attempt to read from CPU1: Not "
753
                   "supported.\n");
754
          break;
755
 
756
        default:
757
          fprintf (stderr, "*** ABORT ***: go_command_read: invalid "
758
                   "module\n");
759
          abort ();
760
        }
761
    }
762
  else
763
    {
764
      /* Mismatch: record the error */
765
      status |= JS_CRC_IN_ERROR;
766
    }
767
 
768
  /* Construct the outgoing register, skipping the data read and returning the
769
     number of JTAG cycles taken (the register length). */
770
  return  construct_response (jreg, status, crc_out, 8 * runtime.debug.size,
771
                              37);
772
 
773
}       /* go_command_read () */
774
 
775
 
776
/*---------------------------------------------------------------------------*/
777
/*!Write WishBone data
778
 
779
   Write memory to WishBone. The WRITE_COMMAND address is updated to reflect
780
   the completed write if successful.
781
 
782
   @note The size of the data is one greater than the length specified in the
783
         original WRITE_COMMAND.
784
 
785
   @todo For now we always write a byte a time. In the future, we ought to use
786
         16 and 32-bit accesses for greater efficiency.
787
 
788
   @todo  The algorithm for ensuring we only set the bits of interest in the
789
          register is inefficient. We should instead clear the whole area
790
          before starting.
791
 
792
   @param[out] jreg        The JTAG register buffer where data is to be
793
                           stored.
794
   @param[in]  skip_bits   Bits to skip before reading data from jreg.
795
   @param[in]  status_ptr  Pointer to the status register.                   */
796
/*---------------------------------------------------------------------------*/
797
static void
798
wishbone_write (unsigned char   *jreg,
799
               unsigned int      skip_bits,
800
               enum jtag_status *status_ptr)
801
{
802
  /* Validate the fields for the wishbone write. If this fails we stop here,
803
     setting an error in the status_ptr. */
804
  if (!validate_wb_fields())
805
    {
806
      *status_ptr |= JS_WISHBONE_ERROR;
807
      return;
808
    }
809
 
810
  /* Transfer each byte in turn, computing the CRC as we go */
811
  unsigned  byte_off = skip_bits / 8;
812
  unsigned  bit_off  = skip_bits % 8;
813
 
814
  uint32_t  i;                          /* Index into the data being write */
815
 
816
  for (i = 0; i < runtime.debug.size; i++)
817
    {
818
      /* Error if we can't access this byte */
819
      if (NULL == verify_memoryarea (runtime.debug.addr + i))
820
        {
821
          *status_ptr |= JS_WISHBONE_ERROR;
822
          return;
823
        }
824
 
825
      /* Extract the byte from the register. Simplified version when the bit
826
         offset is zero. */
827
      unsigned char  byte_r;
828
 
829
      if (0 == bit_off)
830
        {
831
          byte_r = jreg[byte_off + i];
832
        }
833
      else
834
        {
835
          byte_r = jreg[byte_off + i]     >>      bit_off  |
836
                   jreg[byte_off + i + 1] >> (8 - bit_off);
837
        }
838
 
839
      /* Circumvent the read-only check usually done for mem accesses. */
840
      set_program8 (runtime.debug.addr + i, reverse_byte (byte_r));
841
    }
842
 
843
  runtime.debug.addr += runtime.debug.size;
844
 
845
}       /* wishbone_write () */
846
 
847
 
848
/*---------------------------------------------------------------------------*/
849
/*!Write SPR data
850
 
851
   Write memory to WishBone. The WRITE_COMMAND address is updated to reflect
852
   the completed write if successful.
853
 
854
   Unlike with Wishbone, there is no concept of any errors possible when
855
   writeing an SPR.
856
 
857
   @todo The algorithm for ensuring we only set the bits of interest in the
858
         register is inefficient. We should instead clear the whole area
859
         before starting.
860
 
861
   @note The address is treated as a word address of the SPR.
862
 
863
   @note The debug unit is documented as being explicitly Big Endian. However
864
         that seems to be a poor basis for modeling, and more to do with the
865
         debug unit only ever being used with big-endian architectures. We
866
         transfer the bytes in the endianness of the OR1K.
867
 
868
   @param[out] jreg       The JTAG register buffer where data is to be stored.
869
   @param[in]  skip_bits  Bits to skip before reading data from jreg.        */
870
/*---------------------------------------------------------------------------*/
871
static void
872
spr_write (unsigned char *jreg,
873
          unsigned int   skip_bits)
874
{
875
  /* Validate the fields for the SPR write. This doesn't stop us - just prints
876
     out warnings and corrects the problems. */
877
  validate_spr_fields ();
878
 
879
  /* Construct the SPR value one byte at a time. */
880
  uint32_t  spr = 0;
881
 
882
  unsigned  byte_off = skip_bits / 8;
883
  unsigned  bit_off  = skip_bits % 8;
884
 
885
  /* Each byte in turn */
886
  int  i;
887
 
888
  for (i = 0; i < 4; i++)
889
    {
890
      uint8_t byte;
891
 
892
      /* Simplified version when the bit offset is zero */
893
      if (0 == bit_off)
894
        {
895
          byte = reverse_byte (jreg[byte_off + i]);
896
        }
897
      else
898
        {
899
          byte = reverse_byte ((jreg[byte_off + i]     >>      bit_off) |
900
                               (jreg[byte_off + i + 1] << (8 - bit_off)));
901
        }
902
 
903
#ifdef OR32_BIG_ENDIAN
904
      spr |= ((uint32_t) (byte)) << (8 * i);
905
#else /* !OR32_BIG_ENDIAN */
906
      spr |= ((uint32_t) (byte)) << (24 - (8 * i));
907
#endif /* OR32_BIG_ENDIAN */
908
    }
909
 
910
  /* Transfer the SPR */
911
  mtspr (runtime.debug.addr, spr);
912
  runtime.debug.addr++;
913
 
914
}       /* spr_write () */
915
 
916
 
917
/*---------------------------------------------------------------------------*/
918
/*!Carry out a write to WishBone or SPR
919
 
920
   Process a GO_COMMAND register for write. The format is:
921
 
922
          +-------------+-------+------------+---------+---+
923
          |             |       |            |    GO   |   |
924
   TDI -> |   Ignored   |  CRC  |    Data    | COMMAND | 0 | -> TDO
925
          |             |       |            |  (0x0)  |   |
926
          +-------------+-------+------------+---------+---+
927
                36          32     8 * size       4
928
               bits        bits      bits       bits
929
 
930
   The returned register has the format:
931
 
932
          +-------+--------+-------------+
933
          |       |        |             |
934
   TDI -> |  CRC  | Status |  00......00 | -> TDO
935
          |       |        |             |
936
          +-------+--------+-------------+
937
              32       4    8 * size + 37
938
             bits    bits        bits
939
 
940
   Fields are always shifted in MS bit first, so must be reversed. The CRC in
941
   is computed on the first 5 + 8 * size bits, the CRC out on the 4 status
942
   bits.
943
 
944
   @note The size of the data is one greater than the length specified in the
945
         original WRITE_COMMAND.
946
 
947
   @todo The rules say we look for errors in the WRITE_COMMAND spec
948
         here. However it would be better to do that at WRITE_COMMAND time and
949
         save the result for here, to avoid using duff data.
950
 
951
   @param[in,out] jreg  The register to shift in, and the register shifted
952
                        back out.
953
 
954
   @return  The number of cycles the shift took, which in turn is the number
955
            of bits in the register                                          */
956
/*---------------------------------------------------------------------------*/
957
static int
958
go_command_write (unsigned char *jreg)
959
{
960
  /* Break out the fields */
961
  uint32_t  crc_in =
962
    reverse_bits (((uint32_t) (jreg[runtime.debug.size + 0] & 0xe0) >>  5) |
963
                  ((uint32_t)  jreg[runtime.debug.size + 1]         <<  3) |
964
                  ((uint32_t)  jreg[runtime.debug.size + 2]         << 11) |
965
                  ((uint32_t)  jreg[runtime.debug.size + 3]         << 19) |
966
                  ((uint32_t) (jreg[runtime.debug.size + 4] & 0x1f) << 27),
967
                  32);
968
 
969
  /* Compute the expected CRC */
970
  uint32_t  crc_computed;
971
 
972
  crc_computed = crc32 (0,                1, 0xffffffff);
973
  crc_computed = crc32 (JCMD_GO_COMMAND,  4, crc_computed);
974
 
975
  int  i;
976
 
977
  for (i = 0; i < runtime.debug.size; i++)
978
    {
979
      uint8_t  byte = ((jreg[i] & 0xe0) >> 5) | ((jreg[i + 1] & 0x1f) << 3);
980
      crc_computed = crc32 (byte, 8, crc_computed);
981
    }
982
 
983
  /* Status flags */
984
  enum jtag_status  status = JS_OK;
985
 
986
  /* Validate the CRC */
987
  if (crc_computed == crc_in)
988
    {
989
      /* Read the data. */
990
      switch (runtime.debug.mod_id)
991
        {
992
        case JM_WISHBONE:
993
          wishbone_write (jreg, 5, &status);
994
          break;
995
 
996
        case JM_CPU0:
997
          spr_write (jreg, 5);
998
          break;
999
 
1000
        case JM_CPU1:
1001
          fprintf (stderr, "Warning: JTAG attempt to write to CPU1: Not "
1002
                   "supported.\n");
1003
          break;
1004
 
1005
        default:
1006
          fprintf (stderr, "*** ABORT ***: go_command_write: invalid "
1007
                   "module\n");
1008
          abort ();
1009
        }
1010
    }
1011
  else
1012
    {
1013
      /* Mismatch: record the error */
1014
      status |= JS_CRC_IN_ERROR;
1015
    }
1016
 
1017
  /* Construct the outgoing register, skipping the data read and returning the
1018
     number of JTAG cycles taken (the register length). */
1019
  return  construct_response (jreg, status, 0xffffffff, 0,
1020
                              37 + 8 * runtime.debug.size);
1021
 
1022
}       /* go_command_write () */
1023
 
1024
 
1025
/*---------------------------------------------------------------------------*/
1026
/*!Invoke the action specified by a prior WRITE_COMMAND register
1027
 
1028
   Process a GO_COMMAND register.
1029
 
1030
   How this is handled depends on whether a previous WRITE_COMMAND has
1031
   selected a read access type or a write access type has been selected.
1032
 
1033
   This function breaks this out.
1034
 
1035
   @param[in,out] jreg  The register to shift in, and the register shifted
1036
                        back out.
1037
 
1038
   @return  The number of cycles the shift took, which in turn is the number
1039
            of bits in the register                                          */
1040
/*---------------------------------------------------------------------------*/
1041
static int
1042
go_command (unsigned char *jreg)
1043
{
1044
  /* Have we even had a WRITE_COMMAND? */
1045
  if (!runtime.debug.write_defined_p)
1046
    {
1047
      fprintf (stderr, "Warning: JTAG GO_COMMAND with no prior WRITE_COMMAND: "
1048
               "ignored\n");
1049
      return 4 + 1;                     /* Only the first 5 bits meaningful */
1050
    }
1051
 
1052
  /* Whether to read or write depends on the access type */
1053
  switch (runtime.debug.acc_type)
1054
    {
1055
    case JAT_WRITE8:
1056
    case JAT_WRITE16:
1057
    case JAT_WRITE32:
1058
      return  go_command_write (jreg);
1059
 
1060
    case JAT_READ8:
1061
    case JAT_READ16:
1062
    case JAT_READ32:
1063
      return  go_command_read (jreg);
1064
 
1065
    default:
1066
      fprintf (stderr, "Warning: JTAG GO_COMMAND: invalid access type: "
1067
               "ignored\n");
1068
      return 4 + 1;                     /* Only the first 5 bits meaningful */
1069
    }
1070
}       /* go_command () */
1071
 
1072
 
1073
/*---------------------------------------------------------------------------*/
1074
/*!Read a previouse WRITE_COMMAND register
1075
 
1076
   Process a READ_COMMAND register. The format is:
1077
 
1078
          +---------+-------+---------+---+
1079
          |         |       |   READ  |   |
1080
   TDI -> | Ignored |  CRC  | COMMAND | 0 | -> TDO
1081
          |         |       |  (0x1)  |   |
1082
          +---------+-------+---------+---+
1083
              88        32       4
1084
             bits      bits    bits
1085
 
1086
   The returned register has the format:
1087
 
1088
          +-------+--------+--------+---------+--------+---------+
1089
          |       |        |        |         |        |         |
1090
   TDI -> |  CRC  | Status | Length | Address | Access |  00..00 | -> TDO
1091
          |       |        |        |         |  Type  |         |
1092
          +-------+--------+--------+---------+--------+---------+
1093
              32       4       16        32        4        37
1094
             bits    bits     bits      bits     bits      bits
1095
 
1096
   Fields are always shifted in MS bit first, so must be reversed. The CRC in
1097
   is computed on the first 5 bits, the CRC out on the 56 status, length,
1098
   address and access type bits.
1099
 
1100
   @param[in,out] jreg  The register to shift in, and the register shifted
1101
                        back out.
1102
 
1103
   @return  The number of cycles the shift took, which in turn is the number
1104
            of bits in the register                                          */
1105
/*---------------------------------------------------------------------------*/
1106
static int
1107
read_command (unsigned char *jreg)
1108
{
1109
  /* Break out the fields */
1110
  uint32_t  crc_in   = reverse_bits (((uint32_t) (jreg[0] & 0xe0) >>  5) |
1111
                                     ((uint32_t)  jreg[1]         <<  3) |
1112
                                     ((uint32_t)  jreg[2]         << 11) |
1113
                                     ((uint32_t)  jreg[3]         << 19) |
1114
                                     ((uint32_t) (jreg[4] & 0x1f) << 27), 32);
1115
 
1116
  /* Compute the expected CRC */
1117
  uint32_t  crc_computed;
1118
 
1119
  crc_computed = crc32 (0,                   1, 0xffffffff);
1120
  crc_computed = crc32 (JCMD_READ_COMMAND,  4, crc_computed);
1121
 
1122
  /* CRC to go out */
1123
  uint32_t  crc_out = 0xffffffff;
1124
 
1125
  /* Status flags */
1126
  enum jtag_status  status = JS_OK;
1127
 
1128
  /* Validate the CRC */
1129
  if (crc_computed != crc_in)
1130
    {
1131
      /* Mismatch: record the error */
1132
      status |= JS_CRC_IN_ERROR;
1133
    }
1134
  else if (runtime.debug.write_defined_p)
1135
    {
1136
      /* Compute the CRC */
1137
      crc_out = crc32 (runtime.debug.acc_type,  4, crc_out);
1138
      crc_out = crc32 (runtime.debug.addr,     32, crc_out);
1139
      crc_out = crc32 (runtime.debug.size - 1, 16, crc_out);
1140
 
1141
      /* Construct the outgoing register. Fields can only be written if they
1142
         are available */
1143
      uint8_t   acc_type_r = reverse_bits (runtime.debug.acc_type,  4);
1144
      uint32_t  addr_r     = reverse_bits (runtime.debug.addr,     32);
1145
      uint16_t  len_r      = reverse_bits (runtime.debug.size - 1, 16);
1146
 
1147
      jreg[ 4] |= (acc_type_r <<  5) & 0xf8;
1148
      jreg[ 5] |= (acc_type_r >>  3) & 0x07;
1149
      jreg[ 5] |= (addr_r     <<  1) & 0xfe;
1150
      jreg[ 6] |= (addr_r     >>  7) & 0xff;
1151
      jreg[ 7] |= (addr_r     >> 15) & 0xff;
1152
      jreg[ 8] |= (addr_r     >> 23) & 0xff;
1153
      jreg[ 9] |= (addr_r     >> 31) & 0x01;
1154
      jreg[ 9] |= (len_r      <<  1) & 0xfe;
1155
      jreg[10] |= (len_r      >>  7) & 0xff;
1156
      jreg[11] |= (len_r      >> 15) & 0x01;
1157
    }
1158
  else
1159
    {
1160
      fprintf (stderr, "Warning: JTAG attempt to READ_COMMAND without prior "
1161
               "WRITE_COMMAND: no data returned\n");
1162
    }
1163
 
1164
  /* Construct the final response with the status, skipping the fields we've
1165
     just (possibly) written. */
1166
  return  construct_response (jreg, status, crc_out, 52, 37);
1167
 
1168
}       /* read_command () */
1169
 
1170
 
1171
/*---------------------------------------------------------------------------*/
1172
/*!Specify details for a subsequence GO_COMMAND
1173
 
1174
   Process a WRITE_COMMAND register. The format is:
1175
 
1176
          +---------+-------+--------+---------+--------+---------+---+
1177
          |         |       |        |         |        |  WRITE  |   |
1178
   TDI -> | Ignored |  CRC  | Length | Address | Access | COMMAND | 0 | -> TDO
1179
          |         |       |        |         |  Type  |  (0x2)  |   |
1180
          +---------+-------+--------+---------+--------+---------+---+
1181
              36        32      16        32        4         4
1182
             bits      bits    bits      bits     bits      bits
1183
 
1184
   The returned register has the format:
1185
 
1186
          +-------+--------+---------+
1187
          |       |        |         |
1188
   TDI -> |  CRC  | Status |  00..00 | -> TDO
1189
          |       |        |         |
1190
          +-------+--------+---------+
1191
              32       4        89
1192
             bits    bits      bits
1193
 
1194
 
1195
   Fields are always shifted in MS bit first, so must be reversed. The CRC in
1196
   is computed on the first 57 bits, the CRC out on the 4 status bits.
1197
 
1198
   @param[in,out] jreg  The register to shift in, and the register shifted
1199
                        back out.
1200
 
1201
   @return  The number of cycles the shift took, which in turn is the number
1202
            of bits in the register                                          */
1203
/*---------------------------------------------------------------------------*/
1204
static int
1205
write_command (unsigned char *jreg)
1206
{
1207
  /* Break out the fields */
1208
  uint8_t   acc_type = reverse_bits (((jreg[0] & 0x0e) >> 5) |
1209
                                      (jreg[1] & 0x01), 4);
1210
  uint32_t  addr     = reverse_bits (((uint32_t) (jreg[ 1] & 0xfe) >>  1) |
1211
                                     ((uint32_t)  jreg[ 2]         <<  7) |
1212
                                     ((uint32_t)  jreg[ 3]         << 15) |
1213
                                     ((uint32_t)  jreg[ 4]         << 23) |
1214
                                     ((uint32_t) (jreg[ 5] & 0x01) << 31), 32);
1215
  uint16_t  len      = reverse_bits (((uint32_t) (jreg[ 5] & 0xfe) >>  1) |
1216
                                     ((uint32_t)  jreg[ 6]         <<  7) |
1217
                                     ((uint32_t) (jreg[ 7] & 0x01) << 15), 16);
1218
  uint32_t  crc_in   = reverse_bits (((uint32_t) (jreg[ 7] & 0xfe) >>  1) |
1219
                                     ((uint32_t)  jreg[ 8]         <<  7) |
1220
                                     ((uint32_t)  jreg[ 9]         << 15) |
1221
                                     ((uint32_t)  jreg[10]         << 23) |
1222
                                     ((uint32_t) (jreg[11] & 0x01) << 31), 32);
1223
 
1224
  /* Compute the expected CRC */
1225
  uint32_t  crc_computed;
1226
 
1227
  crc_computed = crc32 (0,                   1, 0xffffffff);
1228
  crc_computed = crc32 (JCMD_WRITE_COMMAND,  4, crc_computed);
1229
  crc_computed = crc32 (acc_type,            4, crc_computed);
1230
  crc_computed = crc32 (addr,               32, crc_computed);
1231
  crc_computed = crc32 (len,                16, crc_computed);
1232
 
1233
  /* Status flags */
1234
  enum jtag_status  status = JS_OK;
1235
 
1236
  /* Validate the CRC */
1237
  if (crc_computed != crc_in)
1238
    {
1239
      /* Mismatch: record the error */
1240
      status |= JS_CRC_IN_ERROR;
1241
    }
1242
  else
1243
    {
1244
      /* All OK. All other errors can only occur when the GO_COMMAND tries to
1245
         execute the write. Record the information for next GO_COMMAND */
1246
      runtime.debug.write_defined_p = 1;
1247
      runtime.debug.acc_type        = acc_type;
1248
      runtime.debug.addr            = addr;
1249
      runtime.debug.size            = (unsigned long int) len + 1UL;
1250
    }
1251
 
1252
  /* Construct the outgoing register and return the JTAG cycles taken (the
1253
     register length) */
1254
  return  construct_response (jreg, status, 0xffffffff, 0, 89);
1255
 
1256
}       /* write_command () */
1257
 
1258
 
1259
/*---------------------------------------------------------------------------*/
1260
/*!Read the control bits from a CPU.
1261
 
1262
   Process a READ_CONTROL register. The format is:
1263
 
1264
          +---------+-------+---------+---+
1265
          |         |       |  READ   |   |
1266
   TDI -> | Ignored |  CRC  | CONTROL | 0 | -> TDO
1267
          |         |       |  (0x3)  |   |
1268
          +---------+-------+---------+---+
1269
              36        32       4
1270
             bits      bits    bits
1271
 
1272
   The returned register has the format:
1273
 
1274
          +-------+--------+--------+---------+
1275
          |       |        |        |         |
1276
   TDI -> |  CRC  | Status |  Data  |  00..00 | -> TDO
1277
          |       |        |        |         |
1278
          +-------+--------+--------+---------+
1279
              32       4       52        37
1280
             bits    bits     bits      bits
1281
 
1282
   Fields are always shifted in MS bit first, so must be reversed. The CRC in
1283
   is computed on the first 57 bits, the CRC out on the 4 status bits.
1284
 
1285
   @param[in,out] jreg  The register to shift in, and the register shifted
1286
                        back out.
1287
 
1288
   @return  The number of cycles the shift took, which in turn is the number
1289
            of bits in the register                                          */
1290
/*---------------------------------------------------------------------------*/
1291
static int
1292
read_control (unsigned char *jreg)
1293
{
1294
  /* Break out the fields. */
1295
  uint32_t  crc_in = reverse_bits (((uint32_t) (jreg[0] & 0xe0) >>  5) |
1296
                                   ((uint32_t)  jreg[1]         <<  3) |
1297
                                   ((uint32_t)  jreg[2]         << 11) |
1298
                                   ((uint32_t)  jreg[3]         << 19) |
1299
                                   ((uint32_t) (jreg[4] & 0x1f) << 27), 32);
1300
 
1301
  /* Compute the expected CRC */
1302
  uint32_t  crc_computed;
1303
 
1304
  crc_computed = crc32 (0,                   1, 0xffffffff);
1305
  crc_computed = crc32 (JCMD_READ_CONTROL,  4, crc_computed);
1306
 
1307
  /* CRC to go out */
1308
  uint32_t  crc_out = 0xffffffff;
1309
 
1310
  /* Status flags */
1311
  enum jtag_status  status = JS_OK;
1312
 
1313
  /* Validate the CRC */
1314
  if (crc_computed != crc_in)
1315
    {
1316
      /* Mismatch: record the error */
1317
      status |= JS_CRC_IN_ERROR;
1318
    }
1319
  else if (JM_CPU0 == runtime.debug.mod_id)
1320
    {
1321
      /* Valid module. Only bit we can sensibly read is the stall bit. */
1322
      uint64_t  data = (uint64_t) runtime.cpu.stalled << JCB_STALL;
1323
 
1324
      /* Compute the CRC */
1325
      crc_out = crc32 (data,  52, crc_out);
1326
 
1327
      /* Construct the outgoing register. */
1328
      uint64_t  data_r = reverse_bits (data, 52);
1329
 
1330
      jreg[ 4] |= (data_r <<  5) & 0xf8;
1331
      jreg[ 5] |= (data_r >>  3) & 0x07;
1332
      jreg[ 5] |= (data_r >> 11) & 0xff;
1333
      jreg[ 5] |= (data_r >> 19) & 0xff;
1334
      jreg[ 5] |= (data_r >> 27) & 0xff;
1335
      jreg[ 5] |= (data_r >> 35) & 0xff;
1336
      jreg[ 5] |= (data_r >> 43) & 0xff;
1337
      jreg[ 5] |= (data_r >> 51) & 0x01;
1338
    }
1339
  else
1340
    {
1341
      /* Not a valid module */
1342
      fprintf (stderr, "ERROR: JTAG attempt to read control data for module "
1343
               "other than CPU0: ignored\n");
1344
    }
1345
 
1346
  /* Construct the response with the status */
1347
  return  construct_response (jreg, status, crc_out, 52, 37);
1348
 
1349
}       /* read_control () */
1350
 
1351
 
1352
/*---------------------------------------------------------------------------*/
1353
/*!Write the control bits to a CPU.
1354
 
1355
   Process a WRITE_CONTROL register. The format is:
1356
 
1357
          +---------+-------+--------+---------+---+
1358
          |         |       |        |  WRITE  |   |
1359
   TDI -> | Ignored |  CRC  |  Data  | CONTROL | 0 | -> TDO
1360
          |         |       |        |  (0x4)  |   |
1361
          +---------+-------+--------+---------+---+
1362
              36        32      52        4
1363
             bits      bits    bits     bits
1364
 
1365
   The returned register has the format:
1366
 
1367
          +-------+--------+---------+
1368
          |       |        |         |
1369
   TDI -> |  CRC  | Status |  00..00 | -> TDO
1370
          |       |        |         |
1371
          +-------+--------+---------+
1372
              32       4        89
1373
             bits    bits      bits
1374
 
1375
   Fields are always shifted in MS bit first, so must be reversed. The CRC in
1376
   is computed on the first 57 bits, the CRC out on the 4 status bits.
1377
 
1378
   @param[in,out] jreg  The register to shift in, and the register shifted
1379
                        back out.
1380
 
1381
   @return  The number of cycles the shift took, which in turn is the number
1382
            of bits in the register                                          */
1383
/*---------------------------------------------------------------------------*/
1384
static int
1385
write_control (unsigned char *jreg)
1386
{
1387
  /* Break out the fields. */
1388
  uint64_t  data   = reverse_bits (((uint64_t) (jreg[ 0] & 0xe0) >>  5) |
1389
                                   ((uint64_t)  jreg[ 1]         <<  3) |
1390
                                   ((uint64_t)  jreg[ 2]         << 11) |
1391
                                   ((uint64_t)  jreg[ 3]         << 19) |
1392
                                   ((uint64_t)  jreg[ 4]         << 27) |
1393
                                   ((uint64_t)  jreg[ 5]         << 35) |
1394
                                   ((uint64_t)  jreg[ 6]         << 43) |
1395
                                   ((uint64_t) (jreg[ 7] & 0x01) << 51), 52);
1396
  uint32_t  crc_in = reverse_bits (((uint32_t) (jreg[ 7] & 0xfe) >>  1) |
1397
                                   ((uint32_t)  jreg[ 8]         <<  7) |
1398
                                   ((uint32_t)  jreg[ 9]         << 15) |
1399
                                   ((uint32_t)  jreg[10]         << 23) |
1400
                                   ((uint32_t) (jreg[11] & 0x01) << 31), 32);
1401
 
1402
  /* Compute the expected CRC */
1403
  uint32_t  crc_computed;
1404
 
1405
  crc_computed = crc32 (0,                   1, 0xffffffff);
1406
  crc_computed = crc32 (JCMD_WRITE_CONTROL,  4, crc_computed);
1407
  crc_computed = crc32 (data,               52, crc_computed);
1408
 
1409
  /* Status flags */
1410
  enum jtag_status  status = JS_OK;
1411
 
1412
  /* Validate the CRC */
1413
  if (crc_computed != crc_in)
1414
    {
1415
      /* Mismatch: record the error */
1416
      status |= JS_CRC_IN_ERROR;
1417
    }
1418
  else if (JM_CPU0 == runtime.debug.mod_id)
1419
    {
1420
      /* Good data and valid module. Reset, stall or unstall the register as
1421
         required. If reset is requested, there is no point considering
1422
         stalling! */
1423
      int  reset_bit = (0x1 == ((data >> JCB_RESET) & 0x1));
1424
      int  stall_bit = (0x1 == ((data >> JCB_STALL) & 0x1));
1425
 
1426
      if (reset_bit)
1427
        {
1428
          sim_reset ();
1429
        }
1430
      else
1431
        {
1432
          set_stall_state (stall_bit);
1433
        }
1434
    }
1435
  else
1436
    {
1437
      /* Not a valid module */
1438
      fprintf (stderr, "ERROR: JTAG attempt to control module other than "
1439
               "CPU0: ignored\n");
1440
    }
1441
 
1442
  /* Construct the response with the status */
1443
  return  construct_response (jreg, status, 0xffffffff, 0, 89);
1444
 
1445
}       /* write_control () */
1446
 
1447
 
1448
/*---------------------------------------------------------------------------*/
1449
/*!Initialize the JTAG system
1450
 
1451
   For now just reset the JTAG interface                                     */
1452
/*---------------------------------------------------------------------------*/
1453
void
1454
jtag_init ()
1455
{
1456
  (void) jtag_reset ();
1457
 
1458
}       /* jtag_init () */
1459
 
1460
 
1461
/*---------------------------------------------------------------------------*/
1462
/*!Reset the JTAG interface
1463
 
1464
   Mark the current JTAG instruction as undefined.
1465
 
1466
   @return  The number of cycles the reset took.                             */
1467
/*---------------------------------------------------------------------------*/
1468
int
1469
jtag_reset ()
1470
{
1471
  runtime.debug.instr = JI_UNDEFINED;
1472
 
1473
  return  JTAG_RESET_CYCLES;
1474
 
1475
}       /* jtag_reset () */
1476
 
1477
 
1478
/*---------------------------------------------------------------------------*/
1479
/*!Shift a JTAG instruction register
1480
 
1481
   @note Like all the JTAG interface functions, this must not be called
1482
         re-entrantly while a call to any other function (e.g. or1kim_run ())
1483
         is in progress. It is the responsibility of the caller to ensure this
1484
         constraint is met, for example by use of a SystemC mutex.
1485
 
1486
   The register is represented as a vector of bytes, with the byte at offset
1487
   zero being shifted first, and the least significant bit in each byte being
1488
   shifted first. Where the register will not fit in an exact number of bytes,
1489
   the odd bits are in the highest numbered byte, shifted to the low end.
1490
 
1491
   The format is:
1492
 
1493
          +-------------+
1494
          |             |
1495
   TDI -> | Instruction | -> TDO
1496
          |             |
1497
          +-------------+
1498
                 4
1499
               bits
1500
 
1501
   With this debug interface, registers are shifted MS bit first, so we must
1502
   reverse the bits to get the actual value.
1503
 
1504
   We record the selected instruction. For completeness the register is parsed
1505
   and a warning given if any register other than DEBUG is shifted.
1506
 
1507
   @param[in,out] jreg  The register to shift in, and the register shifted
1508
                        back out.
1509
 
1510
   @return  The number of cycles the shift took, which in turn is the number
1511
            of bits in the register                                          */
1512
/*---------------------------------------------------------------------------*/
1513
int
1514
jtag_shift_ir (unsigned char *jreg)
1515
{
1516
  runtime.debug.instr = reverse_bits (jreg[0] & 0xf, 4);
1517
 
1518
  switch (runtime.debug.instr)
1519
    {
1520
    case JI_EXTEST:
1521
      fprintf (stderr, "Warning: JTAG EXTEST shifted\n");
1522
      break;
1523
 
1524
    case JI_SAMPLE_PRELOAD:
1525
      fprintf (stderr, "Warning: JTAG SAMPLE/PRELOAD shifted\n");
1526
      break;
1527
 
1528
    case JI_IDCODE:
1529
      fprintf (stderr, "Warning: JTAG IDCODE shifted\n");
1530
      break;
1531
 
1532
    case JI_DEBUG:
1533
      /* Do nothing for this one */
1534
      break;
1535
 
1536
    case JI_MBIST:
1537
      fprintf (stderr, "Warning: JTAG MBIST shifted\n");
1538
      break;
1539
 
1540
    case JI_BYPASS:
1541
      fprintf (stderr, "Warning: JTAG BYPASS shifted\n");
1542
      break;
1543
 
1544
    default:
1545
      fprintf (stderr, "Warning: Unknown JTAG instruction %04x shifted\n",
1546
               runtime.debug.instr);
1547
      break;
1548
    }
1549
 
1550
  return  4;                    /* Register length */
1551
 
1552
}       /* jtag_shift_ir () */
1553
 
1554
 
1555
/*---------------------------------------------------------------------------*/
1556
/*!Shift a JTAG data register
1557
 
1558
   @note Like all the JTAG interface functions, this must not be called
1559
         re-entrantly while a call to any other function (e.g. or1kim_run ())
1560
         is in progress. It is the responsibility of the caller to ensure this
1561
         constraint is met, for example by use of a SystemC mutex.
1562
 
1563
   The register is represented as a vector of bytes, with the byte at offset
1564
   zero being shifted first, and the least significant bit in each byte being
1565
   shifted first. Where the register will not fit in an exact number of bytes,
1566
   the odd bits are in the highest numbered byte, shifted to the low end.
1567
 
1568
   This is only meaningful if the DEBUG register instruction is already
1569
   selected. If not, the data register is rejected.
1570
 
1571
   The register is parsed to determine which of the six possible register
1572
   types it could be.
1573
   - MODULE_SELECT
1574
   - WRITE_COMMNAND
1575
   - READ_COMMAND
1576
   - GO_COMMAND
1577
   - WRITE_CONTROL
1578
   - READ_CONTROL
1579
 
1580
   @note In practice READ_COMMAND is not used. However the functionality is
1581
         provided for future compatibility.
1582
 
1583
   The parsing is hierarchical. The first bit determines if we have
1584
   MODULE_SELECT, if not, the next 4 bits determine the command.
1585
 
1586
   @param[in,out] jreg  The register to shift in, and the register shifted
1587
                        back out.
1588
 
1589
   @return  The number of cycles the shift took, which in turn is the number
1590
            of bits in the register                                          */
1591
/*---------------------------------------------------------------------------*/
1592
int
1593
jtag_shift_dr (unsigned char *jreg)
1594
{
1595
  if (JI_DEBUG != runtime.debug.instr)
1596
    {
1597
      fprintf (stderr, "ERROR: Attempt to shift JTAG data register when "
1598
               "DEBUG not instruction: ignored\n");
1599
      return  0;
1600
    }
1601
 
1602
  int  module_select_p = (1 == (jreg[0] & 0x1));
1603
 
1604
  if (module_select_p)
1605
    {
1606
      return  module_select (jreg);
1607
    }
1608
  else
1609
    {
1610
      enum jtag_cmd  cmd = reverse_bits ((jreg[0] >> 1) & 0xf, 4);
1611
 
1612
      switch (cmd)
1613
        {
1614
        case JCMD_GO_COMMAND:    return  go_command (jreg);
1615
        case JCMD_READ_COMMAND:  return  read_command (jreg);
1616
        case JCMD_WRITE_COMMAND: return  write_command (jreg);
1617
        case JCMD_READ_CONTROL:  return  read_control (jreg);
1618
        case JCMD_WRITE_CONTROL: return  write_control (jreg);
1619
 
1620
        default:
1621
          /* Not a command we recognize. Decide this after we've read just
1622
             the module and command bits */
1623
          return  4 + 1;
1624
        }
1625
    }
1626
}       /* jtag_shift_dr () */

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