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This is ../../or1ksim/doc/or1ksim.info, produced by makeinfo version
2
4.13 from ../../or1ksim/doc/or1ksim.texi.
3 19 jeremybenn
 
4
INFO-DIR-SECTION Embedded development
5
START-INFO-DIR-ENTRY
6
* Or1ksim: (or32-uclinux-or1ksim).      The OpenRISC 1000 Architectural
7
                                        Simulator
8
END-INFO-DIR-ENTRY
9
 
10
This file documents the OpenRISC Architectural Simulator, Or1ksim.
11
 
12
Copyright (C) 2008, 2009 Embecosm Limited.
13
 
14
     Permission is granted to copy, distribute and/or modify this
15
     document under the terms of the GNU Free Documentation License,
16
     Version 1.2 or any later version published by the Free Software
17
     Foundation; with no Invariant Sections, with no Front-Cover Texts,
18
     and with no Back-Cover Texts.  A copy of the license is included
19
     in the section entitled "GNU Free Documentation License".
20
 
21

22
File: or1ksim.info,  Node: Top,  Next: Installation,  Up: (dir)
23
 
24
Scope of this Document
25
**********************
26
 
27
This document is the user guide for Or1ksim, the OpenRISC 1000
28
Architectural Simulator.
29
 
30
* Menu:
31
 
32
* Installation::
33
* Usage::
34
* Configuration::
35
* Interactive Command Line::
36
* Verification API::
37
 
38
* Code Internals::
39
 
40
* GNU Free Documentation License::  The license for this documentation
41
* Index::
42
 
43

44
File: or1ksim.info,  Node: Installation,  Next: Usage,  Prev: Top,  Up: Top
45
 
46
1 Installation
47
**************
48
 
49
Installation follows standard GNU protocols.
50
 
51
* Menu:
52
 
53
* Preparation::
54
* Configuring the Build::
55
* Build and Install::
56
* Known Issues::
57
 
58

59
File: or1ksim.info,  Node: Preparation,  Next: Configuring the Build,  Up: Installation
60
 
61
1.1 Preparation
62
===============
63
 
64
Unpack the software and create a _separate_ directory in which to build
65
it:
66
 
67 230 jeremybenn
     tar jxf or1ksim-2010-08-01.tar.bz2
68 19 jeremybenn
     mkdir builddir_or1ksim
69
     cd builddir_or1ksim
70
 
71

72
File: or1ksim.info,  Node: Configuring the Build,  Next: Build and Install,  Prev: Preparation,  Up: Installation
73
 
74
1.2 Configuring the Build
75
=========================
76
 
77
Configure the software using the `configure' script in the main
78
directory.
79
 
80
The most significant argument is `--target', which should specify the
81 82 jeremybenn
OpenRISC 1000 32-bit architecture.  If this argument is omitted, it will
82 19 jeremybenn
default to OpenRISC 1000 32-bit with a warning
83
 
84 230 jeremybenn
     ../or1ksim-2010-08-01/configure --target=or32-uclinux ...
85 19 jeremybenn
 
86
There are several other options available, many of which are standard
87 82 jeremybenn
to GNU `configure' scripts.  Use `configure --help' to see all the
88
options.  The most useful is `--prefix' to specify a directory for
89 19 jeremybenn
installation of the tools.
90
 
91 104 jeremybenn
For testing (using `make check'), the `--target' parameter _must_ be
92
specified, to allow the target tool chain to be selected. If the tools
93
have been installed using the standard OpenRISC script, then this
94
should be set to `or32-elf'.
95 19 jeremybenn
 
96 104 jeremybenn
A number of Or1ksim specific features in the simulator do require
97
enabling at configuration.  These include
98
 
99 19 jeremybenn
`--enable-profiling'
100
`--disable-profiling'
101 82 jeremybenn
     If enabled, Or1ksim is compiled for profiling with `gprof'.  This
102
     is disabled by default.  Only really of value for developers of
103 19 jeremybenn
     Or1ksim.
104
 
105
`--enable-execution=simple'
106
`--enable-execution=complex'
107
`--enable-execution=dynamic'
108
     Or1ksim has developed to improve functionality and performance.
109
     This feature allows three versions of Or1ksim to be built
110
 
111
    `--enable-execution=simple'
112
          Build the original simple interpreting simulator
113
 
114
    `--enable-execution=complex'
115 82 jeremybenn
          Build a more complex interpreting simulator.  Experiments
116
          suggest this is 50% faster than the simple simulator.  This
117
          is the default.
118 19 jeremybenn
 
119
    `--enable-execution=dynamic'
120 82 jeremybenn
          Build a dynamically compiling simulator.  This is the way
121
          many modern ISS are built.  This represents a work in
122
          progress.  Currently Or1ksim will compile, but segfaults if
123
          configured with this option.
124 19 jeremybenn
 
125
 
126
     The default is `--enable-execution=complex'.
127
 
128
`--enable-ethphy'
129
`--disable-ethphy'
130
     If enabled, this option allows the Ethernet to be simulated by
131
     connecting via a socket (the alternative reads and writes, from
132 82 jeremybenn
     and to files).  This must then be configured using the relevant
133
     fields in the `ethernet' section of the configuration file.  *Note
134 19 jeremybenn
     Ethernet Configuration: Ethernet Configuration.
135
 
136
     The default is for this to be disabled.
137
 
138 127 jeremybenn
`--enable-unsigned-xori'
139
`--disable-unsigned-xori'
140
     Historically, `l.xori', has sign extended its operand. This is
141
     inconsistent with the other logical opcodes (`l.andi', `l.ori'),
142
     but in the absence of `l.not', it allows a register to be inverted
143
     in a single instruction using:
144
 
145
          `l.xori  rD,rA,-1'
146
 
147
     This flag causes Or1ksim to treat the immediate operand as
148
     unsigned (i.e to zero-extend rather than sign-extend).
149
 
150
     The default is to sign-extend, so that existing code will continue
151
     to work.
152
 
153
          Caution: The GNU compiler tool chain makes heavy use of this
154
          instruction.  Using unsigned behavior will require the
155
          compiler to be modified accordingly.
156
 
157
          This option is provided for experimentation.  A future
158
          version of OpenRISC may adopt this more consistent behavior
159
          and also provide a `l.not' opcode.
160
 
161 19 jeremybenn
`--enable-range-stats'
162
`--disable-range-stats'
163
     If enabled, this option allows statistics to be collected to
164 82 jeremybenn
     analyse register access over time.  The default is for this to be
165 19 jeremybenn
     disabled.
166
 
167
`--enable-debug'
168
`--disable-debug'
169
     This is a feature of the Argtable2 package used to process
170 82 jeremybenn
     arguments.  If enabled, some debugging features are turned on in
171
     Argtable2.  It is provided for completeness, but there is no
172
     reason why this feature should ever be needed by any Or1ksim user.
173 19 jeremybenn
 
174 82 jeremybenn
`--enable-all-tests'
175
`--disable-all-tests'
176
     Some of the tests (at the time of writing just one) will not
177
     compile without error.  If enabled with this flag, all test
178
     programs will be compiled with `make check'.
179 19 jeremybenn
 
180 82 jeremybenn
     This flag is intended for those working on the test package, who
181
     wish to get the missing test(s) working.
182
 
183
 
184 112 jeremybenn
A number of configuration flags have been removed since version 0.3.0,
185 124 jeremybenn
because they led to invalid behavior of Or1ksim. Those removed are:
186 112 jeremybenn
 
187 124 jeremybenn
`--enable-arith-flag'
188
`--disable-arith-flag'
189
     If enabled, this option caused certain instructions to set the flag
190
     (`F' bit) in the supervision register if the result were zero.
191
     The instructions affected by this were `l.add', `l.addc',
192
     `l.addi', `l.and' and `l.andi'.
193
 
194
     If set, this caused incorrect behavior. Whether or not flags are
195
     set is part of the OpenRISC 1000 architectural specification.  The
196
     only flags which should set this are the "set flag" instructions:
197
     `l.sfeq', `l.sfeqi', `l.sfges', `l.sfgesi', `l.sfgeu', `l.sfgeui',
198
     `l.sfgts', `l.sfgtsi', `l.sfgtu', `l.sfgtui', `l.sfles',
199
     `l.sflesi', `l.sfleu', `l.sfleui', `l.sflts', `l.sfltsi',
200
     `l.sfltu', `l.sfltui', `l.sfne' and `l.sfnei'.
201
 
202 112 jeremybenn
`--enable-ov-flag'
203
`--disable-ov-flag'
204 124 jeremybenn
     This flag caused certain instructions to set the overflow flag.
205
     If not, those instructions would not set the overflow flat.  The
206
     instructions affected by this were `l.add', `l.addc', `l.addi',
207
     `l.and', `l.andi', `l.div', `l.divu', `l.mul', `l.muli', `l.or',
208
     `l.ori', `l.sll', `l.slli', `l.srl', `l.srli', `l.sra', `l.srai',
209
     `l.sub', `l.xor' and `l.xori'.
210 112 jeremybenn
 
211
     This guaranteed incorrect behavior.  The OpenRISC 1000 architecture
212
     specification defines which flags are set by which instructions.
213
 
214
     Within the above list, the arithmetic instructions (`l.add',
215
     `l.addc', `l.addi', `l.div', `l.divu', `l.mul', `l.muli' and
216
     `l.sub'), together with `l.addic' which is missed out, set the
217
     overflow flag.  All the others (`l.and', `l.andi', `l.or',
218
     `l.ori', `l.sll', `l.slli', `l.srl', `l.srli', `l.sra', `l.srai',
219
     `l.xor' and `l.xori') do not.
220
 
221
 
222 19 jeremybenn

223
File: or1ksim.info,  Node: Build and Install,  Next: Known Issues,  Prev: Configuring the Build,  Up: Installation
224
 
225
1.3 Building and Installing
226
===========================
227
 
228 82 jeremybenn
Build the tool with:
229 19 jeremybenn
 
230
     make all
231 82 jeremybenn
 
232
If you have the OpenRISC tool chain and DejaGNU installed, you can
233
verify the tool as follows (otherwise omit this step):
234
 
235
     make check
236
 
237
Install the tool with:
238
 
239 19 jeremybenn
     make install
240
 
241
This will install the three variations of the Or1ksim tool,
242
`or32-uclinux-sim', `or32-uclinux-psim' and `or32-uclinux-mpsim', the
243
Or1ksim library, `libsim', the header file, `or1ksim.h' and this
244
documentation in `info' format.
245
 
246
     Note: Testing Or1ksim with `make check' is not yet supported.
247
 
248
The documentation may be created and installed in alternative formats
249
(PDF, Postscript, DVI, HTML) with for example:
250
 
251
     make pdf
252
     make install-pdf
253
 
254

255
File: or1ksim.info,  Node: Known Issues,  Prev: Build and Install,  Up: Installation
256
 
257
1.4 Known Problems and Issues
258
=============================
259
 
260 143 jeremybenn
The following problems and issues are known about with Or1ksim
261 230 jeremybenn
2010-08-01.  The OpenRISC tracker may be used to see the current state
262 143 jeremybenn
of these issues and to raise new problems and feature requests.  It may
263
be found at `http://www.opencores.org/ptracker.cgi/view/or1k/398'.
264 19 jeremybenn
 
265
   * The Supervision Register Little Endian Enable (LEE) bit is
266 82 jeremybenn
     ignored.  Or1ksim can be built for either little endian or big
267 19 jeremybenn
     endian use, but that behavior cannot be changed dynamically.
268
 
269
   * The NPC is a read/write register, but after being written it
270 82 jeremybenn
     clears the pipeline.  This means that if the processor is stalled,
271 19 jeremybenn
     the value should subsequently read back as 0, until the processor
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     is unstalled and able to refill its pipeline.  By default Or1ksim
273 19 jeremybenn
     always reports back the value of NPC, even when it has been
274
     written while stalled.
275
 
276
     There is now an option, `--strict-npc', which will enforce this
277 82 jeremybenn
     behavior.  At some stage in the future it will become the default
278 19 jeremybenn
     behavior, but for now it is an option, since its use will break
279
     GDB.
280
 
281
   * The memory components are given names in the configuration file.
282
     However there is currently no way for Or1ksim to report that name
283
     back to the user (for example to identify which memory block
284
     corresponds to a particular access).
285
 
286
   * Or1ksim allows the processor to be stalled (from the command
287 82 jeremybenn
     line), even if there is no debugger present.  This seems to be a
288 19 jeremybenn
     meaningless operation.
289
 
290
   * Or1ksim is not reentrant, so a program cannot instantiate multiple
291 82 jeremybenn
     instances using the library.  This is clearly a problem when
292
     considering multi-core applications.  However it stems from the
293
     original design, and can only be fixed by a complete rewrite.  The
294 19 jeremybenn
     entire source code uses static global constants liberally!
295
 
296 104 jeremybenn
   * There is no support for single precision floating point
297
     instructions in Or1ksim if configured in the CPU (*note CPU
298
     Configuration: CPU Configuration.).  These are implemented using
299
     the floating point support in the host C library, which will
300
     usually be IEEE 745 compliant.  There is at present no support for
301
     double precision floating point instructions, since these are
302
     meaningless with 32-bit registers.
303 19 jeremybenn
 
304 104 jeremybenn
     Floating point support within OpenRISC is intended to follow IEEE
305
     745, which offers a degree of configurability. However at present
306
     the FPSCR register is not supported, so there is no mechanism for
307
     configuring floating point behavior. Thus the default
308
     functionality of the host C library will be used.
309 19 jeremybenn
 
310 104 jeremybenn
   * The single precision floating point multiply and add instruction,
311
     `lf.madd.s', is not clearly specified in the original architectural
312
     manual. User should consult the `OpenRISC 1200 version 2
313
     Supplementary Programmer's Reference Manual' for a specification
314
     of the functionality implemented.
315
 
316
 
317 19 jeremybenn

318
File: or1ksim.info,  Node: Usage,  Next: Configuration,  Prev: Installation,  Up: Top
319
 
320
2 Usage
321
*******
322
 
323
* Menu:
324
 
325
* Standalone Simulator::
326
* Profiling Utility::
327
* Memory Profiling Utility::
328
* Simulator Library::
329
 
330

331
File: or1ksim.info,  Node: Standalone Simulator,  Next: Profiling Utility,  Up: Usage
332
 
333
2.1 Standalone Simulator
334
========================
335
 
336
The general form the standalone command is:
337
 
338
     or32-uclinux-sim [-vhi] [-f FILE] [--nosrv] [--srv=[N]] [-d STR]
339
                      [--enable-profile] [--enable-mprofile] [FILE]
340
 
341 82 jeremybenn
Many of the options have both a short and a long form.  For example
342
`-h' or `--help'.
343 19 jeremybenn
 
344
`-v'
345
`--version'
346
     Print out the version and copyright notice for Or1ksim and exit.
347
 
348
`-h'
349
`--help'
350
     Print out help about the command line options and what they mean.
351
 
352
`-f FILE'
353
`--file FILE'
354
     Read configuration commands from the specified file, looking first
355
     in the current directory, and otherwise in the `$HOME/.or1k'
356 82 jeremybenn
     directory.  If this argument is not specified, the file `sim.cfg'
357
     in those two locations is used.  Failure to find the file is a
358
     fatal error.  *Note Configuration: Configuration, for detailed
359
     information on configuring Or1ksim.
360 19 jeremybenn
 
361
`--nosrv'
362 82 jeremybenn
     Do not start up the debug server.  This overrides any setting
363
     specified in the configuration file.  This option may not be
364
     specified with `--srv'.  If it is, a rude message is printed and
365
     the `--nosrv' option is ignored.
366 19 jeremybenn
 
367
`--srv'
368
 
369
`--srv=N'
370 82 jeremybenn
     Start up the debug server.  If the parameter, N, is specified, use
371 19 jeremybenn
     that as the TCP/IP port for the server, otherwise a random value
372 82 jeremybenn
     from the private port range (41920-65535) will be used.  This
373
     option may not be specified with `--nosrv'.  If it is, a rude
374
     message is printed and the `--nosrv' option is ignored.
375 19 jeremybenn
 
376
`-d=CONFIG_STRING'
377
`--debug-config=CONFIG_STRING'
378 82 jeremybenn
     Enable selected debug messages in Or1ksim.  This parameter is for
379
     use by developers only, and is not covered further here.  See the
380 19 jeremybenn
     source code for more details.
381
 
382
`-i'
383
`--interactive'
384
     After starting, drop into the Or1ksim interactive command shell.
385
 
386
`--strict-npc'
387
     In real hardware, setting the next program counter (NPC, SPR 16),
388 82 jeremybenn
     flushes the processor pipeline.  The consequence of this is that
389
     until the pipeline refills, reading the NPC will return zero.
390
     This is typically the case when debugging, since the processor is
391 19 jeremybenn
     stalled.
392
 
393
     Historically, Or1ksim has always returned the value of the NPC,
394 82 jeremybenn
     irrespective of when it is changed.  If the `--strict-npc' option
395
     is used, then Or1ksim will mirror real hardware more accurately.
396
     If the NPC is changed while the processor is stalled, subsequent
397 19 jeremybenn
     reads of its value will return 0 until the processor is unstalled.
398
 
399
     This is not currently the default behavior, since tools such as
400
     GDB have been implemented assuming the historic Or1ksim behavior.
401
     However at some time in the future it will become the default.
402
 
403
`--enable-profile'
404
     Enable instruction profiling.
405
 
406
`--enable-mprofile'
407
     Enable memory profiling.
408
 
409
 
410

411
File: or1ksim.info,  Node: Profiling Utility,  Next: Memory Profiling Utility,  Prev: Standalone Simulator,  Up: Usage
412
 
413
2.2 Profiling Utility
414
=====================
415
 
416 82 jeremybenn
This utility analyses instruction profile data generated by Or1ksim.
417
It may be invoked as a standalone command, or from the Or1ksim CLI.
418
The general form the standalone command is:
419 19 jeremybenn
 
420
     or32-uclinux-profile [-vhcq] [-g=FILE]
421
 
422 82 jeremybenn
Many of the options have both a short and a long form.  For example
423
`-h' or `--help'.
424 19 jeremybenn
 
425
`-v'
426
`--version'
427
     Print out the version and copyright notice for the Or1ksim
428
     profiling utility and exit.
429
 
430
`-h'
431
`--help'
432
     Print out help about the command line options and what they mean.
433
 
434
`-c'
435
`--cumulative'
436
     Show cumulative sum of cycles in functions
437
 
438
`-q'
439
`--quiet'
440
     Suppress messages
441
 
442
`-g=FILE'
443
`--generate=FILE'
444 82 jeremybenn
     The data file to analyse.  If omitted, the default file,
445 19 jeremybenn
     `sim.profile' is used.
446
 
447
 
448

449
File: or1ksim.info,  Node: Memory Profiling Utility,  Next: Simulator Library,  Prev: Profiling Utility,  Up: Usage
450
 
451
2.3 Memory Profiling Utility
452
============================
453
 
454 82 jeremybenn
This utility analyses memory profile data generated by Or1ksim.  It may
455
be invoked as a standalone command, or from the Or1ksim CLI.  The
456 19 jeremybenn
general form the standalone command is:
457
 
458
     or32-uclinux-mprofile  [-vh] [-m=M] [-g=N] [-f=FILE] FROM TO
459
 
460 82 jeremybenn
Many of the options have both a short and a long form.  For example
461
`-h' or `--help'.
462 19 jeremybenn
 
463
`-v'
464
`--version'
465
     Print out the version and copyright notice for the Or1ksim memory
466
     profiling utility and exit.
467
 
468
`-h'
469
`--help'
470
     Print out help about the command line options and what they mean.
471
 
472
`-m=M'
473
`--mode=M'
474 82 jeremybenn
     Specify the mode out output.  Permitted options are
475 19 jeremybenn
 
476
    `detailed'
477
    `d'
478 82 jeremybenn
          Detailed output.  This is the default if no mode is specified.
479 19 jeremybenn
 
480
    `pretty'
481
    `p'
482
          Pretty printed output.
483
 
484
    `access'
485
    `a'
486
          Memory accesses only.
487
 
488
    `width'
489
    `w'
490
          Access width only.
491
 
492
 
493
`-g=N'
494
`--group=N'
495
     Group 2^n bits of successive addresses together.
496
 
497
`-f=FILE'
498
`--filename=FILE'
499 82 jeremybenn
     The data file to analyse.  If not specified, the default,
500 19 jeremybenn
     `sim.profile' is used.
501
 
502
`FROM'
503
`TO'
504
     FROM and TO are respectively the start and end address of the
505
     region of memory to be analysed.
506
 
507
 
508

509
File: or1ksim.info,  Node: Simulator Library,  Prev: Memory Profiling Utility,  Up: Usage
510
 
511
2.4 Simulator Library
512
=====================
513
 
514
Or1ksim may be used as a static of dynamic library, `libsim.a' or
515 82 jeremybenn
`libsim.so'.  When compiling with the static library, the flag, `-lsim'
516 19 jeremybenn
should be added to the link command.
517
 
518
The header file `or1ksim.h' contains appropriate declarations of the
519 82 jeremybenn
functions exported by the Or1ksim library.  These are:
520 19 jeremybenn
 
521 93 jeremybenn
 -- `or1ksim.h': int or1ksim_init (const char
522
     *CONFIG_FILE, const char *IMAGE_FILE, void *CLASS_PTR, int
523
     (*UPR)(void *CLASS_PTR, unsigned long int ADDR, unsigned char
524
     MASK[], unsigned char RDATA[], int DATA_LEN), int (*UPW)(void
525
     *CLASS_PTR, unsigned long int ADDR, unsigned char MASK[], unsigned
526
     char WDATA[], int DATA_LEN))
527
 
528 19 jeremybenn
     The initialization function is supplied with the name of a
529
     configuration file, CONFIG_FILE, an executable image, IMAGE_FILE,
530
     a pointer to the calling class, CLASS_PTR (since the library may
531
     be used from C++) and two up-call functions, one for reads, UPR,
532
     and one for writes, UPW.
533
 
534
     *Note Configuration: Configuration, for detailed information on
535
     configuring Or1ksim and the format of the configuration file.
536
 
537
     UPW is called for any write to an address external to the model
538 82 jeremybenn
     (determined by a `generic' section in the configuration file).
539
     UPR is called for any reads to an external address.  The CLASS_PTR
540
     is passed back with these upcalls, allowing the function to
541
     associate the call with the class which originally initialized the
542 93 jeremybenn
     library.  Both UPW and UPR should return zero on success and
543
     non-zero otherwise.  At the present time the meaning of non-zero
544
     values is not defined but this may change in the future.
545 19 jeremybenn
 
546 93 jeremybenn
     MASK indicates which bytes in the data are to be written or read.
547 82 jeremybenn
     Bytes to be read/written should have 0xff set in MASK.  Otherwise
548 93 jeremybenn
     the byte should be zero.  The adddress, ADDR, is the _full_
549
     address, since the upcall function must handle all generic
550
     devices, using the full address for decoding.
551 19 jeremybenn
 
552 93 jeremybenn
     Endianness is not completely transparent, since Or1ksim is
553
     transferring byte vectors, not multi-byte values.
554 19 jeremybenn
 
555 93 jeremybenn
          Caution: This is a change from version 0.3.0. It simplifies
556
          the interface, and makes Or1ksim more consistent with payload
557
          representation in SystemC TLM 2.0.
558 19 jeremybenn
 
559 93 jeremybenn
          Note: The current implementation of Or1ksim always transfers
560
          single words (4 bytes), using masks if smaller values are
561
          required.  In this it mimcs the behavior of the WishBone bus.
562
 
563
 
564 19 jeremybenn
 -- `or1ksim.h': int or1ksim_run (double DURATION)
565
     Run the simulator for the simulated duration specified (in
566
     seconds).
567
 
568
 
569
 -- `or1ksim.h': void or1ksim_reset_duration (double DURATION)
570
     Change the duration of a run specified in an earlier call to
571 82 jeremybenn
     `or1ksim_run'.  Typically this is called from an upcall, which
572 19 jeremybenn
     realizes it needs to change the duration of the run specified in
573
     the call to `or1ksim_run' that has been interrupted by the upcall.
574
 
575
     The time specified is the amount of time that the run must continue
576
     for (i.e the duration from _now_, not the duration from the
577
     original call to `or1ksim_run').
578
 
579
 
580
 -- `or1ksim.h': void or1ksim_set_time_point ()
581 82 jeremybenn
     Set a timing point.  For use with `or1ksim_get_time_period'.
582 19 jeremybenn
 
583
 
584
 -- `or1ksim.h': double or1ksim_get_time_period ()
585
     Return the simulated time (in seconds) that has elapsed since the
586
     last call to `or1ksim_set_time_point'.
587
 
588
 
589
 -- `or1ksim.h': int or1ksim_is_le ()
590
     Return 1 (logical true) if the Or1ksim simulation is
591
     little-endian, 0 otherwise.
592
 
593
 
594
 -- `or1ksim.h': unsigned long int or1ksim_clock_rate ()
595 82 jeremybenn
     Return the Or1ksim clock rate (in Hz).  This is the value
596
     specified in the configuration file.
597 19 jeremybenn
 
598
 
599
 -- `or1ksim.h': void or1ksim_interrupt (int I)
600 82 jeremybenn
     Generate an edge-triggered interrupt on interrupt line I.  The
601
     interrupt is then immediately cleared automatically.  A warning
602 19 jeremybenn
     will be generated and the interrupt request ignored if level
603
     sensitive interrupts have been configured with the programmable
604
     interrupt controller (*note Interrupt Configuration: Interrupt
605
     Configuration.).
606
 
607
 
608
 -- `or1ksim.h': void or1ksim_interrupt_set (int I)
609 82 jeremybenn
     Assert a level-triggered interrupt on interrupt line I.  The
610 19 jeremybenn
     interrupt must be cleared separately by an explicit call to
611 82 jeremybenn
     `or1ksim_interrupt_clear'.  A warning will be generated, and the
612 19 jeremybenn
     interrupt request ignored if edge sensitive interrupts have been
613
     configured with the programmable interrupt controller (*note
614
     Interrupt Configuration: Interrupt Configuration.).
615
 
616
 
617
 -- `or1ksim.h': void or1ksim_interrupt_clear (int I)
618
     Clear a level-triggered interrupt on interrupt line I, which was
619 82 jeremybenn
     previously asserted by a call to `or1ksim_interrupt_set'.  A
620 19 jeremybenn
     warning will be generated, and the interrupt request ignored if
621
     edge sensitive interrupts have been configured with the
622
     programmable interrupt controller (*note Interrupt Configuration:
623
     Interrupt Configuration.).
624
 
625
 
626 104 jeremybenn
 -- `or1ksim.h': double or1ksim_jtag_reset ()
627
     Drive a reset sequence through the JTAG interface. Return the
628
     (model) time taken for this action.  Remember that the JTAG has
629
     its own clock, which can be an order of magnitude slower than the
630
     main clock, so even a reset (5 JTAG cycles) could take 50
631
     processor clock cycles to complete.
632
 
633
 
634
 -- `or1ksim.h': double or1ksim_jtag_shift_ir (unsigned
635
     char *JREG, int NUM_BITS)
636
 
637
     Shift the supplied register through the JTAG instruction register.
638
     Return the (model) time taken for this action. The register is
639
     supplied as a byte vector, with the least significant bits in the
640
     least significant byte.  If the total number of bits is not an
641
     exact number of bytes, then the odd bits are found in the least
642
     significant end of the highest numbered byte.
643
 
644
     For example a 12-bit register would have bits 0-7 in byte 0 and
645
     bits 11-8 in the least significant 4 bits of byte 1.
646
 
647
 
648
 -- `or1ksim.h': double or1ksim_jtag_shift_dr (unsigned
649
     char *JREG, int NUM_BITS)
650
 
651
     Shift the supplied register through the JTAG data register.
652
     Return the (model) time taken for this action. The register is
653
     supplied as a byte vector, with the least significant bits in the
654
     least significant byte.  If the total number of bits is not an
655
     exact number of bytes, then the odd bits are found in the least
656
     significant end of the highest numbered byte.
657
 
658
     For example a 12-bit register would have bits 0-7 in byte 0 and
659
     bits 11-8 in the least significant 4 bits of byte 1.
660
 
661
 
662 19 jeremybenn
The libraries will be installed in the `lib' sub-directory of the main
663
installation directory (as specified with the `--prefix' option to the
664
`configure' script).
665
 
666
For example if the main installation directory is `/opt/or1ksim', the
667 82 jeremybenn
library will be found in the `/opt/or1ksim/lib' directory.  It is
668 19 jeremybenn
available as both a static library (`libsim.a') and a shared object
669
(`libsim.so').
670
 
671
To link against the library add the `-lsim' flag when linking and do
672
one of the following:
673
 
674
   * Add the library directory to the `LD_LIBRARY_PATH' environment
675 82 jeremybenn
     variable during execution.  For example:
676 19 jeremybenn
 
677
          export LD_LIBRARY_PATH=/opt/or1ksim/lib:$LD_LIBRARY_PATH
678
 
679
   * Add the library directory to the `LD_RUN_PATH' environment
680 82 jeremybenn
     variable during linking.  For example:
681 19 jeremybenn
 
682
          export LD_RUN_PATH=/opt/or1ksim/lib:$LD_RUN_PATH
683
 
684
   * Use the linker `--rpath' option and specify the library directory
685 82 jeremybenn
     when linking your program.  For example
686 19 jeremybenn
 
687 82 jeremybenn
          gcc ...  -Wl,--rpath -Wl,/opt/or1ksim/lib ...
688 19 jeremybenn
 
689
   * Add the library directory to `/etc/ld.so.conf'
690
 
691
 
692

693
File: or1ksim.info,  Node: Configuration,  Next: Interactive Command Line,  Prev: Usage,  Up: Top
694
 
695
3 Configuration
696
***************
697
 
698 82 jeremybenn
Or1ksim is configured through a configuration file.  This is specified
699 19 jeremybenn
through the `-f' parameter to the Or1ksim command, or passed as a
700 82 jeremybenn
string when initializing the Or1ksim library.  If no file is specified,
701
the default `sim.cfg' is used.  The file is looked for first in the
702 224 jeremybenn
current directory, then in the `$HOME/.or1ksim' directory of the user.
703 19 jeremybenn
 
704
* Menu:
705
 
706
* Configuration File Format::
707
* Simulator Configuration::
708
* Core OpenRISC Configuration::
709
* Peripheral Configuration::
710
 
711

712
File: or1ksim.info,  Node: Configuration File Format,  Next: Simulator Configuration,  Up: Configuration
713
 
714
3.1 Configuration File Format
715
=============================
716
 
717
The configuration file is a plain text file.
718
 
719
* Menu:
720
 
721
* Configuration File Preprocessing::
722
* Configuration File Syntax::
723
 
724

725
File: or1ksim.info,  Node: Configuration File Preprocessing,  Next: Configuration File Syntax,  Up: Configuration File Format
726
 
727
3.1.1 Configuration File Preprocessing
728
--------------------------------------
729
 
730 82 jeremybenn
The configuration file may include C style comments (i.e.  delimited by
731 19 jeremybenn
`/*' and `*/').
732
 
733

734
File: or1ksim.info,  Node: Configuration File Syntax,  Prev: Configuration File Preprocessing,  Up: Configuration File Format
735
 
736
3.1.2 Configuration File Syntax
737
-------------------------------
738
 
739
The configuration file is divided into a series of sections, with the
740
general form:
741
 
742
     section SECTION_NAME
743
 
744
       ...
745
 
746
     end
747
 
748
Sections may also have sub-sections within them (currently only the
749
ATA/ATAPI disc interface uses this).
750
 
751
Within a section, or sub-section are a series of parameter assignments,
752
one per line, withe the general form
753
 
754
       PARAMETER = VALUE
755
 
756
Depending on the parameter, the value may be a named value (an
757
enumeration), an integer (specified in any format acceptable in C) or a
758 82 jeremybenn
string in doubple quotes.  For flag parameters, the value 1 is used to
759
mean "true" or "on" and the value "0" to mean "false" or "off".  An
760 19 jeremybenn
example from a memory section shows each of these
761
 
762
     section memory
763
       type    = random
764
       pattern = 0x00
765
       name    = "FLASH"
766
       ...
767
     end
768
 
769
Many parameters are optional and take reasonable default values if not
770 82 jeremybenn
specified.  However there are some parameters (for example the `ce'
771 19 jeremybenn
parameter in `section memory') _must_ be specified.
772
 
773
Subsections are introduced by a keyword, with a parameter value (no `='
774 82 jeremybenn
sign), and end with the same keyword prefixed by `end'.  Thus the
775 19 jeremybenn
ATA/ATAPI inteface (`section ata') has a `device' subsection, thus:
776
 
777
     section ata
778
       ...
779
       device 0
780
         type    = 1
781
         file = "FILENAME"
782
         ...
783
       enddevice
784
       ...
785
     end
786
 
787
Some sections (for example `section sim') should appear only once.
788
Others (for example `section memory' may appear multiple times.
789
 
790
Sections may be omitted, _unless they contain parameters which are
791 82 jeremybenn
non-optional_.  If the section describes a part of the simulator which
792 19 jeremybenn
is optional (for example whether it has a UART), then that
793 82 jeremybenn
functionality will not be provided.  If the section describes a part of
794 19 jeremybenn
the simulator which is not optional (for example the CPU), then all the
795
parameters of that section will take their default values.
796
 
797
All optional parts of the functionality are always described by
798
sections including a `enabled' parameter, which can be set to 0 to
799
ensure that functionality is explicitly omitted.
800
 
801
Even if a section is disabled, all its parameters will be read and
802 82 jeremybenn
stored.  This is helpful if the section is subsequently enabled from
803
the Or1ksim command line (*note Interactive Command Line: Interactive
804 19 jeremybenn
Command Line.).
805
 
806
     Tip: It generally clearer to have sections describing _all_
807
     components, with omitted functionality explicitly indicated by
808
     setting the `enabled' parameter to 0
809
 
810
The following sections describe the various configuration sections and
811
the parameters which may be set in each.
812
 
813

814
File: or1ksim.info,  Node: Simulator Configuration,  Next: Core OpenRISC Configuration,  Prev: Configuration File Format,  Up: Configuration
815
 
816
3.2 Simulator Configuration
817
===========================
818
 
819
* Menu:
820
 
821
* Simulator Behavior::
822
* Verification API Configuration::
823
* CUC Configuration::
824
 
825

826
File: or1ksim.info,  Node: Simulator Behavior,  Next: Verification API Configuration,  Up: Simulator Configuration
827
 
828
3.2.1 Simulator Behavior
829
------------------------
830
 
831 82 jeremybenn
Simulator behavior is described in `section sim'.  This section should
832
appear only once.  The following parameters may be specified.
833 19 jeremybenn
 
834
`verbose = 0|1'
835 82 jeremybenn
     If 1 (true), print extra messages.  Default 0.
836 19 jeremybenn
 
837
`debug = 0-9'
838 82 jeremybenn
 
839
     higher the value the greater the number of messages.  Default 0.
840
     Negative values will be treated as 0 (with a warning).  Values
841
     that are too large will be treated as 9 (with a warning).
842 19 jeremybenn
 
843
`profile = 0|1'
844
     If 1 (true) generate a profiling file using the file specified in
845 82 jeremybenn
     the `prof_file' parameter or otherwise `sim.profile'.  Default 0.
846 19 jeremybenn
 
847
`prof_file = ``FILENAME'''
848 82 jeremybenn
     Specifies the file to be used with the `profile' parameter.
849
     Default `sim.profile'.  For backwards compatibility, the
850
     alternative name `prof_fn' is supported for this parameter, but
851
     deprecated.
852 19 jeremybenn
 
853
`mprofile = 0|1'
854
     If 1 (true) generate a memory profiling file using the file
855
     specified in the `mprof_file' parameter or otherwise
856 82 jeremybenn
     `sim.mprofile'.  Default 0.
857 19 jeremybenn
 
858
`mprof_fn = ``FILENAME'''
859
     Specifies the file to be used with the `mprofile' parameter.
860 82 jeremybenn
     Default `sim.mprofile'.  For backwards compatibility, the
861 19 jeremybenn
     alternative name `mprof_fn' is supported for this parameter, but
862
     deprecated.
863
 
864
`history = 0|1'
865 82 jeremybenn
     If 1 (true) track execution flow.  Default 0.
866 19 jeremybenn
 
867
          Note: Setting this parameter seriously degrades performance.
868
 
869
          Note: If this execution flow tracking is enabled, then
870
          `dependstats' must be enabled in the CPU configuration
871
          section (*note CPU Configuration: CPU Configuration.).
872
 
873
`exe_log = 0|1'
874 82 jeremybenn
     If 1 (true), generate an execution log.  Log is written to the
875
     file specified in parameter `exe_log_file'.  Default 0.
876 19 jeremybenn
 
877
          Note: Setting this parameter seriously degrades performance.
878
 
879
`exe_log_type = default|hardware|simple|software'
880
     Type of execution log to produce.
881
 
882
    `default'
883 82 jeremybenn
          Produce default output for the execution log.  In the current
884 19 jeremybenn
          implementation this is the equivalent of `hardware'.
885
 
886
    `hardware'
887
          After each instruction execution, log the number of
888
          instructions executed so far, the next instruction to execute
889
          (in hex), the general purpose registers (GPRs), status
890
          register, exception program counter, exception, effective
891
          address register and exception status register.
892
 
893
    `simple'
894
          After each instruction execution, log the number of
895
          instructions executed so far and the next instruction to
896
          execute, symbolically disassembled.
897
 
898
    `software'
899
          After each instruction execution, log the number of
900
          instructions executed so far and the next instruction to
901 82 jeremybenn
          execute, symbolically disassembled.  Also show the value of
902 19 jeremybenn
          each operand to the instruction.
903
 
904
 
905 82 jeremybenn
     Default value `hardware'.  Any unrecognized keyword (case
906 19 jeremybenn
     insensitive) will be treated as the default with a warning.
907
 
908
          Note: Execution logs can be _very_ big.
909
 
910
`exe_log_start = VALUE'
911 82 jeremybenn
     Address of the first instruction to start logging.  Default 0.
912 19 jeremybenn
 
913
`exe_log_end = VALUE'
914 82 jeremybenn
     Address of the last instruction to log.  Default no limit (i.e
915
     once started logging will continue until the simulator exits).
916 19 jeremybenn
 
917
`exe_log_marker = VALUE'
918
     Specifies the number of instructions between printing horizontal
919 82 jeremybenn
     markers.  Default is to produce no markers.
920 19 jeremybenn
 
921
`exe_log_file = FILENAME'
922
     Filename for the execution log filename if `exe_log' is enabled.
923 82 jeremybenn
     Default `executed.log'.  For backwards compatibility, the
924 19 jeremybenn
     alternative name `exe_log_fn' is supported for this parameter, but
925
     deprecated.
926
 
927 202 julius
`exe_bin_insn_log = 0|1'
928
     Enable logging of executed instructions to a file in binary
929
     format. This is helpful for off-line dynamic execution analysis.
930
 
931
          Note: Execution logs can be _very_ big. For example, while
932 220 jeremybenn
          booting the Linux kernel, version 2.6.34, a log file 1.2GB in
933
          size was generated.
934 202 julius
 
935
`exe_bin_insn_log_file = FILENAME'
936
     Filename for the binary execution log filename if
937
     `exe_bin_insn_log' is enabled.  Default `exe-insn.bin'.
938
 
939 19 jeremybenn
`clkcycle = VALUE[ps|ns|us|ms]'
940 82 jeremybenn
     Specify the time taken by one clock cycle.  If no units are
941
     specified, `ps' is assumed.  Default 4000ps (250MHz).
942 19 jeremybenn
 
943
 
944

945
File: or1ksim.info,  Node: Verification API Configuration,  Next: CUC Configuration,  Prev: Simulator Behavior,  Up: Simulator Configuration
946
 
947
3.2.2 Verification API (VAPI) Configuration
948
-------------------------------------------
949
 
950
The Verification API (VAPI) provides a TCP/IP interface to allow
951 82 jeremybenn
components of the simulation to be controlled externally.  *Note
952 19 jeremybenn
Verification API: Verification API, for more details.
953
 
954 82 jeremybenn
Verification API configuration is described in `section vapi'.  This
955
section may appear at most once.  The following parameters may be
956 19 jeremybenn
specified.
957
 
958
`enabled = 0|1'
959
     If 1 (true), verification API is enabled and its server started.
960
     If 0 (the default), it is disabled.
961
 
962
`server_port = VALUE'
963
     When VAPI is enabled, communication will be via TCP/IP on the port
964 82 jeremybenn
     specified by VALUE.  The value must lie in the range 1 to 65535.
965 19 jeremybenn
     The default value is 50000.
966
 
967 82 jeremybenn
          Tip: There is no registered port for Or1ksim VAPI.  Good
968 19 jeremybenn
          practice suggests users should adopt port values in the
969 82 jeremybenn
          "Dynamic" or "Private" port range, i.e.  49152-65535.
970 19 jeremybenn
 
971
`log_enabled = 0|1'
972
     If 1 (true), all VAPI requests and sent commands will be logged.
973 82 jeremybenn
     If 0 (the default), logging is diabled.  Logs are written to the
974 19 jeremybenn
     file specified by the `vapi_log_file' field (see below).
975
 
976
          Caution: This can generate a substantial amount of file I/O
977
          and seriously degrade simulator performance.
978
 
979
`hide_device_id = 0|1'
980 82 jeremybenn
     If 1 (true) don't log the device ID.  If 0 (the default), log the
981
     device ID.  This feature (when set to 1) is provided for backwards
982 19 jeremybenn
     compatibility with an old version of VAPI.
983
 
984
`vapi_log_file = "FILENAME"'
985
     Use `filename' as the file for logged data is logging is enabled
986 82 jeremybenn
     (see `log_enabled' above).  The default is `"vapi.log"'.  For
987 19 jeremybenn
     backwards compatibility, the alternative name `vapi_log_fn' is
988
     supported for this parameter, but deprecated.
989
 
990
 
991

992
File: or1ksim.info,  Node: CUC Configuration,  Prev: Verification API Configuration,  Up: Simulator Configuration
993
 
994
3.2.3 Custom Unit Compiler (CUC) Configuration
995
----------------------------------------------
996
 
997
The Custom Unit Compiler (CUC) was a project by Marko Mlinar to generate
998 82 jeremybenn
Verilog from ANSI C functions.  The project seems to not have progressed
999
beyond the initial prototype phase.  The configuration parameters are
1000 19 jeremybenn
described here for the record.
1001
 
1002 82 jeremybenn
CUC configuration is described in `section cuc'.  This section may
1003
appear at most once.  The following parameters may be specified.
1004 19 jeremybenn
 
1005
`memory_order = none|weak|strong|exact'
1006
     This parameter specifies the memory ordering required:
1007
 
1008
    `memory_order=none'
1009
          Different memory ordering, even if there are dependencies.
1010
          Bursts can be made, width can change.
1011
 
1012 82 jeremybenn
          Different memory ordering, even if there are dependencies.  If
1013 19 jeremybenn
          dependencies cannot occur, then bursts can be made, width can
1014
          change.
1015
 
1016 82 jeremybenn
          Same memory ordering.  Bursts can be made, width can change.
1017 19 jeremybenn
 
1018
          Exactly the same memory ordering and widths.
1019
 
1020
 
1021 82 jeremybenn
     The default value is `memory_order=exact'.  Invalid memory
1022 19 jeremybenn
     orderings are ignored with a warning.
1023
 
1024
`calling_convention = 0|1'
1025 82 jeremybenn
     If 1 (true), programs follow OpenRISC calling conventions.  If 0
1026 19 jeremybenn
     (the default), they may use other convenitions.
1027
 
1028
`enable_bursts = 0 | 1'
1029 82 jeremybenn
     If 1 (true), bursts are detected.  If 0 (the default), bursts are
1030 19 jeremybenn
     not detected.
1031
 
1032
`no_multicycle = 0 | 1'
1033 82 jeremybenn
     If 1 (true), no multicycle logic paths will be generated.  If 0
1034
     (the default), multicycle logic paths will be generated.
1035 19 jeremybenn
 
1036
`timings_file = "FILENAME"'
1037 82 jeremybenn
     FILENAME specifies a file containing timing information.  The
1038
     default value is `"virtex.tim"'.  For backwards compatibility, the
1039 19 jeremybenn
     alternative name `timings_fn' is supported for this parameter, but
1040
     deprecated.
1041
 
1042
 
1043

1044
File: or1ksim.info,  Node: Core OpenRISC Configuration,  Next: Peripheral Configuration,  Prev: Simulator Configuration,  Up: Configuration
1045
 
1046
3.3 Configuring the OpenRISC Architectural Components
1047
=====================================================
1048
 
1049
* Menu:
1050
 
1051
* CPU Configuration::
1052
* Memory Configuration::
1053
* Memory Management Configuration::
1054
* Cache Configuration::
1055
* Interrupt Configuration::
1056
* Power Management Configuration::
1057
* Branch Prediction Configuration::
1058
* Debug Interface Configuration::
1059
 
1060

1061
File: or1ksim.info,  Node: CPU Configuration,  Next: Memory Configuration,  Up: Core OpenRISC Configuration
1062
 
1063
3.3.1 CPU Configuration
1064
-----------------------
1065
 
1066 82 jeremybenn
CPU configuration is described in `section cpu'.  This section should
1067
appear only once.  At present Or1ksim does not model multi-CPU systems.
1068 19 jeremybenn
The following parameters may be specified.
1069
 
1070
`ver = VALUE'
1071
 
1072
`cfg = VALUE'
1073
 
1074
`rev = VALUE'
1075
     The values are used to form the corresponding fields in the `VR'
1076 82 jeremybenn
     Special Purpose Register (SPR 0).  Default values 0.  A warning is
1077 19 jeremybenn
     given and the value truncated if it is too large (8 bits for `ver'
1078
     and `cfg', 6 bits for `rev').
1079
 
1080
`upr = VALUE'
1081
     Used as the value of the Unit Present Register (UPR) Special
1082 82 jeremybenn
     Purpose Register (SPR 1) to VALUE.  Default value is 0x0000075f,
1083 19 jeremybenn
     i.e.
1084
        * UPR present (0x00000001)
1085
 
1086
        * Data cache present (0x00000002)
1087
 
1088
        * Instruction cache present (0x00000004)
1089
 
1090
        * Data MMY present (0x00000008)
1091
 
1092
        * Instruction MMU present (0x00000010)
1093
 
1094
        * Debug unit present (0x00000040)
1095
 
1096
        * Power management unit present (0x00000100)
1097
 
1098
        * Programmable interrupt controller present (0x00000200)
1099
 
1100
        * Tick timer present (0x00000400)
1101
 
1102
     However, with the exection of the UPR present (0x00000001) and tick
1103
     timer present, the various fields will be modified with the values
1104
     specified in their corresponding configuration sections.
1105
 
1106
`cfgr = VALUE'
1107
     Sets the CPU configuration register (Special Purpose Register 2) to
1108 82 jeremybenn
     VALUE.  Default value is 0x00000020, i.e.  support for the ORBIS32
1109
     instruction set.  Attempts to set any other value are accepted, but
1110 19 jeremybenn
     issue a warning that there is no support for the instruction set.
1111
 
1112
`sr = VALUE'
1113
     Sets the supervision register Special Purpose Register (SPR 0x11)
1114 82 jeremybenn
     to VALUE.  Default value is 0x00008001, i.e.  start in supervision
1115 19 jeremybenn
     mode (0x00000001) and set the "Fixed One" bit (0x00008000).
1116
 
1117 98 jeremybenn
          Note: This is particularly useful when an image is held in
1118
          Flash at high memory (0xf0000000).  The EPH  bit can be set,
1119
          so that interrupt vectors are basedf at 0xf0000000, rather
1120
          than 0x0.
1121
 
1122 19 jeremybenn
`superscalar = 0|1'
1123 82 jeremybenn
     If 1, the processor operates in superscalar mode.  Default value is
1124 19 jeremybenn
     0.
1125
 
1126
     In the current simulator, the only functional effect of superscalar
1127
     mode is to affect the calculation of the number of cycles taken to
1128
     execute an instruction.
1129
 
1130
          Caution: The code for this does not appear to be complete or
1131
          well tested, so users are advised not to use this option.
1132
 
1133
`hazards = 0|1'
1134 82 jeremybenn
     If 1, data hazards are tracked in a superscalar CPU.  Default
1135
     value is 0.
1136 19 jeremybenn
 
1137
     In the current simulator, the only functional effect is to cause
1138
     logging of hazard waiting information if the CPU is superscalar.
1139
     However nowhere in the simulator is this data actually computed,
1140
     so the net result is probably to have no effect.
1141
 
1142
     if harzards are tracked, current hazards can be displayed using the
1143
     simulator's `r' command.
1144
 
1145
          Caution: The code for this does not appear to be complete or
1146
          well tested, so users are advised not to use this option.
1147
 
1148
`dependstats = 0|1'
1149 82 jeremybenn
     If 1, inter-instruction dependencies are calculated.  Default
1150
     value 0.
1151 19 jeremybenn
 
1152
     If these values are calculated, the depencies can be displayed
1153
     using the simulator's `stat' command.
1154
 
1155
          Note: This field must be enabled, if execution execution flow
1156
          tracking (field `history') has been requested in the simulator
1157
          configuration section (*note Simulator Behavior: Simulator
1158
          Behavior.).
1159
 
1160
`sbuf_len = VALUE'
1161
     The length of the store buffer is set to VALUE, which must be no
1162 82 jeremybenn
     greater than 256.  Larger values will be truncated to 256 with a
1163
     warning.  Negative values will be treated as 0 with a warning.
1164
     Use 0 to disable the store buffer.
1165 19 jeremybenn
 
1166
     When the store buffer is active, stores are accumulated and
1167
     committed when I/O is idle.
1168
 
1169 100 julius
`hardfloat = 0|1'
1170
     If 1, hardfloat instructions are enabled. Default value 0.
1171 19 jeremybenn
 
1172 104 jeremybenn
 
1173 19 jeremybenn

1174
File: or1ksim.info,  Node: Memory Configuration,  Next: Memory Management Configuration,  Prev: CPU Configuration,  Up: Core OpenRISC Configuration
1175
 
1176
3.3.2 Memory Configuration
1177
--------------------------
1178
 
1179 82 jeremybenn
Memory configuration is described in `section memory'.  This section
1180 98 jeremybenn
may appear multiple times, specifying multiple blocks of memory.
1181 19 jeremybenn
 
1182 98 jeremybenn
     Caution: The user may choose whether or not to enable a memory
1183
     controller. If a memory controller is enabled, then the standard
1184
     OpenRISC C libraries will initialize it to expect 64MB memory
1185
     blocks, and any memory declarations _must_ reflect this.  The
1186
     section describing memory controller configuration describes the
1187
     steps necessary for using smaller or larger memory sections (*note
1188
     Memory Controller Configuration: Memory Controller Configuration.).
1189
 
1190
     If a memory controller is _not_ enabled, then the standard C
1191
     library code will generate memory access errors.  The solution is
1192
     to declare an additional writable memory block, mimicing the memory
1193
     controller's register bank as follows.
1194
 
1195
          section memory
1196
            pattern = 0x00
1197
            type = unknown
1198
            name = "MC shadow"
1199
            baseaddr = 0x93000000
1200
            size     = 0x00000080
1201
            delayr = 2
1202
            delayw = 4
1203
          end
1204
 
1205
 
1206
The following parameters may be specified.
1207
 
1208 19 jeremybenn
`type=random|pattern|unknown|zero'
1209 82 jeremybenn
     Specifies the values to which memory should be initialized.  The
1210 19 jeremybenn
     default value is `unknown'.
1211
 
1212
    `random'
1213 82 jeremybenn
          Set the memory values to be a random value.  A seed for the
1214 19 jeremybenn
          random generator may be set using the `random_seed' field in
1215
          this section (see below), thus ensuring the same "random"
1216
          values are used each time.
1217
 
1218
    `pattern'
1219
          Set the memory values to be a pattern value, which is set
1220
          using the `pattern' field in this section (see below).
1221
 
1222
    `unknown'
1223 82 jeremybenn
          The memory values are not initialized (i.e.  left "unknown").
1224 19 jeremybenn
          This option will yield faster initialization of the simulator.
1225
 
1226
    `zero'
1227 82 jeremybenn
          Set the memory values to be 0.  This is the equivalent of
1228 19 jeremybenn
          `type=pattern' and a `pattern' value of 0, and implemented as
1229
          such.
1230
 
1231
               Note: As a consequence, if the `pattern' field is
1232
               _subsequently_ specified in this section, the value in
1233
               that field will be used instead of zero to initialize
1234
               the memory.
1235
 
1236
 
1237
`random_seed = VALUE'
1238 82 jeremybenn
     Set the seed for the random number generator to VALUE.  This only
1239 19 jeremybenn
     has any effect for memory type `random'.
1240
 
1241
     The default value is -1, which means the seed will be set from a
1242
     call to the `time' function, thus ensuring different random values
1243 82 jeremybenn
     are used on each run.  The simulator prints out the seed used in
1244 19 jeremybenn
     this case, allowing repeat runs to regenerate the same random
1245
     values used in any particular run.
1246
 
1247
`pattern = VALUE'
1248 82 jeremybenn
     Set the pattern to be used when initializing memory to VALUE.  The
1249
     default value is 0.  This only has any effect for memory type
1250
     `pattern'.  The least significant 8 bits of this value is used to
1251
     initialize each byte.  More than 8 bits can be specified, but will
1252 19 jeremybenn
     ignored with a warning.
1253
 
1254
          Tip: The default value, is equivalent to setting the memory
1255 82 jeremybenn
          `type' to be `zero'.  If that is what is intended, then using
1256 19 jeremybenn
          `type=zero' explicitly is better than using `type=pattern'
1257
          and not specifying a value for `pattern'.
1258
 
1259
`baseaddr = VALUE'
1260 82 jeremybenn
     Set the base address of the memory to VALUE.  It should be aligned
1261 19 jeremybenn
     to a multiple of the memory size rounded up to the nearest 2^n.
1262
     The default value is 0.
1263
 
1264
`size = VALUE'
1265 82 jeremybenn
     Set the size of the memory block to be VALUE bytes.  This should
1266
     be a multiple of 4 (i.e.  word aligned).  The default value is
1267
     1024.
1268 19 jeremybenn
 
1269
          Note: When allocating memory, the simulator will allocate the
1270
          nearest 2^n bytes greater than or equal to VALUE, and will not
1271
          notice memory misses in any part of the memory between VALUE
1272
          and the amount allocated.
1273
 
1274
          As a consequence users are strongly recommended to specify
1275 82 jeremybenn
          memory sizes that are an exact power of 2.  If some other
1276 19 jeremybenn
          amount of memory is required, it should be specified as
1277
          separate, contiguous blocks, each of which is a power of 2 in
1278
          size.
1279
 
1280
`name = "TEXT"'
1281 82 jeremybenn
     Name the block.  Typically these describe the type of memory being
1282
     modeled (thus `"SRAM"' or `"Flash"'.  The default is
1283 19 jeremybenn
     `"anonymous memory block"'.
1284
 
1285
          Note: It is not clear that this information is currently ever
1286 82 jeremybenn
          used in normal operation of the simulator.  Even the `info'
1287 19 jeremybenn
          command of the simulator ignores it.
1288
 
1289
`ce = VALUE'
1290 82 jeremybenn
     Set the chip enable index of the memory instance.  Each memory
1291 19 jeremybenn
     instance should have a unique chip enable index, which should be
1292 82 jeremybenn
     greater than or equal to zero.  This is used by the memory
1293 19 jeremybenn
     controller when identifying different memory instances.
1294
 
1295 98 jeremybenn
     There is no requirement to set  `ce' if a memory controller is not
1296
     enabled. The default value is -1 (invalid).
1297 19 jeremybenn
 
1298
`mc = VALUE'
1299 82 jeremybenn
     Specifies the memory controller this memory is connected to.  It
1300 19 jeremybenn
     should correspond to the `index' field specified in a `section mc'
1301
     for a memory controller (*note Memory Controller Configuration:
1302
     Memory Controller Configuration.).
1303
 
1304 98 jeremybenn
     There is no requirement to set  `mc' if a memory controller is not
1305
     enabled. Default value is 0, which is also the default value of a
1306
     memory controller `index' field.  This is suitable therefore for
1307
     designs with just one memory controller.
1308 19 jeremybenn
 
1309
`delayr = VALUE'
1310 82 jeremybenn
     The number of cycles required for a read access.  Set to -1 if the
1311
     memory does not support reading.  Default value 1.  The simulator
1312 19 jeremybenn
     will add this number of cycles to the total instruction cycle
1313
     count when reading from main memory.
1314
 
1315
`delayw = VALUE'
1316 82 jeremybenn
     The number of cycles required for a write access.  Set to -1 if the
1317
     memory does not support writing.  Default value 1.  The simulator
1318 19 jeremybenn
     will add this number of cycles to the total instruction cycle
1319
     count when writing to main memory.
1320
 
1321
`log = "FILE"'
1322
     If specified, `file' names a file for all memory accesses to be
1323 82 jeremybenn
     logged.  If not specified, the default value, NULL is used, meaning
1324 19 jeremybenn
     that the memory is not logged.
1325
 
1326
 
1327

1328
File: or1ksim.info,  Node: Memory Management Configuration,  Next: Cache Configuration,  Prev: Memory Configuration,  Up: Core OpenRISC Configuration
1329
 
1330
3.3.3 Memory Management Configuration
1331
-------------------------------------
1332
 
1333
Memory Management Unit (MMU) configuration is described in `section
1334
dmmu' (for the data MMU) and `section immu' (for the instruction MMU).
1335 82 jeremybenn
Each section should appear at most once.  The following parameters may
1336 19 jeremybenn
be specified.
1337
 
1338
`enabled = 0|1'
1339
     If 1 (true), the data or instruction (as appropriate) MMU is
1340 82 jeremybenn
     enabled.  If 0 (the default), it is disabled.
1341 19 jeremybenn
 
1342
`nsets = VALUE'
1343
     Sets the number of data or instruction (as appropriate) TLB sets to
1344 82 jeremybenn
     VALUE, which must be a power of two, not exceeding 128.  Values
1345
     which do not fit these criteria are ignored with a warning.  The
1346 19 jeremybenn
     default value is 1.
1347
 
1348
`nways = VALUE'
1349
     Sets the number of data or instruction (as appropriate) TLB ways to
1350 82 jeremybenn
     VALUE.  The value must be in the range 1 to 4.  Values outside
1351
     this range are ignored with a warning.  The default value is 1.
1352 19 jeremybenn
 
1353
`pagesize = VALUE'
1354
     The data or instruction (as appropriate) MMU page size is set to
1355 82 jeremybenn
     VALUE, which must be a power of 2.  Values which are not a power
1356
     of 2 are ignored with a warning.  The default is 8192 (0x2000).
1357 19 jeremybenn
 
1358
`entrysize = VALUE'
1359
     The data or instruction (as appropriate) MMU entry size is set to
1360 82 jeremybenn
     VALUE, which must be a power of 2.  Values which are not a power
1361
     of 2 are ignored with a warning.  The default value is 1.
1362 19 jeremybenn
 
1363
          Note: Or1ksim does not appear to use the `entrysize' parameter
1364 82 jeremybenn
          in its simulation of the MMUs.  Thus setting this value does
1365 19 jeremybenn
          not seem to matter.
1366
 
1367
`ustates = VALUE'
1368
     The number of instruction usage states for the data or instruction
1369
     (as appropriate) MMU is set to VALUE, which must be 2, 3 or 4.
1370 82 jeremybenn
     Values outside this range are ignored with a warning.  The default
1371 19 jeremybenn
     value is 2.
1372
 
1373
          Note: Or1ksim does not appear to use the `ustates' parameter
1374 82 jeremybenn
          in its simulation of the MMUs.  Thus setting this value does
1375 19 jeremybenn
          not seem to matter.
1376
 
1377
`hitdelay = VALUE'
1378
     Set the number of cycles a data or instruction (as appropriate) MMU
1379 82 jeremybenn
     hit costs.  Default value 1.
1380 19 jeremybenn
 
1381
`missdelay = VALUE'
1382
     Set the number of cycles a data or instruction (as appropriate) MMU
1383 82 jeremybenn
     miss costs.  Default value 1.
1384 19 jeremybenn
 
1385
 
1386

1387
File: or1ksim.info,  Node: Cache Configuration,  Next: Interrupt Configuration,  Prev: Memory Management Configuration,  Up: Core OpenRISC Configuration
1388
 
1389
3.3.4 Cache Configuration
1390
-------------------------
1391
 
1392
Cache configuration is described in `section dc' (for the data cache)
1393 82 jeremybenn
and `seciton ic' (for the instruction cache).  Each section should
1394
appear at most once.  The following parameters may be specified.
1395 19 jeremybenn
 
1396
`enabled = 0|1'
1397
     If 1 (true), the data or instruction (as appropriate) cache is
1398 82 jeremybenn
     enabled.  If 0 (the default), it is disabled.
1399 19 jeremybenn
 
1400
`nsets = VALUE'
1401
     Sets the number of data or instruction (as appropriate) cache sets
1402
     to VALUE, which must be a power of two, not exceeding
1403
     `MAX_DC_SETS' (for the data cache) or `MAX_IC_SETS' (for the
1404 82 jeremybenn
     instruction cache).  At the time of writing, these constants are
1405
     both defined in the code to be 1024).  The default value is 1.
1406 19 jeremybenn
 
1407
`nways = VALUE'
1408
     Sets the number of data or instruction (as appropriate) cache ways
1409
     to VALUE, which must be a power of two, not exceeding
1410
     `MAX_DC_WAYS' (for the data cache) or `MAX_IC_WAYS' (for the
1411 82 jeremybenn
     instruction cache).  At the time of writing, these constants are
1412
     both defined in the code to be 32).  The default value is 1.
1413 19 jeremybenn
 
1414
`blocksize = VALUE'
1415
     The data or instruction (as appropriate) cache block size is set to
1416 82 jeremybenn
     VALUE bytes, which must be either 16 or 32.  The default is 16.
1417 19 jeremybenn
 
1418
`ustates = VALUE'
1419
     The number of instruction usage states for the data or instruction
1420
     (as appropriate) cache is set to VALUE, which must be 2, 3 or 4.
1421
     The default value is 2.
1422
 
1423
`hitdelay = VALUE'
1424 82 jeremybenn
     _Instruction cache only_.  Set the number of cycles an instruction
1425
     cache hit costs.  Default value 1.
1426 19 jeremybenn
 
1427
`missdelay = VALUE'
1428 82 jeremybenn
     _Instruction cache only_.  Set the number of cycles an instruction
1429
     cache miss costs.  Default value 1.
1430 19 jeremybenn
 
1431
`load_hitdelay = VALUE'
1432 82 jeremybenn
     _Data cache only_.  Set the number of cycles a data load cache hit
1433
     costs.  Default value 2.
1434 19 jeremybenn
 
1435
`load_missdelay = VALUE'
1436 82 jeremybenn
     _Data cache only_.  Set the number of cycles a data load cache
1437
     miss costs.  Default value 2.
1438 19 jeremybenn
 
1439
`store_hitdelay = VALUE'
1440 82 jeremybenn
     _Data cache only_.  Set the number of cycles a data store cache hit
1441
     costs.  Default value 0.
1442 19 jeremybenn
 
1443
`store_missdelay = VALUE'
1444 82 jeremybenn
     _Data cache only_.  Set the number of cycles a data store cache
1445
     miss costs.  Default value 0.
1446 19 jeremybenn
 
1447
 
1448

1449
File: or1ksim.info,  Node: Interrupt Configuration,  Next: Power Management Configuration,  Prev: Cache Configuration,  Up: Core OpenRISC Configuration
1450
 
1451
3.3.5 Interrupt Configuration
1452
-----------------------------
1453
 
1454
Programmable Interrupt Controller (PIC) configuration is described in
1455 82 jeremybenn
`section pic'.  This section may appear at most once--Or1ksim has no
1456
mechanism for handling multiple interrupt controllers.  The following
1457 19 jeremybenn
parameters may be specified.
1458
 
1459
`enabled = 0|1'
1460 82 jeremybenn
     If 1 (true), the programmable interrupt controller is enabled.  If
1461
 
1462 19 jeremybenn
 
1463
`edge_trigger = 0|1'
1464
     If 1 (true, the default), the programmable interrupt controller is
1465 82 jeremybenn
     edge triggered.  If 0 (false), it is level triggered.
1466 19 jeremybenn
 
1467
 
1468

1469
File: or1ksim.info,  Node: Power Management Configuration,  Next: Branch Prediction Configuration,  Prev: Interrupt Configuration,  Up: Core OpenRISC Configuration
1470
 
1471
3.3.6 Power Management Configuration
1472
------------------------------------
1473
 
1474 82 jeremybenn
Power management implementation is incomplete.  At present the effect
1475 19 jeremybenn
(which only happens when the power management unit is enabled) of
1476
setting the different bits in the power management Special Purpose
1477
Register (PMR, SPR 0x4000) is
1478
 
1479
`SDF (bit mask 0x0000000f)'
1480
     No effect - these bits are ignored
1481
 
1482
`DME (bit mask 0x00000010)'
1483
`SME (bit mask 0x00000020)'
1484
     Both these bits cause the processor to stop executing
1485 82 jeremybenn
     instructions.  However all other functions (debug interaction, CLI,
1486 19 jeremybenn
     VAPI etc) carry on as normal.
1487
 
1488
`DCGE (bit mask 0x00000004)'
1489
     No effect - this bit is ignored
1490
 
1491
`SUME (bit mask 0x00000008)'
1492
     Enabling this bit causes a message to be printed, advising that the
1493
     processor is suspending and the simulator exits.
1494
 
1495
 
1496
On reset all bits are cleared.
1497
 
1498 82 jeremybenn
Power management configuration is described in `section pm'.  This
1499
section may appear at most once.  The following parameter may be
1500 19 jeremybenn
specified.
1501
 
1502
`enabled = 0|1'
1503 82 jeremybenn
     If 1 (true), power management is enabled.  If 0 (the default), it
1504
     is disabled.
1505 19 jeremybenn
 
1506
 
1507

1508
File: or1ksim.info,  Node: Branch Prediction Configuration,  Next: Debug Interface Configuration,  Prev: Power Management Configuration,  Up: Core OpenRISC Configuration
1509
 
1510
3.3.7 Branch Prediction Configuration
1511
-------------------------------------
1512
 
1513
From examining the code base, it seems the branch prediction function
1514 82 jeremybenn
is not fully implemented.  At present the functionality seems
1515
restricted to collection of statistics.
1516 19 jeremybenn
 
1517 82 jeremybenn
Branch prediction configuration is described in `section bpb'.  This
1518
section may appear at most once.  The following parameters may be
1519 19 jeremybenn
specified.
1520
 
1521
`enabled = 0|1'
1522 82 jeremybenn
     If 1 (true), branch prediction is enabled.  If 0 (the default), it
1523 19 jeremybenn
     is disabled.
1524
 
1525
`btic = 0|1'
1526
     If 1 (true), the branch target instruction cache model is enabled.
1527
     If 0 (the default), it is disabled.
1528
 
1529
`sbp_bf_fwd = 0|1'
1530 82 jeremybenn
     If 1 (true), use forward prediction for the `l.bf' instruction.  If
1531 19 jeremybenn
 
1532
     instruction.
1533
 
1534
`sbp_bnf_fwd = 0|1'
1535 82 jeremybenn
     If 1 (true), use forward prediction for the `l.bnf' instruction.
1536
     If 0 (the default), do not use forward prediction for this
1537 19 jeremybenn
     instruction.
1538
 
1539
`hitdelay = VALUE'
1540 82 jeremybenn
     Set the number of cycles a branch prediction hit costs.  Default
1541 19 jeremybenn
     value 0.
1542
 
1543
`missdelay = VALUE'
1544 82 jeremybenn
     Set the number of cycles a branch prediction miss costs.  Default
1545 19 jeremybenn
     value 0.
1546
 
1547
 
1548

1549
File: or1ksim.info,  Node: Debug Interface Configuration,  Prev: Branch Prediction Configuration,  Up: Core OpenRISC Configuration
1550
 
1551
3.3.8 Debug Interface Configuration
1552
-----------------------------------
1553
 
1554
The debug unit and debug interface configuration is described in
1555 82 jeremybenn
`section debug'.  This section may appear at most once.  The following
1556 19 jeremybenn
parameters may be specified.
1557
 
1558
`enabled = 0|1'
1559 82 jeremybenn
     If 1 (true), the debug unit is enabled.  If 0 (the default), it is
1560 19 jeremybenn
     disabled.
1561
 
1562
          Note: This enables the functionality of the debug unit (its
1563 82 jeremybenn
          registers etc) within the mode.  It does not provide any
1564
          external interface to the debug unit.  For that, see
1565 19 jeremybenn
          `gdb_enabled' and `rsp_enabled' below.
1566
 
1567
`rsp_enabled = 0|1'
1568
     If 1 (true), the GDB "Remote Serial Protocol" server is started,
1569
     provding an interface to an external GNU debugger, using the port
1570
     specified in the `rsp_port' field (see below), or the
1571 82 jeremybenn
     `or1ksim-rsp' TCP/IP service.  If 0 (the default), the server is
1572 19 jeremybenn
     not started, and no external interface is provided.
1573
 
1574
     For more detailed information on the interface to the GNU Debugger
1575
     see Embecosm Application Note 2, `Howto: Porting the GNU Debugger
1576
     Practical Experience with the OpenRISC 1000 Architecture', by
1577
     Jeremy Bennett, published by Embecosm Limited (`www.embecosm.com').
1578
 
1579 82 jeremybenn
          Note: `rsp_enabled' may not be enabled with `gdb_enabled' (see
1580
          below).  If both are enabled, a warning is issued and only
1581
          the "Remote Serial Protocol" interface is enabled.
1582 19 jeremybenn
 
1583
`rsp_port = VALUE'
1584
     VALUE specifies the port to be used for the GDB "Remote Serial
1585 82 jeremybenn
     Protocol" interface to the GNU Debugger (GDB).  Default value
1586
     51000.  If the value 0 is specified, Or1ksim will instead look for
1587 19 jeremybenn
     a TCP/IP service named `or1ksim-rsp'.
1588
 
1589
          Tip: There is no registered port for Or1ksim "Remote Serial
1590 82 jeremybenn
          Protocol" service `or1ksim-rsp'.  Good practice suggests
1591
          users should adopt port values in the "Dynamic" or "Private"
1592
          port range, i.e.  49152-65535.
1593 19 jeremybenn
 
1594
`gdb_enabled = 0|1'
1595
     If 1 (true), the OpenRISC Remote JTAG protocol server is started,
1596
     provding an interface to an external GNU debugger, using the port
1597
     specified in the `server_port' field (see below), or the `or1ksim'
1598 82 jeremybenn
     TCP/IP service.  If 0 (the default), the server is not started,
1599
     and no external interface is provided.
1600 19 jeremybenn
 
1601
     For more detailed information on the interface to the GNU Debugger
1602
     see Embecosm Application Note 2, `Howto: Porting the GNU Debugger
1603
     Practical Experience with the OpenRISC 1000 Architecture', by
1604
     Jeremy Bennett, published by Embecosm Limited (`www.embecosm.com').
1605
 
1606
          Note: The OpenRISC Remote JTAG protocol is unique to
1607 82 jeremybenn
          OpenRISC, and remains only for backward compatibility.  New
1608 19 jeremybenn
          users should adopt the standard GDB "Remote Serial Protocol"
1609
          interface (see `rsp_enabled' above) providing access to a
1610
          wider range of GDB functionality.
1611
 
1612 82 jeremybenn
          Note: `gdb_enabled' may not be enabled with `rsp_enabled'.
1613
          If both are enabled, a warning is issued and only the "Remote
1614 19 jeremybenn
          Serial Protocol" interface is enabled.
1615
 
1616
`server_port = VALUE'
1617
     VALUE specifies the port to be used for the OpenRISC Rmote JTAG
1618 82 jeremybenn
     protocol interface to the GNU Debugger (GDB).  Default value
1619
     51000.  If the value 0 is specified, Or1ksim will instead look for
1620
     a TCP/IP service named `or1ksim'.
1621 19 jeremybenn
 
1622
          Tip: There is no registered port for Or1ksim Remote JTAG
1623 82 jeremybenn
          Interface or service `or1ksim'.  Good practice suggests users
1624 19 jeremybenn
          should adopt port values in the "Dynamic" or "Private" port
1625 82 jeremybenn
          range, i.e.  49152-65535.
1626 19 jeremybenn
 
1627
`vapi_id = VALUE'
1628
     VALUE specifies the value of the Verification API (VAPI) base
1629 82 jeremybenn
     address to be used with the debug unit.  *Note Verification API:
1630 19 jeremybenn
     Verification API, for more details.
1631
 
1632
     If this is specified and VALUE is non-zero, all OpenRISC Remote
1633
     JTAG protocol transactions will be logged to the VAPI log file, if
1634 82 jeremybenn
     enabled.  This is the only functionality associated with VAPI for
1635
     the debug unit.  No VAPI commands are sent, nor requests handled.
1636 19 jeremybenn
 
1637
 
1638

1639
File: or1ksim.info,  Node: Peripheral Configuration,  Prev: Core OpenRISC Configuration,  Up: Configuration
1640
 
1641
3.4 Configuring Memory Mapped Peripherals
1642
=========================================
1643
 
1644 82 jeremybenn
All peripheral components are optional.  If they are specified, then
1645 19 jeremybenn
(unlike other components) by default they are enabled.
1646
 
1647
* Menu:
1648
 
1649
* Memory Controller Configuration::
1650
* UART Configuration::
1651
* DMA Configuration::
1652
* Ethernet Configuration::
1653
* GPIO Configuration::
1654
* Display Interface Configuration::
1655
* Frame Buffer Configuration::
1656
* Keyboard Configuration::
1657
* Disc Interface Configuration::
1658
* Generic Peripheral Configuration::
1659
 
1660

1661
File: or1ksim.info,  Node: Memory Controller Configuration,  Next: UART Configuration,  Up: Peripheral Configuration
1662
 
1663
3.4.1 Memory Controller Configuration
1664
-------------------------------------
1665
 
1666
The memory controller used in Or1ksim is the component implemented at
1667 98 jeremybenn
OpenCores, and found in the top level SVN directory, `mem_ctrl'.  It is
1668 19 jeremybenn
described in the document `Memory Controller IP Core' by Rudolf
1669 82 jeremybenn
Usselmann, which can be found in the `doc' subdirectory.  It is a
1670
memory mapped component, which resides on the main OpenRISC Wishbone
1671
data bus.
1672 19 jeremybenn
 
1673 82 jeremybenn
The memory controller configuration is described in `section mc'.  This
1674 19 jeremybenn
section may appear multiple times, specifying multiple memory
1675 98 jeremybenn
controllers.
1676 19 jeremybenn
 
1677 98 jeremybenn
     Caution: The standard OpenRISC C libraries will initialize the
1678
     memory controller to expect 64MB memory blocks, and any memory
1679
     declarations _must_ reflect this.
1680
 
1681
     If smaller memory blocks are declared with a memory controller,
1682
     then sufficient memory will not be allocated by Or1ksim, but out of
1683
     range memory accesses will not be trapped. For example declaring a
1684
     memory section from 0-4MB with a memory controller enabled would
1685
     mean that accesses between 4MB and 64MB would be permitted, but
1686
     having no allocated memory would likely cause a segmentation fault.
1687
 
1688
     If the user is determined to use smaller memories with the memory
1689
     controller, then custom initialization code must be provided, to
1690
     ensure the memory controller traps out-of-memory accesses.
1691
 
1692
The following parameters may be specified.
1693
 
1694 19 jeremybenn
`enabled = 0|1'
1695 82 jeremybenn
     If 1 (true, the default), this memory controller is enabled.  If
1696
     0, it is disabled.
1697 19 jeremybenn
 
1698
          Note: The memory controller can effectively also be disabled
1699
          by setting an appropriate power on control register value
1700 82 jeremybenn
          (see below).  However this should only be used if it is
1701 19 jeremybenn
          desired to specifically model this behavior of the memory
1702
          controller, not as a way of disabling the memory controller
1703
          in general.
1704
 
1705
`baseaddr = VALUE'
1706
     Set the base address of the memory controller's memory mapped
1707 82 jeremybenn
     registers to VALUE.  The default is 0, which is probably not a
1708 19 jeremybenn
     sensible value.
1709
 
1710
     The memory controller has a 7 bit address bus, with a total of 19
1711
     32-bit registers, at addresses 0x00 through 0x4c (address 0x0c and
1712
     addresses 0x50 through 0x7c are not used).
1713
 
1714
`poc = VALUE'
1715
     Specifies the value of the power on control register, The least
1716
     signficant two bits specify the bus width (use 0 for an 8-bit bus,
1717
     1 for a 16-bit bus and 2 for a 32-bit bus) and the next two bits
1718
     the type of memory connected (use 0 for a disabled interface, 1
1719
     for SSRAM, 2 for asyncrhonous devices and 3 for synchronous
1720
     devices).
1721
 
1722
     If other bits are specified, they are ignored with a warning.
1723
 
1724
          Caution: The default value, 0, corresponds to a disabled
1725
          8-bit bus, and is likely not the most suitable value
1726
 
1727
`index = VALUE'
1728
     Specify the index of this memory controller amongst all the memory
1729 82 jeremybenn
     controllers.  This value should be unique for each memory
1730 19 jeremybenn
     controller, and is used to associate specific memories with the
1731
     controller, through the `mc' field in the `section memory'
1732
     configuration (*note Memory Configuration: Memory Configuration.).
1733
 
1734
     The default value, 0, is suitable when there is only one memory
1735
     controller.
1736
 
1737
 
1738

1739
File: or1ksim.info,  Node: UART Configuration,  Next: DMA Configuration,  Prev: Memory Controller Configuration,  Up: Peripheral Configuration
1740
 
1741
3.4.2 UART Configuration
1742
------------------------
1743
 
1744
The UART implemented in Or1ksim follows the specification of the
1745 82 jeremybenn
National Semiconductor 16450 and 16550 parts.  It is a memory mapped
1746 19 jeremybenn
component, which resides on the main OpenRISC Wishbone data bus.
1747
 
1748
The component provides a number of interfaces to emulate the behavior
1749
of an external terminal connected to the UART.
1750
 
1751 82 jeremybenn
UART configuration is described in `section uart'.  This section may
1752
appear multiple times, specifying multiple UARTs.  The following
1753 19 jeremybenn
parameters may be specified.
1754
 
1755
`enabled = 0|1'
1756 82 jeremybenn
     If 1 (true, the default), this UART is enabled.  If 0, it is
1757 19 jeremybenn
     disabled.
1758
 
1759
`baseaddr = VALUE'
1760
     Set the base address of the UART's memory mapped registers to
1761 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
1762 19 jeremybenn
 
1763
     The UART has a 3 bit address bus, with a total of 8 8-bit
1764
     registers, at addresses 0x0 through 0x7.
1765
 
1766
`channel = "TYPE:ARGS"'
1767
     Specify the channel representing the terminal connected to the UART
1768
     Rx & Tx pins.
1769
 
1770
    `channel="file:`rxfile',`txfile'"'
1771
          Read input characters from the file `rxfile' and write output
1772
          characters to the file `txfile' (which will be created if
1773
          required).
1774
 
1775
    `channel="xterm:ARGS"'
1776
          Create an xterm on startup, write UART Tx traffic to the
1777
          xterm and take Rx traffic from the keyboard when the xterm
1778 82 jeremybenn
          window is selected.  Additional arguments to the xterm
1779
          command (for example specifying window size may be specified
1780
          in ARGS, or this may be left blank.
1781 19 jeremybenn
 
1782
    `channel="tcp:VALUE"'
1783
          Open the TCP/IP port specified by VALUE and read and write
1784
          UART traffic from and to it.
1785
 
1786
          Typically a telnet session is connected to the other end of
1787
          this port.
1788
 
1789
               Tip: There is no registered port for Or1ksim telnet UART
1790 82 jeremybenn
               connection.  Priviledged access is required to read
1791 19 jeremybenn
               traffic on the registered "well-known" telnet port (23).
1792
               Instead users should use port values in the "Dynamic" or
1793 82 jeremybenn
               "Private" port range, i.e.  49152-65535.
1794 19 jeremybenn
 
1795
    `channel="fd:`rxfd',`txfd'"'
1796
          Read and write characters from and to the existing open
1797
          numerical file descriptors, file `rxfd' and `txfd'.
1798
 
1799
    `channel="tty:device=/dev/ttyS0,baud=9600"'
1800
          Read and write characters from and to a physical serial port.
1801
          The precise device (shown here as `/dev/ttyS0') may vary from
1802
          machine to machine.
1803
 
1804
 
1805
     The default value for this field is `"xterm:"'.
1806
 
1807
`irq = VALUE'
1808 82 jeremybenn
     Use VALUE as the IRQ number of this UART.  Default value 0.
1809 19 jeremybenn
 
1810
`16550 = 0|1'
1811 82 jeremybenn
     If 1 (true), the UART has the functionality of a 16550.  If 0 (the
1812
     default), it has the functionality of a 16450.  The principal
1813 19 jeremybenn
     difference is that the 16550 can buffer multiple characters.
1814
 
1815
`jitter = VALUE'
1816
     Set the jitter, modeled as a time to block, to VALUE milliseconds.
1817 82 jeremybenn
     Set to -1 to disable jitter modeling.  Default value 0.
1818 19 jeremybenn
 
1819
          Note: This functionality has yet to be implemented, so this
1820
          parameter has no effect.
1821
 
1822
`vapi_id = VALUE'
1823
     VALUE specifies the value of the Verification API (VAPI) base
1824 82 jeremybenn
     address to be used with the UART.  *Note Verification API:
1825 19 jeremybenn
     Verification API, for more details, which details the use of the
1826
     VAPI with the UART.
1827
 
1828
 
1829

1830
File: or1ksim.info,  Node: DMA Configuration,  Next: Ethernet Configuration,  Prev: UART Configuration,  Up: Peripheral Configuration
1831
 
1832
3.4.3 DMA Configuration
1833
-----------------------
1834
 
1835
The DMA controller used in Or1ksim is the component implemented at
1836 98 jeremybenn
OpenCores, and found in the top level SVN directory, `wb_dma'.  It is
1837 19 jeremybenn
described in the document `Wishbone DMA/Bridge IP Core' by Rudolf
1838 82 jeremybenn
Usselmann, which can be found in the `doc' subdirectory.  It is a
1839
memory mapped component, which resides on the main OpenRISC Wishbone
1840
data bus.  The present implementation is incomplete, intended only to
1841
support the Ethernet interface (*note Ethernet Configuration::),
1842
although the Ethernet interface is not yet completed.
1843 19 jeremybenn
 
1844 82 jeremybenn
DMA configuration is described in `section dma'.  This section may
1845
appear multiple times, specifying multiple DMA controllers.  The
1846 19 jeremybenn
following parameters may be specified.
1847
 
1848
`enabled = 0|1'
1849 82 jeremybenn
     If 1 (true, the default), this DMA controller is enabled.  If 0,
1850
     it is disabled.
1851 19 jeremybenn
 
1852
`baseaddr = VALUE'
1853
     Set the base address of the DMA's memory mapped registers to
1854 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
1855 19 jeremybenn
 
1856
     The DMA controller has a 10 bit address bus, with a total of 253
1857 82 jeremybenn
     32-bit registers.  The first 5 registers at addresses 0x000 through
1858
     0x010 control the overall behavior of the DMA controller.  There
1859
     are then 31 blocks of 8 registers, controlling each of the 31 DMA
1860
     channels available.  Addresses 0x014 through 0x01c are not used.
1861 19 jeremybenn
 
1862
`irq = VALUE'
1863 82 jeremybenn
     Use VALUE as the IRQ number of this DMA controller.  Default value
1864 19 jeremybenn
     0.
1865
 
1866
`vapi_id = VALUE'
1867
     VALUE specifies the value of the Verification API (VAPI) base
1868 82 jeremybenn
     address to be used with the DMA controller.  *Note Verification
1869 19 jeremybenn
     API: Verification API, for more details, which details the use of
1870
     the VAPI with the DMA controller.
1871
 
1872
 
1873

1874
File: or1ksim.info,  Node: Ethernet Configuration,  Next: GPIO Configuration,  Prev: DMA Configuration,  Up: Peripheral Configuration
1875
 
1876
3.4.4 Ethernet Configuration
1877
----------------------------
1878
 
1879
The Ethernet MAC used in Or1ksim is the component implemented at
1880 98 jeremybenn
OpenCores, and found in the top level SVN directory, `ethmac'.  It also
1881
forms part of the OpenRISC SoC, ORPSoC.  It is described in the
1882 19 jeremybenn
document `Ethernet IP Core Specification' by Igor Mohor, which can be
1883 82 jeremybenn
found in the `doc' subdirectory.  It is a memory mapped component,
1884
which resides on the main OpenRISC Wishbone data bus.
1885 19 jeremybenn
 
1886 82 jeremybenn
Ethernet configuration is described in `section ethernet'.  This
1887
section may appear multiple times, specifying multiple Ethernet
1888
interfaces.  The following parameters may be specified.
1889 19 jeremybenn
 
1890
`enabled = 0|1'
1891 82 jeremybenn
     If 1 (true, the default), this Ethernet MAC is enabled.  If 0, it
1892
     is disabled.
1893 19 jeremybenn
 
1894
`baseaddr = VALUE'
1895
     Set the base address of the MAC's memory mapped registers to
1896 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
1897 19 jeremybenn
 
1898
     The Ethernet MAC has a 7-bit address bus, with a total of 21
1899 82 jeremybenn
     32-bit registers.  Addresses 0x54 through 0x7c are not used.
1900 19 jeremybenn
 
1901
          Note: The Ethernet specification describes a Tx control
1902 82 jeremybenn
          register, `TXCTRL', at address 0x50.  However this register
1903
          is not implemented in the Or1ksim model.
1904 19 jeremybenn
 
1905
`dma = VALUE'
1906
     VALUE specifies the DMA controller with which this Ethernet is
1907 82 jeremybenn
     associated.  The default value is 0.
1908 19 jeremybenn
 
1909
          Note: Support for external DMA is not provided in the current
1910 82 jeremybenn
          implementation, and this value is ignored.  In any case there
1911 19 jeremybenn
          is no equivalent field to which this can be matched in the
1912
          current DMA component implementation (*note DMA
1913
          Configuration: DMA Configuration.).
1914
 
1915
`irq = VALUE'
1916 82 jeremybenn
     Use VALUE as the IRQ number of this Ethernet MAC.  Default value 0.
1917 19 jeremybenn
 
1918
`rtx_type = 0|1'
1919
     If 1 (true) use a socket interface to the Ethernet (see parameter
1920 82 jeremybenn
     `sockif' below).  If 0 (the default), use a file interface,
1921
     reading and writing from and to the files specified in the
1922
     `rxfile' and `txfile' parameters (see below).
1923 19 jeremybenn
 
1924
          Note: By default the socket interface is not provided in
1925 82 jeremybenn
          Or1ksim.  If it is required, this must be requested when
1926 19 jeremybenn
          configuring, by use of the `--enable-ethphy' option to
1927
          `configure'.
1928
 
1929
               configure --target=or32-uclinux --enable-ethphy ...
1930
 
1931
`rx_channel = RXVALUE'
1932
`tx_channel = TXVALUE'
1933
     RXVALUE specifies the DMA channel to use for receive and TXVALUE
1934 82 jeremybenn
     the DMA channel to use for transmit.  Both default to 0.
1935 19 jeremybenn
 
1936
          Note: As noted above, support for external DMA is not
1937
          provided in the current implementation, and so these values
1938
          are ignored.
1939
 
1940
`rxfile = "RXFILE"'
1941
`txfile = "TXFILE"'
1942
     When `rtx_type' is 0 (see above), RXFILE specifies the file to use
1943
     as input and TXFILE specifies the fie to use as output.
1944
 
1945 82 jeremybenn
     The file contains a sequence of packets.  Each packet consists of a
1946
     packet length (32 bits), followed by that many bytes of data.
1947
     Once the input file is empty, the Ethernet MAC behaves as though
1948
     there were no data on the Ethernet.  The default values of these
1949 19 jeremybenn
     parameters are `"eth_rx"' and `"eth_tx"' respectively.
1950
 
1951 82 jeremybenn
     The input file must exist and be readable.  The output file must be
1952
     writable and will be created if necessary.  If either of these
1953 19 jeremybenn
     conditions is not met, a warning will be given.
1954
 
1955
`sockif = "SERVICE"'
1956
     When `rtx_type' is 1 (see above), SERVICE specifies the service to
1957 82 jeremybenn
     use for communication.  This may be TCP/IP or UDP/IP.  The default
1958 19 jeremybenn
     value of this parameter is `"or1ksim_eth"'.
1959
 
1960
`vapi_id = VALUE'
1961
     VALUE specifies the value of the Verification API (VAPI) base
1962 82 jeremybenn
     address to be used with the Ethernet PHY.  *Note Verification API:
1963 19 jeremybenn
     Verification API, for more details, which details the use of the
1964
     VAPI with the DMA controller.
1965
 
1966
 
1967

1968
File: or1ksim.info,  Node: GPIO Configuration,  Next: Display Interface Configuration,  Prev: Ethernet Configuration,  Up: Peripheral Configuration
1969
 
1970
3.4.5 GPIO Configuration
1971
------------------------
1972
 
1973
The GPIO used in Or1ksim is the component implemented at OpenCores, and
1974 98 jeremybenn
found in the top level SVN directory, `gpio'.  It is described in the
1975 19 jeremybenn
document `GPIO IP Core Specification' by Damjan Lampret and Goran
1976 82 jeremybenn
Djakovic, which can be found in the `doc' subdirectory.  It is a memory
1977 19 jeremybenn
mapped component, which resides on the main OpenRISC Wishbone data bus.
1978
 
1979 82 jeremybenn
GPIO configuration is described in `section gpio'.  This section may
1980
appear multiple times, specifying multiple GPIO devices.  The following
1981 19 jeremybenn
parameters may be specified.
1982
 
1983
`enabled = 0|1'
1984 82 jeremybenn
     If 1 (true, the default), this GPIO is enabled.  If 0, it is
1985 19 jeremybenn
     disabled.
1986
 
1987
`baseaddr = VALUE'
1988
     Set the base address of the GPIO's memory mapped registers to
1989 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
1990 19 jeremybenn
 
1991
     The GPIO has a 6 bit address bus, with a total of 10 32-bit
1992
     registers, although the number of bits that are actively used
1993 82 jeremybenn
     varies.  Addresses 0x28 through 0x3c are not used.
1994 19 jeremybenn
 
1995
`irq = VALUE'
1996 82 jeremybenn
     Use VALUE as the IRQ number of this GPIO.  Default value 0.
1997 19 jeremybenn
 
1998
`vapi_id = VALUE'
1999
     VALUE specifies the value of the Verification API (VAPI) base
2000 82 jeremybenn
     address to be used with the GPIO.  *Note Verification API:
2001 19 jeremybenn
     Verification API, for more details, which details the use of the
2002 82 jeremybenn
     VAPI with the GPIO controller.  For backwards compatibility, the
2003 19 jeremybenn
     alternative name `base_vapi_id' is supported for this parameter,
2004
     but deprecated.
2005
 
2006
 
2007

2008
File: or1ksim.info,  Node: Display Interface Configuration,  Next: Frame Buffer Configuration,  Prev: GPIO Configuration,  Up: Peripheral Configuration
2009
 
2010
3.4.6 Display Interface Configuration
2011
-------------------------------------
2012
 
2013
Or1ksim models a VGA interface to an external monitor.  The VGA
2014
controller used in Or1ksim is the component implemented at OpenCores,
2015 98 jeremybenn
and found in the top level SVN directory, `vga_lcd', with no support
2016 82 jeremybenn
for the optional hardware cursors.  It is described in the document
2017 19 jeremybenn
`VGA/LCD Core v2.0 Specifications' by Richard Herveille, which can be
2018 82 jeremybenn
found in the `doc' subdirectory.  It is a memory mapped component,
2019
which resides on the main OpenRISC Wishbone data bus.
2020 19 jeremybenn
 
2021
The current implementation provides only functionality to dump the
2022
screen to a file at intervals.
2023
 
2024 82 jeremybenn
VGA controller configuration is described in `section vga'.  This
2025 19 jeremybenn
section may appear multiple times, specifying multiple VGA controllers.
2026
The following parameters may be specified.
2027
 
2028
`enabled = 0|1'
2029 82 jeremybenn
     If 1 (true, the default), this VGA is enabled.  If 0, it is
2030 19 jeremybenn
     disabled.
2031
 
2032
`baseaddr = VALUE'
2033
     Set the base address of the VGA controller's memory mapped
2034 82 jeremybenn
     registers to VALUE.  The default is 0, which is probably not a
2035 19 jeremybenn
     sensible value.
2036
 
2037
     The VGA controller has a 12-bit address bus, with 7 32-bit
2038
     registers, at addresses 0x000 through 0x018, and two color lookup
2039 82 jeremybenn
     tables at addresses 0x800 through 0xfff.  The hardware cursor
2040 19 jeremybenn
     registers are not implemented, so addresses 0x01c through 0x7fc
2041
     are not used.
2042
 
2043
`irq = VALUE'
2044 82 jeremybenn
     Use VALUE as the IRQ number of this VGA controller.  Default value
2045 19 jeremybenn
     0.
2046
 
2047
`refresh_rate = VALUE'
2048 82 jeremybenn
     VALUE specifies number of cycles between screen dumps.  Default
2049 19 jeremybenn
     value is derived from the simulation clock cycle time (*note
2050
     Simulator Behavior: Simulator Behavior.), to correspond to dumping
2051
     50 times per simulated second.
2052
 
2053
`txfile = "FILE"'
2054
     FILE specifies the base of the filename for screen dumps.
2055
     Successive screen dumps will be in BMP format, in files with the
2056
     name `FILENNNN.bmp', where NNNN is a sequential count of the
2057 82 jeremybenn
     screen dumps starting at zero.  The default value is `"vga_out"'.
2058 19 jeremybenn
     For backwards compatibility, the alternative name `filename' is
2059
     supported for this parameter, but deprecated.
2060
 
2061
 
2062

2063
File: or1ksim.info,  Node: Frame Buffer Configuration,  Next: Keyboard Configuration,  Prev: Display Interface Configuration,  Up: Peripheral Configuration
2064
 
2065
3.4.7 Frame Buffer Configuration
2066
--------------------------------
2067
 
2068 82 jeremybenn
     Caution: The frame buffer is only partially implemented.  Its
2069 19 jeremybenn
     configuration fields are described here, but the component should
2070 82 jeremybenn
     not be used at this time.  Like the VGA controller, it is designed
2071 19 jeremybenn
     to make screen dumps to file.
2072
 
2073 82 jeremybenn
Frame buffer configuration is described in `section fb'.  This section
2074
may appear multiple times, specifying multiple frame buffers.  The
2075 19 jeremybenn
following parameters may be specified.
2076
 
2077
`enabled = 0|1'
2078 82 jeremybenn
     If 1 (true, the default), this frame buffer is enabled.  If 0, it
2079 19 jeremybenn
     is disabled.
2080
 
2081
`baseaddr = VALUE'
2082
     Set the base address of the frame buffer's memory mapped registers
2083 82 jeremybenn
     to VALUE.  The default is 0, which is probably not a sensible
2084
     value.
2085 19 jeremybenn
 
2086
     The frame buffer has an 121-bit address bus, with 4 32-bit
2087
     registers, at addresses 0x000 through 0x00c, and a PAL lookup
2088 82 jeremybenn
     table at addresses 0x400 through 0x4ff.  Addresses 0x010 through
2089 19 jeremybenn
     0x3fc and addresses 0x500 through 0x7ff are not used.
2090
 
2091
`refresh_rate = VALUE'
2092 82 jeremybenn
     VALUE specifies number of cycles between screen dumps.  Default
2093 19 jeremybenn
     value is derived from the simulation clock cycle time (*note
2094
     Simulator Behavior: Simulator Behavior.), to correspond to dumping
2095
     50 times per simulated second.
2096
 
2097
`txfile = "FILE"'
2098
     FILE specifies the base of the filename for screen dumps.
2099
     Successive screen dumps will be in BMP format, in files with the
2100
     name `FILENNNN.bmp', where NNNN is a sequential count of the
2101 82 jeremybenn
     screen dumps starting at zero.  The default value is `"fb_out"'.
2102 19 jeremybenn
     For backwards compatibility, the alternative name `filename' is
2103
     supported for this parameter, but deprecated.
2104
 
2105
 
2106

2107
File: or1ksim.info,  Node: Keyboard Configuration,  Next: Disc Interface Configuration,  Prev: Frame Buffer Configuration,  Up: Peripheral Configuration
2108
 
2109
3.4.8 Keyboard Configuration (PS2)
2110
----------------------------------
2111
 
2112 82 jeremybenn
The PS2 interface provided by Or1ksim is not documented.  It may be
2113 98 jeremybenn
based on the PS2 project at OpenCores, and found in the top level SVN
2114 82 jeremybenn
directory, `ps2'.  However this project lacks any documentation beyond
2115
its project webpage.  Since most PS2 interfaces follow the Intel i8042
2116 19 jeremybenn
standard, this is presumably what is expected with this device.
2117
 
2118
The implementation only provides for keyboard support, which is
2119 82 jeremybenn
modelled as a file of keystrokes.  There is no mouse support.
2120 19 jeremybenn
 
2121
     Caution: A standard i8042 device has two registers at addresses
2122 82 jeremybenn
     0x60 (command) and 0x64 (status).  Inspection of the code,
2123
     suggests that the Or1ksim component places these registers at
2124
     addresses 0x00 and 0x04.
2125 19 jeremybenn
 
2126
     The port of Linux for the OpenRISC 1000, which runs on Or1ksim
2127
     implements the i8042 device driver, anticipating these registers
2128 82 jeremybenn
     reside at their conventional address.  It seems unlikel that this
2129 19 jeremybenn
     code will work.
2130
 
2131
     This component should be used with caution.
2132
 
2133 82 jeremybenn
Keyboard configuration is described in `section kbd'.  This section may
2134
appear multiple times, specifying multiple keyboard interfaces.  The
2135 19 jeremybenn
following parameters may be specified.
2136
 
2137
`enabled = 0|1'
2138 82 jeremybenn
     If 1 (true, the default), this keyboard is enabled.  If 0, it is
2139 19 jeremybenn
     disabled.
2140
 
2141
`baseaddr = VALUE'
2142
     Set the base address of the keyboard's memory mapped registers to
2143 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
2144 19 jeremybenn
 
2145
     The keyboard PS/2 interface has an 3-bit address bus, with 2 8-bit
2146
     registers, at addresses 0x000 and 0x004.
2147
 
2148
          Caution: As noted above, a standard Intel 8042 interface
2149
          would expect to find these registers at locations 0x60 and
2150
          0x64, thus requiring at least a 7-bit bus.
2151
 
2152
`irq = VALUE'
2153 82 jeremybenn
     Use VALUE as the IRQ number of this Keyboard interface.  Default
2154 19 jeremybenn
     value 0.
2155
 
2156
`rxfile = "FILE"'
2157
     `file' specifies a file containing raw key stroke data, which
2158 82 jeremybenn
     models the input from a physical keyboard.  The default value is
2159 19 jeremybenn
     `"kbd_in"'.
2160
 
2161
 
2162

2163
File: or1ksim.info,  Node: Disc Interface Configuration,  Next: Generic Peripheral Configuration,  Prev: Keyboard Configuration,  Up: Peripheral Configuration
2164
 
2165
3.4.9 Disc Interface Configuration
2166
----------------------------------
2167
 
2168
The ATA/ATAPI disc controller used in Or1ksim is the OCIDEC (OpenCores
2169
IDE Controller) component implemented at OpenCores, and found in the
2170 98 jeremybenn
top level SVN directory, `ata'.  It is described in the document
2171 19 jeremybenn
`ATA/ATAPI-5 Core Specification' by Richard Herveille, which can be
2172 82 jeremybenn
found in the `doc' subdirectory.  It is a memory mapped component,
2173
which resides on the main OpenRISC Wishbone data bus.
2174 19 jeremybenn
 
2175 82 jeremybenn
ATA/ATAPI configuration is described in `section ata'.  This section
2176
may appear multiple times, specifying multiple disc controllers.  The
2177 19 jeremybenn
following parameters may be specified.
2178
 
2179
`enabled = 0|1'
2180 82 jeremybenn
     If 1 (true, the default), this ATA/ATAPI interface is enabled.  If
2181 19 jeremybenn
     0, it is disabled.
2182
 
2183
`baseaddr = VALUE'
2184
     Set the base address of the ATA/ATAPI interface's memory mapped
2185 82 jeremybenn
     registers to VALUE.  The default is 0, which is probably not a
2186 19 jeremybenn
     sensible value.
2187
 
2188
     The ATA/ATAPI PS/2 interface has an 5-bit address bus, with 8
2189 82 jeremybenn
     32-bit registers.  Depending on the version of the OCIDEC
2190
     ATA/ATAPI interface selected (see `dev_id' below), not all
2191
     registers will be available.
2192 19 jeremybenn
 
2193
`irq = VALUE'
2194 82 jeremybenn
     Use VALUE as the IRQ number of this ATA/ATAPI interface.  Default
2195 19 jeremybenn
     value 0.
2196
 
2197
`dev_id = 1|2|3'
2198
     This parameter specifies which version of the OCIDEC ATA/ATAPI
2199 82 jeremybenn
     interface to model.  The default value is 1.
2200 19 jeremybenn
 
2201
     Version 1 supports only the `CTRL', `STAT' and `PCTR' registers.
2202
     Versions 2 & 3 add the `FCTR' registers, Version 3 adds the `DTR'
2203
     registers and the `RXD'/`TXD' registers.
2204
 
2205
`rev = VALUE'
2206
     Set the VALUE as the revision of the OCIDEC ATA/ATAPI interface.
2207 82 jeremybenn
     The default value is 1.  The default value is 0.  Its value should
2208
     be in the range 0-15.  Larger values are truncated with a warning.
2209 19 jeremybenn
     This only affects the reset value of the `STAT' register, where it
2210
     forms bits 24-27.
2211
 
2212
`pio_mode0_t1 = VALUE'
2213
`pio_mode0_t2 = VALUE'
2214
`pio_mode0_t4 = VALUE'
2215
`pio_mode0_teoc = VALUE'
2216
     These parameters specify the timings for use with Programmed
2217 82 jeremybenn
     Input/Output (PIO) transfers.  They are specified as the number of
2218 19 jeremybenn
     clock cycles - 2, rounded up to the next highest integer, or zero
2219 82 jeremybenn
     if that would be negative.  The values should not exceed 255.  If
2220 19 jeremybenn
     they do, they will be ignored with a warning.
2221
 
2222
     See the ATA/ATAPI-5 specification for explanations of each of these
2223 82 jeremybenn
     timing parameters.  The default values are:
2224 19 jeremybenn
 
2225
          pio_mode0_t1   =  6
2226
          pio_mode0_t2   = 28
2227
          pio_mode0_t4   =  2
2228
          pio_mode0_teoc = 23
2229
 
2230
`dma_mode0_tm = VALUE'
2231
`dma_mode0_td = VALUE'
2232
`dma_mode0_teoc = VALUE'
2233
     These parameters specify the timings for use with DMA transfers.
2234
     They are specified as the number of clock cycles - 2, rounded up
2235
     to the next highest integer, or zero if that would be negative.
2236 82 jeremybenn
     The values should not exceed 255.  If they do, they will be
2237
     ignored with a warning.
2238 19 jeremybenn
 
2239
     See the ATA/ATAPI-5 specification for explanations of each of these
2240 82 jeremybenn
     timing parameters.  The default values are:
2241 19 jeremybenn
 
2242
          dma_mode0_tm   =  4
2243
          dma_mode0_td   = 21
2244
          dma_mode0_teoc = 21
2245
 
2246
 
2247
3.4.9.1 ATA/ATAPI Device Configuration
2248
......................................
2249
 
2250 82 jeremybenn
Within the `section ata', each device is specified separately.  The
2251 19 jeremybenn
device subsection is introduced by
2252
 
2253
     device VALUE
2254
 
2255 82 jeremybenn
VALUE is the device number, which should be 0 or 1.  The subsection
2256
ends with `enddevice'.  Note that if the same device number is
2257
specified more than once, the previous values will be overwritten.
2258
Within the `device' subsection, the following parameters may appear:
2259 19 jeremybenn
 
2260
`type = VALUE'
2261
     VALUEspecifies the type of device: 0 (the default) for "not
2262
     connected", 1 for hard disk simulated in a file and 2 for local
2263
     system hard disk.
2264
 
2265
`file = "FILENAME"'
2266
     `filename' specifies the file to be used for a simulated ATA
2267 82 jeremybenn
     device if the file type (see `type' above) is 1.  Default value
2268 19 jeremybenn
     `"ata-FileN"', where N is the device number.
2269
 
2270
`size = VALUE'
2271
     VALUE specifies the size of a simulated ATA device if the file
2272 82 jeremybenn
     type (see `type' above) is 1.  The default value is zero.
2273 19 jeremybenn
 
2274
`packet = 0|1'
2275 82 jeremybenn
     If 1 (true), implement the PACKET command feature set.  If 0 (the
2276 19 jeremybenn
     default), do not implement the PACKET command feature set.
2277
 
2278
`firmware = "STR"'
2279
     Firmware to report in response to the "Identify Device" command.
2280
     Default `"02207031"'.
2281
 
2282
`heads = VALUE'
2283 82 jeremybenn
     Number of heads in the device.  Default 7, use -1 to disable all
2284 19 jeremybenn
     heads.
2285
 
2286
`sectors = VALUE'
2287 82 jeremybenn
     Number of sectors per track in the device.  Default 32.
2288 19 jeremybenn
 
2289
`mwdma = 0|1|2|-1'
2290 82 jeremybenn
     Highest multi-word DMA mode supported.  Default 2, use -1 to
2291 19 jeremybenn
     disable.
2292
 
2293
`pio = 0|1|2|3|4'
2294 82 jeremybenn
     Highest PIO mode supported.  Default 4.
2295 19 jeremybenn
 
2296
 
2297

2298
File: or1ksim.info,  Node: Generic Peripheral Configuration,  Prev: Disc Interface Configuration,  Up: Peripheral Configuration
2299
 
2300
3.4.10 Generic Peripheral Configuration
2301
---------------------------------------
2302
 
2303
When used as a library (*note Simulator Library: Simulator Library.),
2304
Or1ksim makes provision for any additional peripheral to be implemented
2305 82 jeremybenn
externally.  Any read or write access to this peripheral's memory map
2306
generates "upcall"s to an external handler.  This interface can support
2307 19 jeremybenn
either C or C++, and was particularly designed to facilitate support
2308
for OSCI SystemC (see `http://www.systemc.org').
2309
 
2310
Generic peripheral configuration is described in `section generic'.
2311
This section may appear multiple times, specifying multiple external
2312 82 jeremybenn
peripherals.  The following parameters may be specified.
2313 19 jeremybenn
 
2314
`enabled = 0|1'
2315 82 jeremybenn
     If 1 (true, the default), this ATA/ATAPI interface is enabled.  If
2316 19 jeremybenn
     0, it is disabled.
2317
 
2318
`baseaddr = VALUE'
2319
     Set the base address of the generic peripheral's memory mapped
2320 82 jeremybenn
     registers to VALUE.  The default is 0, which is probably not a
2321 19 jeremybenn
     sensible value.
2322
 
2323
     The size of the memory mapped register space is controlled by the
2324
     `size' paramter, described below.
2325
 
2326
`size = VALUE'
2327
     Set the size of the generic peripheral's memory mapped register
2328 82 jeremybenn
     space to VALUE bytes.  Any read or write accesses to addresses with
2329 19 jeremybenn
     offsets of 0 to VALUE-1 bytes from the base address specified in
2330
     parameter `baseaddr' (see above) will be directed to the external
2331
     interface.
2332
 
2333 82 jeremybenn
     VALUE will be rounded up the nearest power of 2.  It's default
2334
     value is zero.  If VALUE is not an exact power of two, accesses to
2335 19 jeremybenn
     address offsets of VALUE or above up to the next power of 2 will
2336
     generate a warning, and have no effect (reads will return zero).
2337
 
2338
`name = "STR"'
2339 82 jeremybenn
     This gives the peripheral the name `"STR"'.  This is used to
2340 19 jeremybenn
     identify the peripheral in error messages and warnings, and when
2341 82 jeremybenn
     reporting its status.  The default value is
2342 19 jeremybenn
     `"anonymous external peripheral"'.
2343
 
2344
`byte_enabled = 0|1'
2345
`hw_enabled = 0|1'
2346
`word_enabled = 0|1'
2347
     If 1 (true, the default), these parameters respectively enable the
2348 82 jeremybenn
     device for byte wide, half-word wide and word wide accesses.  If 0,
2349 19 jeremybenn
     accesses of that width will fail.
2350
 
2351
 
2352

2353
File: or1ksim.info,  Node: Interactive Command Line,  Next: Verification API,  Prev: Configuration,  Up: Top
2354
 
2355
4 Interactive Command Line
2356
**************************
2357
 
2358
If started with the `-f' flag, or if interrupted with `ctrl-C', Or1ksim
2359 82 jeremybenn
provides the user with an interactive command line.  The commands
2360 19 jeremybenn
available, which may not be abbreviated, are:
2361
 
2362
`q'
2363
     Exit the simulator
2364
 
2365
`r'
2366 82 jeremybenn
     Display all the General Purpose Registers (GPRs).  Also shows the
2367 19 jeremybenn
     just executed and next to be executed instructions symbolically
2368
     and the state of the flag in the Supervision Register.
2369
 
2370
`t'
2371
     Execute the next instruction and then display register/instruction
2372
     information as with the `r' command (see above).
2373
 
2374
`run NUM [ hush ]'
2375 82 jeremybenn
     Execute NUM instructions.  The register/instruction information is
2376 19 jeremybenn
     displayed after each instruction, as with the `r' command (see
2377
     above) _unless_ `hush' is specified.
2378
 
2379
`pr REG VALUE'
2380
     Patch register REG with VALUE.
2381
 
2382
`dm FROMADDR [ TOADDR ]'
2383 82 jeremybenn
     Display memory bytes between FROMADDR and TOADDR.  If TOADDR is
2384
     not given, 64 bytes are displayed, starting at FROMADDR.
2385 19 jeremybenn
 
2386
          Caution: The output from this command is broken (a bug).
2387 82 jeremybenn
          Or1ksim attempts to print out 16 bytes per row.  However,
2388 19 jeremybenn
          instead of printing out the address at the start of each row,
2389
          it prints the address (of the first of the 16 bytes) before
2390
          _each_ byte.
2391
 
2392
`de FROMADDR [ TOADDR ]'
2393 82 jeremybenn
     Disassemble code between FROMADDR and TOADDR.  If TOADDR is not
2394 19 jeremybenn
     given, 16 instructions are disassembled.
2395
 
2396
     The disassembly is entirely numerical, and gives no symbolic
2397
     information.
2398
 
2399
`pm ADDR VALUE'
2400
     Patch the 4 bytes in memory starting at ADDR with the 32-bit VALUE.
2401
 
2402
`pc VALUE'
2403
     Patch the program counter with VALUE.
2404
 
2405
`cm FROMADDR TOADDR SIZE'
2406
     Copy SIZE bytes in memory from FROMADDR to TOADDR.
2407
 
2408
`break ADDR'
2409
     Toggle the breakpoint set at ADDR.
2410
 
2411
`breaks'
2412
     List all set breakpoints
2413
 
2414
`reset'
2415 82 jeremybenn
     Reset the simulator.  Includes modeling a reset of the processor,
2416
     so execution will restart from the reset vector location, 0x100.
2417 19 jeremybenn
 
2418
`hist'
2419
     If saving the execution history has been configured (*note
2420
     Simulator Behavior: Simulator Behavior.), display the execution
2421
     history.
2422
 
2423
`stall'
2424
     Stall the processor, so that control is passed to the debug unit.
2425 82 jeremybenn
     When stalled, the processor can execute no instructions.  This
2426 19 jeremybenn
     command is useful when debugging the JTAG interface, used by
2427
     debuggers such as GDB.
2428
 
2429
`unstall'
2430 82 jeremybenn
     Unstall the processor, so that normal execution can continue.
2431
     This command is useful when debugging the JTAG interface, used by
2432 19 jeremybenn
     debuggers such as GDB.
2433
 
2434
`stats CATEGORY | clear'
2435
     Print the statistics for the given CATEGORY, if available, or
2436 82 jeremybenn
     clear if `clear' is specified.  The categories are:
2437 19 jeremybenn
 
2438
    1
2439
          Miscellaneous statistics: branch predictions (if branch
2440
          predictions are enabled), branch target cache model (if
2441
          enabled), cache (if enbaled), MMU (if enabled) and number of
2442
          addtional load & store cycles.
2443
 
2444
          *Note Configuring the OpenRisc Achitectural Components: Core
2445
          OpenRISC Configuration, for details of how to enable these
2446
          various features.
2447
 
2448
    2
2449 82 jeremybenn
          Instruction usage statistics.  Requires hazard analysis to be
2450 19 jeremybenn
          enabled (*note CPU Configuration: CPU Configuration.).
2451
 
2452
    3
2453 82 jeremybenn
          Instruction dependency statistics.  Requires hazard analysis
2454 19 jeremybenn
          to be enabled (*note CPU Configuration: CPU Configuration.).
2455
 
2456
    4
2457 82 jeremybenn
          Functional unit dependency statistics.  Requires hazard
2458 19 jeremybenn
          analysis to be enabled (*note CPU Configuration: CPU
2459
          Configuration.).
2460
 
2461
    5
2462 82 jeremybenn
          Raw register usage over time.  Requires hazard analysis to be
2463 19 jeremybenn
          enabled (*note CPU Configuration: CPU Configuration.).
2464
 
2465
    6
2466 82 jeremybenn
          Store buffer statistics.  Requires the store buffer to be
2467 19 jeremybenn
          enabled (*note CPU Configuration: CPU Configuration.).
2468
 
2469
 
2470
`info'
2471
     Display detailed information about the simulator configuration.
2472
     This is quite a lengthy about, because all MMU TLB information is
2473
     displayed.
2474
 
2475
`dv FROMADDR [ TOADDR ] [ MODULE ]'
2476
     Dump the area of memory between FROMADDR and TOADDR as Verilog
2477 82 jeremybenn
     code for a synchronous, 23-bit wide SRAM module, named MODULE.  If
2478 19 jeremybenn
     TOADDR is not specified, then 64 bytes are dumped (as 16 32-bit
2479 82 jeremybenn
     words).  If MODULE is not specified, `or1k_mem' is used.
2480 19 jeremybenn
 
2481
     To save to a file, use the redirection function (described after
2482
     this table, below).
2483
 
2484
`dh FROMADDR [ TOADDR ]'
2485
     Dump the area of memory between FROMADDR and TOADDR as 32-bit hex
2486 82 jeremybenn
     numbers (no `0x', or `32'h' prefix).  If TOADDR is not specified,
2487 19 jeremybenn
     then 64 bytes are dumped (as 16 32-bit words).
2488
 
2489
     To save to a file, use the redirection function (described after
2490
     this table, below).
2491
 
2492
`setdbch'
2493 82 jeremybenn
     Toggle debug channels on/off.  *Note Standalone Simulator:
2494 19 jeremybenn
     Standalone Simulator, for a description of specifying debug
2495
     channels on the command line.
2496
 
2497
`set SECTION PARAM = VALUE'
2498
     Set the configuration parameter PARA in section SECTION to VALUE.
2499
     *Note Configuration: Configuration, for details of configuration
2500
     parameters and their settings.
2501
 
2502
`debug'
2503 82 jeremybenn
     Toggle the simulator debug mode.  *Note Debug Interface
2504 19 jeremybenn
     Configuration: Debug Interface Configuration, for information on
2505
     this parameter.
2506
 
2507
          Caution: This is effectively enabling or disabling the debug
2508 82 jeremybenn
          unit.  It does not effect the remote GDB debug interface.
2509 19 jeremybenn
          However using the remote debug interface while the debug unit
2510
          is disabled will lead to undefined behavior and likely crash
2511
          Or1ksim
2512
 
2513
`cuc'
2514
     Enter the the Custom Unit Compiler command prompt (*note CUC
2515
     Configuration: CUC Configuration.).
2516
 
2517
          Caution: The CUC must be properly configured, for this to
2518 82 jeremybenn
          succeed.  In particular a timing file must be available and
2519
          readable.  Otherwise Or1ksim will crash.
2520 19 jeremybenn
 
2521
`help'
2522
     Print out brief information about each command available.
2523
 
2524
`mprofile [-vh] [-m M] [-g N] [-f FILE] FROM TO'
2525 82 jeremybenn
     Run the memory profiling utility.  This follows the same usage as
2526 19 jeremybenn
     the standalone command (*note Memory Profiling Utility: Memory
2527
     Profiling Utility.).
2528
 
2529
`profile [-vhcq] [-g FILE]'
2530 82 jeremybenn
     Run the instruction profiling utility.  This follows the same
2531
     usage as the standalone command (*note Profiling Utility:
2532
     Profiling Utility.).
2533 19 jeremybenn
 
2534
 
2535
For all commands, it is possible to redirect the output to a file, by
2536
using the redirection operator, `>'.
2537
 
2538
     COMMAND > FILENAME
2539
 
2540
This is particularly useful for commands dumping a large amount of
2541
output, such as `dv'.
2542
 
2543
     Caution: Unfortunately there is a serious bug with the redirection
2544 82 jeremybenn
     operator.  It does not return output to standard output after the
2545
     command completes.  Until this bug is fixed, file redirection
2546 19 jeremybenn
     should not be used.
2547
 
2548

2549
File: or1ksim.info,  Node: Verification API,  Next: Code Internals,  Prev: Interactive Command Line,  Up: Top
2550
 
2551
5 Verification API (VAPI)
2552
*************************
2553
 
2554
The Verification API (VAPI) provides a TCP/IP interface to allow
2555 82 jeremybenn
components of the simulation to be controlled externally.  The
2556
interface is polled for new requests on each simulated clock cycle.
2557
Components within the simulator may send responses to such requests.
2558 19 jeremybenn
 
2559 82 jeremybenn
The inteface is an asynchronous duplex protocol.  On the request side
2560
it provides for simple commands, known as VAPI IDs (a 32 bit integer),
2561
with a single piece of data (also a 32 bit integer).  On the send side,
2562
it provides for sending a single VAPI ID and data.  However there is no
2563
explicit command-response structure.  Some components just accept
2564
requests (e.g.  to set values), some just generate sends (to report
2565 19 jeremybenn
values), and some do both.
2566
 
2567
Each component has a base ID (32 bit) and its commands will start from
2568 82 jeremybenn
that base ID.  This provides a simple partitioning of the command space
2569
amongst components.  Request commands will be directed to the component
2570 19 jeremybenn
with the closest base ID lower than the VAPI ID of the command.
2571
 
2572
Thus if there are two components with base IDs of 0x200 and 0x300, and
2573
a request with VAPI ID of 0x203 is received, it will be directed to the
2574
first component as its command #3.
2575
 
2576
The results of VAPI interactions are logged (by default in `vapi.log'
2577
unless an alternative is specified in `section vapi').
2578
 
2579
Currently the following components support VAPI:
2580
 
2581
Debug Unit
2582
     Although the Debug Unit can specify a base VAPI ID, it is not used
2583
     to send commands or receive requests.
2584
 
2585
     Instead, if the base VAPI ID is set, all remote JTAG protocol
2586
     exchanges are logged in the VAPI log file.
2587
 
2588
UART
2589
     If a base VAPI ID is specified, the UART sends details of any
2590
     chars or break characters sent, with dteails of the line control
2591
     register etc encoded in the data packet sent.
2592
 
2593
     This supports a single VAPI command request, but encodes a
2594
     sub-command in the top 8 bits of the associated data.
2595
 
2596
    `0x00'
2597
          This stuffs the least significant 8 bits of the data into the
2598
          serial register of the UART and the next 8 bits into the line
2599
          control register, effectively providing control of the next
2600
          character to be sent or received.
2601
 
2602
    `0x01'
2603
          The divisor latch bytes are set from the least significant 16
2604
          bits of the data.
2605
 
2606
    `0x02'
2607
          The line control register is set from bits 15-8 of the data.
2608
 
2609
    `0x03'
2610
          The UART skew is set from the least significant 16 bits of
2611
          the data
2612
 
2613
    `0x04'
2614
          If the 16th most significant bit of the data is 1, start
2615 82 jeremybenn
          sending breaks, otherwise stop sending breaks.  The breaks
2616
          are sent or cleared after the number of UART clock divider
2617
          ticks specified by the data (immediately if the data is zero).
2618 19 jeremybenn
 
2619
 
2620
DMA
2621
     Although the DMA unit supports a base VAPI ID in its configuration
2622
     (`section dma'), no VAPI data is sent, nor VAPI requests currently
2623
     implemented.
2624
 
2625
Ethernet
2626 82 jeremybenn
     The following requests are handled by the Ethernet.  Specified
2627 19 jeremybenn
     symbolically, these are the increments from the base VAPI ID of the
2628 82 jeremybenn
     Ethernet.  At present no implementation is provided behind these
2629 19 jeremybenn
     VAPI requests.
2630
 
2631
    `ETH_VAPI_DATA (0)'
2632
 
2633
    `ETH_VAPI_CTRL (0)'
2634
 
2635
GPIO
2636
     If a base VAPI ID is specified, the GPIO sends out on its base
2637
     VAPI ID (symbolically, GPIO_VAPI_DATA (0) offset from the base
2638
     VAPI ID) any changes in outputs.
2639
 
2640 82 jeremybenn
     The following requests are handled by the GPIO.  Specified
2641 19 jeremybenn
     symbolically, these are the increments from the VAPI base ID of the
2642
     GPIO.
2643
 
2644
    `GPIO_VAPI_DATA (0)'
2645
          Set the next input to the commands data field
2646
 
2647
    `GPIO_VAPI_AUX (1)'
2648
          Set the GPIO auxiliary inputs to the data field
2649
 
2650
    `GPIO_VAPI_CLOCK (2)'
2651
          Add an external GPIO clock trigger of period specified in the
2652
          data field.
2653
 
2654
    `GPIO_VAPI_RGPIO_OE (3)'
2655
          Set the GPIO output enable to the data field
2656
 
2657
    `GPIO_VAPI_RGPIO_INTE (4)'
2658
          Set the next interrupt to the data field
2659
 
2660
    `GPIO_VAPI_RGPIO_PTRIG (5)'
2661
          Set the next trigger to the data field
2662
 
2663
    `GPIO_VAPI_RGPIO_AUX (6)'
2664
          Set the next auxiliary input to the data field
2665
 
2666
    `GPIO_VAPI_RGPIO_CTRL (7)'
2667
          Set th next control input to the data field
2668
 
2669
 
2670
 
2671

2672
File: or1ksim.info,  Node: Code Internals,  Next: GNU Free Documentation License,  Prev: Verification API,  Up: Top
2673
 
2674
6 A Guide to Or1ksim Internals
2675
******************************
2676
 
2677 82 jeremybenn
These are notes to help those wanting to extend Or1ksim.  This section
2678 19 jeremybenn
assumes the use of a tag file, so file locations of entities'
2679 82 jeremybenn
definitions are not in general provided.  For more on tags, see the
2680
Linux manual page for `etags'.  A tag file can be created with:
2681 19 jeremybenn
 
2682
     make tags
2683
 
2684
* Menu:
2685
 
2686
* Coding Conventions::
2687
* Global Data Structures::
2688
* Concepts::
2689
* Internal Debugging::
2690 104 jeremybenn
* Regression Testing::
2691 19 jeremybenn
 
2692

2693
File: or1ksim.info,  Node: Coding Conventions,  Next: Global Data Structures,  Up: Code Internals
2694
 
2695
6.1 Coding Conventions for Or1ksim
2696
==================================
2697
 
2698
This chapter provides some guidelines for coding, to facilitate
2699
extensions to Or1ksim
2700
 
2701
_GNU Coding Standard_
2702
     Code should follow the GNU coding standard for C
2703 82 jeremybenn
     (`http://www.gnu.org/prep/standards/'.  If in doubt, put your code
2704 19 jeremybenn
     through the `indent' program.
2705
 
2706
_`#include' headers_
2707
     All C source code files should include `config.h' before any other
2708
     file.
2709
 
2710
     This should be followed by inclusion of any system headers (but see
2711
     the comments about portability and `port.h' below) and then by any
2712
     Or1ksim package headers.
2713
 
2714
     If `port.h' is required, it should be the first package header to
2715
     be included after the system headers.
2716
 
2717
     All C source code and header files should directly include any
2718 82 jeremybenn
     system or package header they depend on, i.e.  not rely on any
2719
     other header having already included it.  The two exceptions are
2720 19 jeremybenn
 
2721
       1. All header files may assume that `config.h' has already been
2722
          included.
2723
 
2724
       2. System headers which impose portability problems should be
2725
          included by using the package header `port.h', rather than
2726 82 jeremybenn
          the system headers themselves.  This is the case for code
2727 19 jeremybenn
          requiring
2728
 
2729
             * `strndup' (from `string.h')
2730
 
2731
             * Integer types (`intN_t', `uintN_t') (from `inttypes.h').
2732
 
2733
             * `isblank' (from `ctype.h')
2734
 
2735
 
2736
 
2737
_`#include' files once only_
2738
     All include files should be protected by `#ifndef' to ensure their
2739 82 jeremybenn
     definitions are only included once.  For instance a header file
2740 19 jeremybenn
     `X-Y.H' should surround its contents with:
2741
 
2742
          #ifndef X_Y__H
2743
          #define X_Y__H
2744
 
2745
          
2746
 
2747
          #endif  /* X_Y__H */
2748
 
2749
_Avoid `typedef'_
2750
     The GNU coding style for C does not have a clear way to distinguish
2751 82 jeremybenn
     between user type name and user variables.  For this reason
2752 19 jeremybenn
     `typedef' should be avoided except for the most ubiquitous user
2753 82 jeremybenn
     defined types.  This makes the code much easier to read.
2754 19 jeremybenn
 
2755
     There are some `typedef' declarations in the `argtable2' library
2756
     and the ELF and COFF headers, because this code is taken from
2757
     other places.
2758
 
2759
     Within Or1ksim legacy uses of `typedef' have largely been purged,
2760
     except in the Custom Unit Compiler (*note Custom Unit Compiler
2761
     (CUC) Configuration: CUC Configuration.).
2762
 
2763
     The remaining uses of `typedef' occur in two places:
2764
 
2765
        * `port/port.h' defines types to replace those in header files
2766
          that are not available (character functions, string
2767
          duplication, integer types).
2768
 
2769
          `cpu/or1k/arch.h' defines types for the key Or1ksim entities:
2770
          addresses (`oraddr_t'), unsigned register values (`uorreg_t')
2771
          and signed register (`orreg_t') values.
2772
 
2773
 
2774
     Where new types are defined, they should appear in one of these two
2775 82 jeremybenn
     files as appropriate.  Or1ksim specific types appearing in
2776
     `arch.h' should always have the suffix `_h'.
2777 19 jeremybenn
 
2778
_Don't begin names with underscore_
2779
     Names beginning with `_' are intended to be part of the C
2780 82 jeremybenn
     infrastructure.  They should not be used in the simulator code.
2781 19 jeremybenn
 
2782
_Keep Non-global top level entities static_
2783
     All top level entities (functions, variables), which are not
2784
     explicitly part of a global interface should be declared static.
2785
     This ensures that unwanted connections are not inadvertently built
2786
     across the program.
2787
 
2788
_Use of `inline'_
2789 82 jeremybenn
     Code should not be declared `inline'.  Modern compilers can work
2790 19 jeremybenn
     out for themselves what is best in this respect.
2791
 
2792
_Initialization_
2793 82 jeremybenn
     All data structures should be explicitly initialized.  In
2794
     particular code should not rely on static data structures being
2795
     initialized to zero.
2796 19 jeremybenn
 
2797
     The rationale is that in future static data structures may become
2798 82 jeremybenn
     dynamic.  This has been a particular source of bugs in Or1ksim
2799 19 jeremybenn
     historically.
2800
 
2801
     A specific case is with new peripherals, which should always
2802
     include a `start' function to pre-initialize all configuration
2803
     parameters to sensible defaults
2804
 
2805
_Configuration Validation_
2806
     All configuration values should be validated, preferably when
2807
     encountered, if not when the `section' is closed, or otherwise at
2808
     run time when the parameter is first used.
2809
 
2810
 
2811

2812
File: or1ksim.info,  Node: Global Data Structures,  Next: Concepts,  Prev: Coding Conventions,  Up: Code Internals
2813
 
2814
6.2 Global Data Structures
2815
==========================
2816
 
2817
`config'
2818
     The global variable `config' of type `struct config' holds the
2819
     configuration data for some of the Or1ksim components which are
2820 82 jeremybenn
     always present.  At present the components are:
2821 19 jeremybenn
 
2822
        * The simulator defined in `section sim' (*note Simulator
2823
          Configuration: Simulator Configuration.).
2824
 
2825
        * The Verification API (VAPI) defined  in `section vapi' (*note
2826
          Verification API (VAPI) Configuration: Verification API
2827
          Configuration.).
2828
 
2829
        * The Custom Unit Compiler (CUC), defined in `section cuc'
2830
          (*note Custom Unit Compiler (CUC) Configuration: CUC
2831
          Configuration.).
2832
 
2833
        * The CPU, defined in `section cpu' (*note CPU Configuration:
2834
          CPU Configuration.).
2835
 
2836
        * The data cache (but not the instruction cache), defined in
2837
          `section dc' (*note Cache Configuration: Cache
2838
          Configuration.).
2839
 
2840
        * The power management unit, defined in `section pm' (*note
2841
          Power Management Configuration: Power Management
2842
          Configuration.).
2843
 
2844
        * The programmable interrupt controller, defined in
2845
          `section pic' (*note Interrupt Configuration: Interrupt
2846
          Configuration.).
2847
 
2848
        * Branch prediciton, defined in `section bpb' (*note Branch
2849
          Prediction Configuration: Branch Prediction Configuration.).
2850
 
2851
        * The debug unit, defined in `section debug' (*note Debug
2852
          Interface Configuration: Debug Interface Configuration.).
2853
 
2854
 
2855
     This struct is made of a collection of structs, one for each
2856 82 jeremybenn
     component.  For example the simulator configuration is held in
2857 19 jeremybenn
     `config.sim'.
2858
 
2859
`config'
2860
     This is a linked list of data structures holding configuration data
2861
     for all sections which are not held in the main `config' data
2862 82 jeremybenn
     structure.  In general these are components (such as peripherals
2863
     and memory) which may occur multiple times.  However it also
2864
     handles some architectural components which may occur only once,
2865
     such as the memory management units, the instruction cache, the
2866
     interrupt controller and branch prediction.
2867 19 jeremybenn
 
2868
`runtime'
2869
     The global variable `runtime' of type `struct runtime' holds all
2870 82 jeremybenn
     the runtime information about the simulation.  To access this
2871 19 jeremybenn
     variable, `sim-config.h' must be included.
2872
 
2873
     This struct is itself made of 3 other structs, `cpu' (for CPU run
2874
     time state), `vapi' (for Verification API state) and `cuc' (for
2875
     Custom Unit Compiler state).
2876
 
2877
 
2878

2879
File: or1ksim.info,  Node: Concepts,  Next: Internal Debugging,  Prev: Global Data Structures,  Up: Code Internals
2880
 
2881
6.3 Concepts
2882
============
2883
 
2884
_Output Redirection_
2885 82 jeremybenn
     The current output stream is held in `runtime.cpu.fout'.  Output
2886 19 jeremybenn
     should be explicitly written to this stream, or may use the
2887
     `PRINTF' macro, which will write its arguments to this output
2888
     stream.
2889
 
2890
_Reset Hooks_
2891
     Any peripheral may register a routine to be called when the the
2892
     processor is reset by calling `reg_sim_reset', providing a
2893 82 jeremybenn
     function and pointer to a data structure as arguments.  On reset
2894 19 jeremybenn
     that function will be called with the data stucture pointer as
2895
     argument.
2896
 
2897
 
2898

2899 104 jeremybenn
File: or1ksim.info,  Node: Internal Debugging,  Next: Regression Testing,  Prev: Concepts,  Up: Code Internals
2900 19 jeremybenn
 
2901
6.4 Internal Debugging
2902
======================
2903
 
2904
The function `debug' is like `printf', but with an extra first
2905 82 jeremybenn
argument, which is the debug level.  If the debug level specified in
2906
the simulator configuration (*note Simulator Behavior: Simulator
2907
Behavior.) is greater than or equal to this value, the remaining
2908
arguments are printed to the current output stream (*note Output
2909
Redirection: Output Redirection.).
2910 19 jeremybenn
 
2911

2912 104 jeremybenn
File: or1ksim.info,  Node: Regression Testing,  Prev: Internal Debugging,  Up: Code Internals
2913
 
2914
6.5 Regression Testing
2915
======================
2916
 
2917
Or1ksim now includes a regression test suite for both standalone and
2918
library usage as described earlier (*note Building and Installing:
2919
Build and Install.).  Running the tests requires that the OpenRISC
2920
toolchain and DejaGNU are both installed.
2921
 
2922
Tests are written using `expect', a derivative of TCL.  Documentation
2923
of DejaGnu, `expect' and TCL are freely available on the Web.  The
2924
Embecosm Application Note 8, `Howto: Using DejaGnu for Testing: A
2925
Simple Introduction' (`http://www.embecosm.com/download/ean8.html')
2926
provides a concise introduction.
2927
 
2928
All test code is found in the `testsuite' directory.  The key files and
2929
directories used are as follows.
2930
 
2931
`global-conf.exp'
2932
     This is the global DejaGNU configuration file used to set up
2933
     parameters common to all tests.  If the user has the environment
2934
     varialbe `DEJAGNU' defined, it will be used instead, but this is
2935
     not recommended.
2936
 
2937
`Makefile.am'
2938
     This is the top level `automake' file for the testsuite.  The only
2939
     changes likely to be needed here is additional local cleanup of
2940
     files created by new tests.
2941
 
2942
`README'
2943
     This contains details of all the tests
2944
 
2945
`config'
2946
     This contains DejaGnu board configurations.  Since the tests are
2947
     generally run on a Unix host, this should just contain `Unix.exp'.
2948
 
2949
`lib'
2950
     This contains DejaGnu tool specific configurations.  "Tool" has a
2951
     specific meaning in DejaGNU, referring just to a grouping of
2952
     tests.  In this case there are two such "tools", "or1ksim" and
2953
     "libsim" for tests of the standalone tool and tests of the library.
2954
 
2955
     Corresponding to this, there are two tool specific configuration
2956
     files, `or1ksim.exp' and `libsim.exp'.  These contain `expect'/TCL
2957
     procedures for common use among the tests.
2958
 
2959
`libsim.tests'
2960
`or1ksim.tests'
2961
     These are the directories of tests of the Or1ksim library.  They
2962
     also include Or1ksim configuration files and each has a
2963
     `Makefile.am' file.  `Makefile.am' should be updated whenever
2964
     files are added to this directory, to ensure they are included in
2965
     the distribution.
2966
 
2967
`test-code'
2968
     These are all the test programs to be compiled on the host (each
2969
     in its own directory).  In general these are programs to support
2970
     testing of the library, and build various programs linking in the
2971
     library.
2972
 
2973
`test-code'
2974
     These are all the test programs to be compiled with the OpenRISC
2975
     tool chain to run with either standalone Or1ksim or the library.
2976
     This directory includes its own `configure.ac', since it must set
2977
     up a separate tool chain based on the target, not the host.
2978
 
2979
 
2980
To add a new test needs the following steps.
2981
 
2982
   * Put new host C code in its own directory within `test-code'. Add
2983
     the directory to the existing `Makefile.am' in the `test-code'
2984
     directory and create a `Makefile.am' in the new directory to drive
2985
     building the test program(s). Don't forget to add the new
2986
     `Makefile' to the top level `configure.ac' so it gets generated.
2987
     Not all tests require code here.
2988
 
2989
   * Put new target C code in its own directory within
2990
     `test-code-or1k'. Once again modify & create `Makefile.am'. this
2991
     time though modify the `configure.ac' in the `test-code-or1k' so
2992
     the `Makefile' gets generated. The existing programs provide
2993
     examples to start from, including custom linker scripts where
2994
     needed.
2995
 
2996
   * Add one or more tests and configuration files to the relevant
2997
     "tool" test directory. Use the existing tests as templates. They
2998
     make heavy use of the `expect'/TCL procedures in the `config'
2999
     directory to facilitate driving the tests.
3000
 
3001
 
3002

3003 19 jeremybenn
File: or1ksim.info,  Node: GNU Free Documentation License,  Next: Index,  Prev: Code Internals,  Up: Top
3004
 
3005
7 GNU Free Documentation License
3006
********************************
3007
 
3008
                      Version 1.2, November 2002
3009
 
3010
     Copyright (C) 2000,2001,2002 Free Software Foundation, Inc.
3011
     51 Franklin St, Fifth Floor, Boston, MA  02110-1301, USA
3012
 
3013
     Everyone is permitted to copy and distribute verbatim copies
3014
     of this license document, but changing it is not allowed.
3015
 
3016
  0. PREAMBLE
3017
 
3018
     The purpose of this License is to make a manual, textbook, or other
3019
     functional and useful document "free" in the sense of freedom: to
3020
     assure everyone the effective freedom to copy and redistribute it,
3021
     with or without modifying it, either commercially or
3022
     noncommercially.  Secondarily, this License preserves for the
3023
     author and publisher a way to get credit for their work, while not
3024
     being considered responsible for modifications made by others.
3025
 
3026
     This License is a kind of "copyleft", which means that derivative
3027
     works of the document must themselves be free in the same sense.
3028
     It complements the GNU General Public License, which is a copyleft
3029
     license designed for free software.
3030
 
3031
     We have designed this License in order to use it for manuals for
3032
     free software, because free software needs free documentation: a
3033
     free program should come with manuals providing the same freedoms
3034
     that the software does.  But this License is not limited to
3035
     software manuals; it can be used for any textual work, regardless
3036
     of subject matter or whether it is published as a printed book.
3037
     We recommend this License principally for works whose purpose is
3038
     instruction or reference.
3039
 
3040
  1. APPLICABILITY AND DEFINITIONS
3041
 
3042
     This License applies to any manual or other work, in any medium,
3043
     that contains a notice placed by the copyright holder saying it
3044
     can be distributed under the terms of this License.  Such a notice
3045
     grants a world-wide, royalty-free license, unlimited in duration,
3046
     to use that work under the conditions stated herein.  The
3047
     "Document", below, refers to any such manual or work.  Any member
3048
     of the public is a licensee, and is addressed as "you".  You
3049
     accept the license if you copy, modify or distribute the work in a
3050
     way requiring permission under copyright law.
3051
 
3052
     A "Modified Version" of the Document means any work containing the
3053
     Document or a portion of it, either copied verbatim, or with
3054
     modifications and/or translated into another language.
3055
 
3056
     A "Secondary Section" is a named appendix or a front-matter section
3057
     of the Document that deals exclusively with the relationship of the
3058
     publishers or authors of the Document to the Document's overall
3059
     subject (or to related matters) and contains nothing that could
3060
     fall directly within that overall subject.  (Thus, if the Document
3061
     is in part a textbook of mathematics, a Secondary Section may not
3062
     explain any mathematics.)  The relationship could be a matter of
3063
     historical connection with the subject or with related matters, or
3064
     of legal, commercial, philosophical, ethical or political position
3065
     regarding them.
3066
 
3067
     The "Invariant Sections" are certain Secondary Sections whose
3068
     titles are designated, as being those of Invariant Sections, in
3069
     the notice that says that the Document is released under this
3070
     License.  If a section does not fit the above definition of
3071
     Secondary then it is not allowed to be designated as Invariant.
3072
     The Document may contain zero Invariant Sections.  If the Document
3073
     does not identify any Invariant Sections then there are none.
3074
 
3075
     The "Cover Texts" are certain short passages of text that are
3076
     listed, as Front-Cover Texts or Back-Cover Texts, in the notice
3077
     that says that the Document is released under this License.  A
3078
     Front-Cover Text may be at most 5 words, and a Back-Cover Text may
3079
     be at most 25 words.
3080
 
3081
     A "Transparent" copy of the Document means a machine-readable copy,
3082
     represented in a format whose specification is available to the
3083
     general public, that is suitable for revising the document
3084
     straightforwardly with generic text editors or (for images
3085
     composed of pixels) generic paint programs or (for drawings) some
3086
     widely available drawing editor, and that is suitable for input to
3087
     text formatters or for automatic translation to a variety of
3088
     formats suitable for input to text formatters.  A copy made in an
3089
     otherwise Transparent file format whose markup, or absence of
3090
     markup, has been arranged to thwart or discourage subsequent
3091
     modification by readers is not Transparent.  An image format is
3092
     not Transparent if used for any substantial amount of text.  A
3093
     copy that is not "Transparent" is called "Opaque".
3094
 
3095
     Examples of suitable formats for Transparent copies include plain
3096
     ASCII without markup, Texinfo input format, LaTeX input format,
3097
     SGML or XML using a publicly available DTD, and
3098
     standard-conforming simple HTML, PostScript or PDF designed for
3099
     human modification.  Examples of transparent image formats include
3100
     PNG, XCF and JPG.  Opaque formats include proprietary formats that
3101
     can be read and edited only by proprietary word processors, SGML or
3102
     XML for which the DTD and/or processing tools are not generally
3103
     available, and the machine-generated HTML, PostScript or PDF
3104
     produced by some word processors for output purposes only.
3105
 
3106
     The "Title Page" means, for a printed book, the title page itself,
3107
     plus such following pages as are needed to hold, legibly, the
3108
     material this License requires to appear in the title page.  For
3109
     works in formats which do not have any title page as such, "Title
3110
     Page" means the text near the most prominent appearance of the
3111
     work's title, preceding the beginning of the body of the text.
3112
 
3113
     A section "Entitled XYZ" means a named subunit of the Document
3114
     whose title either is precisely XYZ or contains XYZ in parentheses
3115
     following text that translates XYZ in another language.  (Here XYZ
3116
     stands for a specific section name mentioned below, such as
3117
     "Acknowledgements", "Dedications", "Endorsements", or "History".)
3118
     To "Preserve the Title" of such a section when you modify the
3119
     Document means that it remains a section "Entitled XYZ" according
3120
     to this definition.
3121
 
3122
     The Document may include Warranty Disclaimers next to the notice
3123
     which states that this License applies to the Document.  These
3124
     Warranty Disclaimers are considered to be included by reference in
3125
     this License, but only as regards disclaiming warranties: any other
3126
     implication that these Warranty Disclaimers may have is void and
3127
     has no effect on the meaning of this License.
3128
 
3129
  2. VERBATIM COPYING
3130
 
3131
     You may copy and distribute the Document in any medium, either
3132
     commercially or noncommercially, provided that this License, the
3133
     copyright notices, and the license notice saying this License
3134
     applies to the Document are reproduced in all copies, and that you
3135
     add no other conditions whatsoever to those of this License.  You
3136
     may not use technical measures to obstruct or control the reading
3137
     or further copying of the copies you make or distribute.  However,
3138
     you may accept compensation in exchange for copies.  If you
3139
     distribute a large enough number of copies you must also follow
3140
     the conditions in section 3.
3141
 
3142
     You may also lend copies, under the same conditions stated above,
3143
     and you may publicly display copies.
3144
 
3145
  3. COPYING IN QUANTITY
3146
 
3147
     If you publish printed copies (or copies in media that commonly
3148
     have printed covers) of the Document, numbering more than 100, and
3149
     the Document's license notice requires Cover Texts, you must
3150
     enclose the copies in covers that carry, clearly and legibly, all
3151
     these Cover Texts: Front-Cover Texts on the front cover, and
3152
     Back-Cover Texts on the back cover.  Both covers must also clearly
3153
     and legibly identify you as the publisher of these copies.  The
3154
     front cover must present the full title with all words of the
3155
     title equally prominent and visible.  You may add other material
3156
     on the covers in addition.  Copying with changes limited to the
3157
     covers, as long as they preserve the title of the Document and
3158
     satisfy these conditions, can be treated as verbatim copying in
3159
     other respects.
3160
 
3161
     If the required texts for either cover are too voluminous to fit
3162
     legibly, you should put the first ones listed (as many as fit
3163
     reasonably) on the actual cover, and continue the rest onto
3164
     adjacent pages.
3165
 
3166
     If you publish or distribute Opaque copies of the Document
3167
     numbering more than 100, you must either include a
3168
     machine-readable Transparent copy along with each Opaque copy, or
3169
     state in or with each Opaque copy a computer-network location from
3170
     which the general network-using public has access to download
3171
     using public-standard network protocols a complete Transparent
3172
     copy of the Document, free of added material.  If you use the
3173
     latter option, you must take reasonably prudent steps, when you
3174
     begin distribution of Opaque copies in quantity, to ensure that
3175
     this Transparent copy will remain thus accessible at the stated
3176
     location until at least one year after the last time you
3177
     distribute an Opaque copy (directly or through your agents or
3178
     retailers) of that edition to the public.
3179
 
3180
     It is requested, but not required, that you contact the authors of
3181
     the Document well before redistributing any large number of
3182
     copies, to give them a chance to provide you with an updated
3183
     version of the Document.
3184
 
3185
  4. MODIFICATIONS
3186
 
3187
     You may copy and distribute a Modified Version of the Document
3188
     under the conditions of sections 2 and 3 above, provided that you
3189
     release the Modified Version under precisely this License, with
3190
     the Modified Version filling the role of the Document, thus
3191
     licensing distribution and modification of the Modified Version to
3192
     whoever possesses a copy of it.  In addition, you must do these
3193
     things in the Modified Version:
3194
 
3195
       A. Use in the Title Page (and on the covers, if any) a title
3196
          distinct from that of the Document, and from those of
3197
          previous versions (which should, if there were any, be listed
3198
          in the History section of the Document).  You may use the
3199
          same title as a previous version if the original publisher of
3200
          that version gives permission.
3201
 
3202
       B. List on the Title Page, as authors, one or more persons or
3203
          entities responsible for authorship of the modifications in
3204
          the Modified Version, together with at least five of the
3205
          principal authors of the Document (all of its principal
3206
          authors, if it has fewer than five), unless they release you
3207
          from this requirement.
3208
 
3209
       C. State on the Title page the name of the publisher of the
3210
          Modified Version, as the publisher.
3211
 
3212
       D. Preserve all the copyright notices of the Document.
3213
 
3214
       E. Add an appropriate copyright notice for your modifications
3215
          adjacent to the other copyright notices.
3216
 
3217
       F. Include, immediately after the copyright notices, a license
3218
          notice giving the public permission to use the Modified
3219
          Version under the terms of this License, in the form shown in
3220
          the Addendum below.
3221
 
3222
       G. Preserve in that license notice the full lists of Invariant
3223
          Sections and required Cover Texts given in the Document's
3224
          license notice.
3225
 
3226
       H. Include an unaltered copy of this License.
3227
 
3228
       I. Preserve the section Entitled "History", Preserve its Title,
3229
          and add to it an item stating at least the title, year, new
3230
          authors, and publisher of the Modified Version as given on
3231
          the Title Page.  If there is no section Entitled "History" in
3232
          the Document, create one stating the title, year, authors,
3233
          and publisher of the Document as given on its Title Page,
3234
          then add an item describing the Modified Version as stated in
3235
          the previous sentence.
3236
 
3237
       J. Preserve the network location, if any, given in the Document
3238
          for public access to a Transparent copy of the Document, and
3239
          likewise the network locations given in the Document for
3240
          previous versions it was based on.  These may be placed in
3241
          the "History" section.  You may omit a network location for a
3242
          work that was published at least four years before the
3243
          Document itself, or if the original publisher of the version
3244
          it refers to gives permission.
3245
 
3246
       K. For any section Entitled "Acknowledgements" or "Dedications",
3247
          Preserve the Title of the section, and preserve in the
3248
          section all the substance and tone of each of the contributor
3249
          acknowledgements and/or dedications given therein.
3250
 
3251
       L. Preserve all the Invariant Sections of the Document,
3252
          unaltered in their text and in their titles.  Section numbers
3253
          or the equivalent are not considered part of the section
3254
          titles.
3255
 
3256
       M. Delete any section Entitled "Endorsements".  Such a section
3257
          may not be included in the Modified Version.
3258
 
3259
       N. Do not retitle any existing section to be Entitled
3260
          "Endorsements" or to conflict in title with any Invariant
3261
          Section.
3262
 
3263
       O. Preserve any Warranty Disclaimers.
3264
 
3265
     If the Modified Version includes new front-matter sections or
3266
     appendices that qualify as Secondary Sections and contain no
3267
     material copied from the Document, you may at your option
3268
     designate some or all of these sections as invariant.  To do this,
3269
     add their titles to the list of Invariant Sections in the Modified
3270
     Version's license notice.  These titles must be distinct from any
3271
     other section titles.
3272
 
3273
     You may add a section Entitled "Endorsements", provided it contains
3274
     nothing but endorsements of your Modified Version by various
3275
     parties--for example, statements of peer review or that the text
3276
     has been approved by an organization as the authoritative
3277
     definition of a standard.
3278
 
3279
     You may add a passage of up to five words as a Front-Cover Text,
3280
     and a passage of up to 25 words as a Back-Cover Text, to the end
3281
     of the list of Cover Texts in the Modified Version.  Only one
3282
     passage of Front-Cover Text and one of Back-Cover Text may be
3283
     added by (or through arrangements made by) any one entity.  If the
3284
     Document already includes a cover text for the same cover,
3285
     previously added by you or by arrangement made by the same entity
3286
     you are acting on behalf of, you may not add another; but you may
3287
     replace the old one, on explicit permission from the previous
3288
     publisher that added the old one.
3289
 
3290
     The author(s) and publisher(s) of the Document do not by this
3291
     License give permission to use their names for publicity for or to
3292
     assert or imply endorsement of any Modified Version.
3293
 
3294
  5. COMBINING DOCUMENTS
3295
 
3296
     You may combine the Document with other documents released under
3297
     this License, under the terms defined in section 4 above for
3298
     modified versions, provided that you include in the combination
3299
     all of the Invariant Sections of all of the original documents,
3300
     unmodified, and list them all as Invariant Sections of your
3301
     combined work in its license notice, and that you preserve all
3302
     their Warranty Disclaimers.
3303
 
3304
     The combined work need only contain one copy of this License, and
3305
     multiple identical Invariant Sections may be replaced with a single
3306
     copy.  If there are multiple Invariant Sections with the same name
3307
     but different contents, make the title of each such section unique
3308
     by adding at the end of it, in parentheses, the name of the
3309
     original author or publisher of that section if known, or else a
3310
     unique number.  Make the same adjustment to the section titles in
3311
     the list of Invariant Sections in the license notice of the
3312
     combined work.
3313
 
3314
     In the combination, you must combine any sections Entitled
3315
     "History" in the various original documents, forming one section
3316
     Entitled "History"; likewise combine any sections Entitled
3317
     "Acknowledgements", and any sections Entitled "Dedications".  You
3318
     must delete all sections Entitled "Endorsements."
3319
 
3320
  6. COLLECTIONS OF DOCUMENTS
3321
 
3322
     You may make a collection consisting of the Document and other
3323
     documents released under this License, and replace the individual
3324
     copies of this License in the various documents with a single copy
3325
     that is included in the collection, provided that you follow the
3326
     rules of this License for verbatim copying of each of the
3327
     documents in all other respects.
3328
 
3329
     You may extract a single document from such a collection, and
3330
     distribute it individually under this License, provided you insert
3331
     a copy of this License into the extracted document, and follow
3332
     this License in all other respects regarding verbatim copying of
3333
     that document.
3334
 
3335
  7. AGGREGATION WITH INDEPENDENT WORKS
3336
 
3337
     A compilation of the Document or its derivatives with other
3338
     separate and independent documents or works, in or on a volume of
3339
     a storage or distribution medium, is called an "aggregate" if the
3340
     copyright resulting from the compilation is not used to limit the
3341
     legal rights of the compilation's users beyond what the individual
3342
     works permit.  When the Document is included in an aggregate, this
3343
     License does not apply to the other works in the aggregate which
3344
     are not themselves derivative works of the Document.
3345
 
3346
     If the Cover Text requirement of section 3 is applicable to these
3347
     copies of the Document, then if the Document is less than one half
3348
     of the entire aggregate, the Document's Cover Texts may be placed
3349
     on covers that bracket the Document within the aggregate, or the
3350
     electronic equivalent of covers if the Document is in electronic
3351
     form.  Otherwise they must appear on printed covers that bracket
3352
     the whole aggregate.
3353
 
3354
  8. TRANSLATION
3355
 
3356
     Translation is considered a kind of modification, so you may
3357
     distribute translations of the Document under the terms of section
3358
     4.  Replacing Invariant Sections with translations requires special
3359
     permission from their copyright holders, but you may include
3360
     translations of some or all Invariant Sections in addition to the
3361
     original versions of these Invariant Sections.  You may include a
3362
     translation of this License, and all the license notices in the
3363
     Document, and any Warranty Disclaimers, provided that you also
3364
     include the original English version of this License and the
3365
     original versions of those notices and disclaimers.  In case of a
3366
     disagreement between the translation and the original version of
3367
     this License or a notice or disclaimer, the original version will
3368
     prevail.
3369
 
3370
     If a section in the Document is Entitled "Acknowledgements",
3371
     "Dedications", or "History", the requirement (section 4) to
3372
     Preserve its Title (section 1) will typically require changing the
3373
     actual title.
3374
 
3375
  9. TERMINATION
3376
 
3377
     You may not copy, modify, sublicense, or distribute the Document
3378
     except as expressly provided for under this License.  Any other
3379
     attempt to copy, modify, sublicense or distribute the Document is
3380
     void, and will automatically terminate your rights under this
3381
     License.  However, parties who have received copies, or rights,
3382
     from you under this License will not have their licenses
3383
     terminated so long as such parties remain in full compliance.
3384
 
3385
 10. FUTURE REVISIONS OF THIS LICENSE
3386
 
3387
     The Free Software Foundation may publish new, revised versions of
3388
     the GNU Free Documentation License from time to time.  Such new
3389
     versions will be similar in spirit to the present version, but may
3390
     differ in detail to address new problems or concerns.  See
3391
     `http://www.gnu.org/copyleft/'.
3392
 
3393
     Each version of the License is given a distinguishing version
3394
     number.  If the Document specifies that a particular numbered
3395
     version of this License "or any later version" applies to it, you
3396
     have the option of following the terms and conditions either of
3397
     that specified version or of any later version that has been
3398
     published (not as a draft) by the Free Software Foundation.  If
3399
     the Document does not specify a version number of this License,
3400
     you may choose any version ever published (not as a draft) by the
3401
     Free Software Foundation.
3402
 
3403
ADDENDUM: How to use this License for your documents
3404
====================================================
3405
 
3406
To use this License in a document you have written, include a copy of
3407
the License in the document and put the following copyright and license
3408
notices just after the title page:
3409
 
3410
       Copyright (C)  YEAR  YOUR NAME.
3411
       Permission is granted to copy, distribute and/or modify this document
3412
       under the terms of the GNU Free Documentation License, Version 1.2
3413
       or any later version published by the Free Software Foundation;
3414
       with no Invariant Sections, no Front-Cover Texts, and no Back-Cover
3415
       Texts.  A copy of the license is included in the section entitled ``GNU
3416
       Free Documentation License''.
3417
 
3418
If you have Invariant Sections, Front-Cover Texts and Back-Cover Texts,
3419
replace the "with...Texts." line with this:
3420
 
3421
         with the Invariant Sections being LIST THEIR TITLES, with
3422
         the Front-Cover Texts being LIST, and with the Back-Cover Texts
3423
         being LIST.
3424
 
3425
If you have Invariant Sections without Cover Texts, or some other
3426
combination of the three, merge those two alternatives to suit the
3427
situation.
3428
 
3429
If your document contains nontrivial examples of program code, we
3430
recommend releasing these examples in parallel under your choice of
3431
free software license, such as the GNU General Public License, to
3432
permit their use in free software.
3433
 
3434

3435
File: or1ksim.info,  Node: Index,  Prev: GNU Free Documentation License,  Up: Top
3436
 
3437
Index
3438
*****
3439
 
3440
 
3441
* Menu:
3442
3443
* --cumulative:                          Profiling Utility.   (line  26)
3444
* --debug-config:                        Standalone Simulator.
3445
                                                              (line  48)
3446 82 jeremybenn
* --disable-all-tests:                   Configuring the Build.
3447 127 jeremybenn
                                                              (line 105)
3448 19 jeremybenn
* --disable-arith-flag:                  Configuring the Build.
3449 127 jeremybenn
                                                              (line 118)
3450 124 jeremybenn
* --disable-debug:                       Configuring the Build.
3451 127 jeremybenn
                                                              (line  98)
3452 19 jeremybenn
* --disable-ethphy:                      Configuring the Build.
3453 104 jeremybenn
                                                              (line  59)
3454 19 jeremybenn
* --disable-ov-flag:                     Configuring the Build.
3455 127 jeremybenn
                                                              (line 133)
3456 19 jeremybenn
* --disable-profiling:                   Configuring the Build.
3457 104 jeremybenn
                                                              (line  30)
3458 19 jeremybenn
* --disable-range-stats:                 Configuring the Build.
3459 127 jeremybenn
                                                              (line  92)
3460
* --disable-unsigned-xori:               Configuring the Build.
3461 104 jeremybenn
                                                              (line  69)
3462 82 jeremybenn
* --enable-all-tests:                    Configuring the Build.
3463 127 jeremybenn
                                                              (line 104)
3464 19 jeremybenn
* --enable-arith-flag:                   Configuring the Build.
3465 127 jeremybenn
                                                              (line 117)
3466 124 jeremybenn
* --enable-debug:                        Configuring the Build.
3467 127 jeremybenn
                                                              (line  97)
3468 19 jeremybenn
* --enable-ethphy:                       Configuring the Build.
3469 104 jeremybenn
                                                              (line  58)
3470 19 jeremybenn
* --enable-execution:                    Configuring the Build.
3471 104 jeremybenn
                                                              (line  37)
3472 19 jeremybenn
* --enable-mprofile:                     Standalone Simulator.
3473
                                                              (line  77)
3474
* --enable-ov-flag:                      Configuring the Build.
3475 127 jeremybenn
                                                              (line 132)
3476 19 jeremybenn
* --enable-profile:                      Standalone Simulator.
3477
                                                              (line  74)
3478
* --enable-profiling:                    Configuring the Build.
3479 104 jeremybenn
                                                              (line  29)
3480 19 jeremybenn
* --enable-range-stats:                  Configuring the Build.
3481 127 jeremybenn
                                                              (line  91)
3482
* --enable-unsigned-xori:                Configuring the Build.
3483 104 jeremybenn
                                                              (line  68)
3484 19 jeremybenn
* --file:                                Standalone Simulator.
3485
                                                              (line  24)
3486
* --filename:                            Memory Profiling Utility.
3487
                                                              (line  51)
3488
* --generate:                            Profiling Utility.   (line  34)
3489
* --group:                               Memory Profiling Utility.
3490
                                                              (line  47)
3491
* --help:                                Standalone Simulator.
3492
                                                              (line  20)
3493
* --help (memory profiling utility):     Memory Profiling Utility.
3494
                                                              (line  22)
3495
* --help (profiling utility):            Profiling Utility.   (line  22)
3496
* --interactive:                         Standalone Simulator.
3497
                                                              (line  54)
3498
* --mode:                                Memory Profiling Utility.
3499
                                                              (line  26)
3500
* --nosrv:                               Standalone Simulator.
3501
                                                              (line  32)
3502
* --quiet:                               Profiling Utility.   (line  30)
3503
* --srv:                                 Standalone Simulator.
3504
                                                              (line  40)
3505
* --strict-npc:                          Standalone Simulator.
3506
                                                              (line  57)
3507
* --version:                             Standalone Simulator.
3508
                                                              (line  16)
3509
* --version (memory profiling utility):  Memory Profiling Utility.
3510
                                                              (line  17)
3511
* --version (profiling utility):         Profiling Utility.   (line  17)
3512
* -c:                                    Profiling Utility.   (line  26)
3513
* -d:                                    Standalone Simulator.
3514
                                                              (line  48)
3515
* -f <1>:                                Memory Profiling Utility.
3516
                                                              (line  51)
3517
* -f:                                    Standalone Simulator.
3518
                                                              (line  24)
3519
* -g <1>:                                Memory Profiling Utility.
3520
                                                              (line  47)
3521
* -g:                                    Profiling Utility.   (line  34)
3522
* -h:                                    Standalone Simulator.
3523
                                                              (line  20)
3524
* -h (memory profiling utility):         Memory Profiling Utility.
3525
                                                              (line  22)
3526
* -h (profiling utility):                Profiling Utility.   (line  22)
3527
* -i:                                    Standalone Simulator.
3528
                                                              (line  54)
3529
* -m:                                    Memory Profiling Utility.
3530
                                                              (line  26)
3531
* -q:                                    Profiling Utility.   (line  30)
3532
* -v:                                    Standalone Simulator.
3533
                                                              (line  16)
3534
* -v (memory profiling utility):         Memory Profiling Utility.
3535
                                                              (line  17)
3536
* -v (profiling utility):                Profiling Utility.   (line  17)
3537
* 0x00 UART VAPI sub-command (UART verification): Verification API.
3538
                                                              (line  49)
3539
* 0x01 UART VAPI sub-command (UART verification): Verification API.
3540
                                                              (line  55)
3541
* 0x02 UART VAPI sub-command (UART verification): Verification API.
3542
                                                              (line  59)
3543
* 0x03 UART VAPI sub-command (UART verification): Verification API.
3544
                                                              (line  62)
3545
* 0x04 UART VAPI sub-command (UART verification): Verification API.
3546
                                                              (line  66)
3547
* 16550 (UART configuration):            UART Configuration.  (line  73)
3548 82 jeremybenn
* all tests enabled:                     Configuring the Build.
3549 127 jeremybenn
                                                              (line 105)
3550 19 jeremybenn
* Argtable2 debugging:                   Configuring the Build.
3551 127 jeremybenn
                                                              (line  98)
3552 19 jeremybenn
* ATA/ATAPI configuration:               Disc Interface Configuration.
3553
                                                              (line   6)
3554
* ATA/ATAPI device configuration:        Disc Interface Configuration.
3555
                                                              (line  88)
3556
* base_vapi_id (GPIO configuration - deprecated): GPIO Configuration.
3557
                                                              (line  32)
3558
* baseaddr (ATA/ATAPI configuration):    Disc Interface Configuration.
3559
                                                              (line  22)
3560
* baseaddr (DMA configuration):          DMA Configuration.   (line  24)
3561
* baseaddr (Ethernet configuration):     Ethernet Configuration.
3562
                                                              (line  22)
3563
* baseaddr (frame buffer configuration): Frame Buffer Configuration.
3564
                                                              (line  20)
3565
* baseaddr (generic peripheral configuration): Generic Peripheral Configuration.
3566
                                                              (line  22)
3567
* baseaddr (GPIO configuration):         GPIO Configuration.  (line  21)
3568
* baseaddr (keyboard configuration):     Keyboard Configuration.
3569
                                                              (line  36)
3570
* baseaddr (memory configuration):       Memory Configuration.
3571 98 jeremybenn
                                                              (line  87)
3572 19 jeremybenn
* baseaddr (memory controller configuration): Memory Controller Configuration.
3573 98 jeremybenn
                                                              (line  46)
3574 19 jeremybenn
* baseaddr (UART configuration):         UART Configuration.  (line  22)
3575
* baseaddr (VGA configuration):          Display Interface Configuration.
3576
                                                              (line  26)
3577
* blocksize (cache configuration):       Cache Configuration. (line  29)
3578
* BPB configuration:                     Branch Prediction Configuration.
3579
                                                              (line   6)
3580
* branch prediction configuration:       Branch Prediction Configuration.
3581
                                                              (line   6)
3582
* break (Interactive CLI):               Interactive Command Line.
3583
                                                              (line  57)
3584
* breakpoint list (Interactive CLI):     Interactive Command Line.
3585
                                                              (line  60)
3586
* breakpoint set/clear (Interactive CLI): Interactive Command Line.
3587
                                                              (line  57)
3588
* breaks (Interactive CLI):              Interactive Command Line.
3589
                                                              (line  60)
3590
* btic (branch prediction configuration): Branch Prediction Configuration.
3591
                                                              (line  19)
3592
* byte_enabled (generic peripheral configuration): Generic Peripheral Configuration.
3593
                                                              (line  48)
3594
* cache configuration:                   Cache Configuration. (line   6)
3595
* calling_convention (CUC configuration): CUC Configuration.  (line  34)
3596
* ce (memory configuration):             Memory Configuration.
3597 98 jeremybenn
                                                              (line 117)
3598 19 jeremybenn
* cfgr (CPU configuration):              CPU Configuration.   (line  47)
3599
* channel (UART configuration):          UART Configuration.  (line  29)
3600
* clear breakpoint (Interactive CLI):    Interactive Command Line.
3601
                                                              (line  57)
3602 202 julius
* clkcycle (simulator configuration):    Simulator Behavior.  (line 115)
3603 19 jeremybenn
* cm (Interactive CLI):                  Interactive Command Line.
3604
                                                              (line  54)
3605
* command line for Or1ksim standalone use: Standalone Simulator.
3606
                                                              (line   6)
3607
* complex model:                         Configuring the Build.
3608 104 jeremybenn
                                                              (line  37)
3609 19 jeremybenn
* config:                                Global Data Structures.
3610
                                                              (line   7)
3611
* config.bpb:                            Global Data Structures.
3612
                                                              (line  37)
3613
* config.cpu:                            Global Data Structures.
3614
                                                              (line  22)
3615
* config.cuc:                            Global Data Structures.
3616
                                                              (line  18)
3617
* config.dc:                             Global Data Structures.
3618
                                                              (line  25)
3619
* config.debug:                          Global Data Structures.
3620
                                                              (line  40)
3621
* config.pic:                            Global Data Structures.
3622
                                                              (line  33)
3623
* config.pm:                             Global Data Structures.
3624
                                                              (line  29)
3625
* config.sim:                            Global Data Structures.
3626
                                                              (line  11)
3627
* config.vapi:                           Global Data Structures.
3628
                                                              (line  14)
3629
* configuration dynamic structure:       Global Data Structures.
3630
                                                              (line  49)
3631
* configuration file structure:          Configuration File Format.
3632
                                                              (line   6)
3633
* configuration global structure:        Global Data Structures.
3634
                                                              (line   7)
3635
* configuration info (Interactive CLI):  Interactive Command Line.
3636
                                                              (line 119)
3637
* configuration of generic peripherals:  Generic Peripheral Configuration.
3638
                                                              (line   6)
3639
* configuration parameter setting (Interactive CLI): Interactive Command Line.
3640
                                                              (line 146)
3641
* configuring branch prediction:         Branch Prediction Configuration.
3642
                                                              (line   6)
3643
* configuring data & instruction caches: Cache Configuration. (line   6)
3644
* configuring data & instruction MMUs:   Memory Management Configuration.
3645
                                                              (line   6)
3646
* configuring DMA:                       DMA Configuration.   (line   6)
3647
* configuring memory:                    Memory Configuration.
3648
                                                              (line   6)
3649
* configuring Or1ksim:                   Configuration.       (line   6)
3650
* configuring power management:          Power Management Configuration.
3651
                                                              (line   6)
3652
* configuring the ATA/ATAPI interfaces:  Disc Interface Configuration.
3653
                                                              (line   6)
3654
* configuring the behavior of Or1ksim:   Simulator Behavior.  (line   6)
3655
* configuring the CPU:                   CPU Configuration.   (line   6)
3656
* configuring the Custom Unit Compiler (CUC): CUC Configuration.
3657
                                                              (line   6)
3658
* configuring the debug unit and interface to external debuggers: Debug Interface Configuration.
3659
                                                              (line   6)
3660
* configuring the Ethernet interface:    Ethernet Configuration.
3661
                                                              (line   6)
3662
* configuring the frame buffer:          Frame Buffer Configuration.
3663
                                                              (line   6)
3664
* configuring the GPIO:                  GPIO Configuration.  (line   6)
3665
* configuring the interrupt controller:  Interrupt Configuration.
3666
                                                              (line   6)
3667
* configuring the keyboard interface:    Keyboard Configuration.
3668
                                                              (line   6)
3669
* configuring the memory controller:     Memory Controller Configuration.
3670
                                                              (line   6)
3671
* configuring the processor:             CPU Configuration.   (line   6)
3672
* configuring the PS2 interface:         Keyboard Configuration.
3673
                                                              (line   6)
3674
* configuring the UART:                  UART Configuration.  (line   6)
3675
* configuring the Verification API (VAPI): Verification API Configuration.
3676
                                                              (line   6)
3677
* configuring the VGA interface:         Display Interface Configuration.
3678
                                                              (line   6)
3679
* copying memory (Interactive CLI):      Interactive Command Line.
3680
                                                              (line  54)
3681
* CPU configuration:                     CPU Configuration.   (line   6)
3682
* CUC configuration:                     CUC Configuration.   (line   6)
3683
* Custom Unit Compiler (Interactive CLI): Interactive Command Line.
3684
                                                              (line 162)
3685
* Custom Unit Compiler Configuration:    CUC Configuration.   (line   6)
3686
* data cache configuration:              Cache Configuration. (line   6)
3687
* data MMU configuration:                Memory Management Configuration.
3688
                                                              (line   6)
3689
* DCGE (power management register):      Power Management Configuration.
3690
                                                              (line  21)
3691
* debug (Interactive CLI):               Interactive Command Line.
3692
                                                              (line 151)
3693
* debug (simulator configuration):       Simulator Behavior.  (line  13)
3694
* debug channel toggle (Interactive CLI): Interactive Command Line.
3695
                                                              (line 141)
3696
* debug interface configuration:         Debug Interface Configuration.
3697
                                                              (line   6)
3698
* debug mode toggle (Interactive CLI):   Interactive Command Line.
3699
                                                              (line 151)
3700
* debug unit configuration:              Debug Interface Configuration.
3701
                                                              (line   6)
3702
* Debug Unit verification (VAPI):        Verification API.    (line  34)
3703
* debugging enabled (Argtable2):         Configuring the Build.
3704 127 jeremybenn
                                                              (line  98)
3705 104 jeremybenn
* DejaGnu board configurations:          Regression Testing.  (line  35)
3706
* DejaGnu configuration:                 Regression Testing.  (line  21)
3707
* DejaGNU tests directories:             Regression Testing.  (line  50)
3708
* DejaGnu tool specific configuration:   Regression Testing.  (line  39)
3709 19 jeremybenn
* delayr (memory configuration):         Memory Configuration.
3710 98 jeremybenn
                                                              (line 137)
3711 19 jeremybenn
* delayw (memory configuration):         Memory Configuration.
3712 98 jeremybenn
                                                              (line 143)
3713
* dependstats (CPU configuration):       CPU Configuration.   (line  89)
3714 19 jeremybenn
* dev_id (ATA/ATAPI configuration):      Disc Interface Configuration.
3715
                                                              (line  36)
3716
* disassemble (Interactive CLI):         Interactive Command Line.
3717
                                                              (line  41)
3718
* disc interface configuration:          Disc Interface Configuration.
3719
                                                              (line   6)
3720
* disc interface device configuration:   Disc Interface Configuration.
3721
                                                              (line  88)
3722
* display interface configuration:       Display Interface Configuration.
3723
                                                              (line   6)
3724
* displaying memory (Interactive CLI):   Interactive Command Line.
3725
                                                              (line  31)
3726
* displaying registers (Interactive CLI): Interactive Command Line.
3727
                                                              (line  14)
3728
* dm (Interactive CLI):                  Interactive Command Line.
3729
                                                              (line  31)
3730
* dma (Ethernet configuration):          Ethernet Configuration.
3731
                                                              (line  33)
3732
* DMA configuration:                     DMA Configuration.   (line   6)
3733
* DMA verification (VAPI):               Verification API.    (line  73)
3734
* dma_mode0_td (ATA/ATAPI configuration): Disc Interface Configuration.
3735
                                                              (line  70)
3736
* dma_mode0_teoc (ATA/ATAPI configuration): Disc Interface Configuration.
3737
                                                              (line  71)
3738
* dma_mode0_tm (ATA/ATAPI configuration): Disc Interface Configuration.
3739
                                                              (line  69)
3740
* DME (power management register):       Power Management Configuration.
3741
                                                              (line  15)
3742
* DMMU configuration:                    Memory Management Configuration.
3743
                                                              (line   6)
3744
* doze mode (power management register): Power Management Configuration.
3745
                                                              (line  15)
3746
* dv (Interactive CLI):                  Interactive Command Line.
3747
                                                              (line 124)
3748
* dynamic clock gating (power management register): Power Management Configuration.
3749
                                                              (line  21)
3750
* dynamic model:                         Configuring the Build.
3751 104 jeremybenn
                                                              (line  37)
3752 19 jeremybenn
* dynamic ports, use of:                 Verification API Configuration.
3753
                                                              (line  23)
3754
* edge_trigger (interrupt controller):   Interrupt Configuration.
3755
                                                              (line  16)
3756
* enable_bursts (CUC configuration):     CUC Configuration.   (line  38)
3757
* enabled (ATA/ATAPI configuration):     Disc Interface Configuration.
3758
                                                              (line  18)
3759
* enabled (branch prediction configuration): Branch Prediction Configuration.
3760
                                                              (line  15)
3761
* enabled (cache configuration):         Cache Configuration. (line  11)
3762
* enabled (debug interface configuration): Debug Interface Configuration.
3763
                                                              (line  11)
3764
* enabled (DMA configuration):           DMA Configuration.   (line  20)
3765
* enabled (Ethernet configuration):      Ethernet Configuration.
3766
                                                              (line  18)
3767
* enabled (frame buffer configuration):  Frame Buffer Configuration.
3768
                                                              (line  16)
3769
* enabled (generic peripheral configuration): Generic Peripheral Configuration.
3770
                                                              (line  18)
3771
* enabled (GPIO configuration):          GPIO Configuration.  (line  17)
3772
* enabled (interrupt controller):        Interrupt Configuration.
3773
                                                              (line  12)
3774
* enabled (keyboard configuration):      Keyboard Configuration.
3775
                                                              (line  32)
3776
* enabled (memory controller configuration): Memory Controller Configuration.
3777 98 jeremybenn
                                                              (line  35)
3778 19 jeremybenn
* enabled (MMU configuration):           Memory Management Configuration.
3779
                                                              (line  12)
3780
* enabled (power management configuration): Power Management Configuration.
3781
                                                              (line  35)
3782
* enabled (UART configuration):          UART Configuration.  (line  18)
3783
* enabled (verification API configuration): Verification API Configuration.
3784
                                                              (line  15)
3785
* enabled (VGA configuration):           Display Interface Configuration.
3786
                                                              (line  22)
3787
* enabling Ethernet via socket:          Configuring the Build.
3788 104 jeremybenn
                                                              (line  59)
3789 19 jeremybenn
* entrysize (MMU configuration):         Memory Management Configuration.
3790
                                                              (line  32)
3791
* ETH_VAPI_CTRL (Ethernet verification): Verification API.    (line  86)
3792
* ETH_VAPI_DATA (Ethernet verification): Verification API.    (line  84)
3793
* Ethernet configuration:                Ethernet Configuration.
3794
                                                              (line   6)
3795
* Ethernet verification (VAPI):          Verification API.    (line  78)
3796
* Ethernet via socket, enabling:         Configuring the Build.
3797 104 jeremybenn
                                                              (line  59)
3798 127 jeremybenn
* exclusive-OR immediate operand:        Configuring the Build.
3799
                                                              (line  69)
3800 202 julius
* exe_bin_insn_log (simulator configuration): Simulator Behavior.
3801
                                                              (line 103)
3802
* exe_bin_insn_log_file (simulator configuration): Simulator Behavior.
3803
                                                              (line 111)
3804 82 jeremybenn
* exe_log (simulator configuration):     Simulator Behavior.  (line  49)
3805
* exe_log_end (simulator configuration): Simulator Behavior.  (line  89)
3806
* exe_log_file (simulator configuration): Simulator Behavior. (line  97)
3807 19 jeremybenn
* exe_log_fn (simulator configuration - deprecated): Simulator Behavior.
3808 82 jeremybenn
                                                              (line  97)
3809 19 jeremybenn
* exe_log_marker (simulator configuration): Simulator Behavior.
3810 82 jeremybenn
                                                              (line  93)
3811 19 jeremybenn
* exe_log_start (simulator configuration): Simulator Behavior.
3812 82 jeremybenn
                                                              (line  86)
3813
* exe_log_type (simulator configuration): Simulator Behavior. (line  55)
3814 19 jeremybenn
* exe_log_type=default (simulator configuration): Simulator Behavior.
3815 82 jeremybenn
                                                              (line  58)
3816 19 jeremybenn
* exe_log_type=hardware (simulator configuration): Simulator Behavior.
3817 82 jeremybenn
                                                              (line  62)
3818 19 jeremybenn
* exe_log_type=simple (simulator configuration): Simulator Behavior.
3819 82 jeremybenn
                                                              (line  69)
3820 19 jeremybenn
* exe_log_type=software (simulator configuration): Simulator Behavior.
3821 82 jeremybenn
                                                              (line  74)
3822 19 jeremybenn
* executing code (Interactive CLI):      Interactive Command Line.
3823
                                                              (line  23)
3824
* execution history (Interactive CLI):   Interactive Command Line.
3825
                                                              (line  67)
3826
* file (ATA/ATAPI device configuration): Disc Interface Configuration.
3827
                                                              (line 104)
3828
* file (keyboard configuration):         Keyboard Configuration.
3829
                                                              (line  51)
3830
* filename (frame buffer configuration - deprecated): Frame Buffer Configuration.
3831 82 jeremybenn
                                                              (line  36)
3832 19 jeremybenn
* filename (VGA configuration - deprecated): Display Interface Configuration.
3833
                                                              (line  47)
3834
* firmware (ATA/ATAPI device configuration): Disc Interface Configuration.
3835
                                                              (line 117)
3836
* flag setting by instructions:          Configuring the Build.
3837 127 jeremybenn
                                                              (line 118)
3838 104 jeremybenn
* floating point multiply and add:       Known Issues.        (line  56)
3839
* floating point support:                Known Issues.        (line  42)
3840 19 jeremybenn
* frame buffer configuration:            Frame Buffer Configuration.
3841
                                                              (line   6)
3842
* gdb_enabled (debug interface configuration): Debug Interface Configuration.
3843
                                                              (line  47)
3844
* generic peripheral configuration:      Generic Peripheral Configuration.
3845
                                                              (line   6)
3846
* GPIO configuration:                    GPIO Configuration.  (line   6)
3847
* GPIO verification (VAPI):              Verification API.    (line  88)
3848
* GPIO_VAPI_AUX (GPIO verification):     Verification API.    (line 100)
3849
* GPIO_VAPI_CLOCK (GPIO verification):   Verification API.    (line 103)
3850
* GPIO_VAPI_CTRL (GPIO verification):    Verification API.    (line 119)
3851
* GPIO_VAPI_DATA (GPIO verification):    Verification API.    (line  97)
3852
* GPIO_VAPI_INTE (GPIO verification):    Verification API.    (line 110)
3853
* GPIO_VAPI_PTRIG (GPIO verification):   Verification API.    (line 113)
3854
* GPIO_VAPI_RGPIO (GPIO verification):   Verification API.    (line 107)
3855 100 julius
* hardfloat (CPU configuration):         CPU Configuration.   (line 110)
3856 98 jeremybenn
* hazards (CPU configuration):           CPU Configuration.   (line  74)
3857 19 jeremybenn
* heads (ATA/ATAPI device configuration): Disc Interface Configuration.
3858
                                                              (line 121)
3859
* help (Interactive CLI):                Interactive Command Line.
3860
                                                              (line 170)
3861
* hexadecimal memory dump (Interactive CLI): Interactive Command Line.
3862
                                                              (line 133)
3863
* hide_device_id (verification API configuration): Verification API Configuration.
3864
                                                              (line  36)
3865
* hist (Interactive CLI):                Interactive Command Line.
3866
                                                              (line  67)
3867 82 jeremybenn
* history (simulator configuration):     Simulator Behavior.  (line  40)
3868 19 jeremybenn
* history of execution (Interactive CLI): Interactive Command Line.
3869
                                                              (line  67)
3870
* hitdelay (branch prediction configuration): Branch Prediction Configuration.
3871
                                                              (line  33)
3872
* hitdelay (instruction cache configuration): Cache Configuration.
3873
                                                              (line  38)
3874
* hitdelay (MMU configuration):          Memory Management Configuration.
3875
                                                              (line  51)
3876 104 jeremybenn
* host test code:                        Regression Testing.  (line  57)
3877 19 jeremybenn
* hw_enabled (generic peripheral configuration): Generic Peripheral Configuration.
3878
                                                              (line  49)
3879
* IMMU configuration:                    Memory Management Configuration.
3880
                                                              (line   6)
3881
* index (memory controller configuration): Memory Controller Configuration.
3882 98 jeremybenn
                                                              (line  68)
3883 19 jeremybenn
* info (Interactive CLI):                Interactive Command Line.
3884
                                                              (line 119)
3885
* installing Or1ksim:                    Installation.        (line   6)
3886
* instruction cache configuration:       Cache Configuration. (line   6)
3887
* instruction MMU configuration:         Memory Management Configuration.
3888
                                                              (line   6)
3889
* instruction profiling for Or1ksim:     Profiling Utility.   (line   6)
3890
* instruction profiling utility (Interactive CLI): Interactive Command Line.
3891
                                                              (line 178)
3892
* internal debugging:                    Internal Debugging.  (line   6)
3893
* interrupt controller configuration:    Interrupt Configuration.
3894
                                                              (line   6)
3895
* irq (ATA/ATAPI configuration):         Disc Interface Configuration.
3896
                                                              (line  32)
3897
* irq (DMA configuration):               DMA Configuration.   (line  34)
3898
* irq (GPIO configuration):              GPIO Configuration.  (line  29)
3899
* irq (keyboard configuration):          Keyboard Configuration.
3900
                                                              (line  47)
3901
* irq (UART configuration):              UART Configuration.  (line  70)
3902
* irq (VGA configuration):               Display Interface Configuration.
3903
                                                              (line  37)
3904
* jitter (UART configuration):           UART Configuration.  (line  78)
3905
* keyboard configuration:                Keyboard Configuration.
3906
                                                              (line   6)
3907 104 jeremybenn
* lf.madd.s:                             Known Issues.        (line  56)
3908 19 jeremybenn
* library version of Or1ksim:            Simulator Library.   (line   6)
3909
* license for Or1ksim:                   GNU Free Documentation License.
3910
                                                              (line   6)
3911
* list breakpoints (Interactive CLI):    Interactive Command Line.
3912
                                                              (line  60)
3913
* load_hitdelay (data cache configuration): Cache Configuration.
3914
                                                              (line  46)
3915
* load_missdelay (data cache configuration): Cache Configuration.
3916
                                                              (line  50)
3917
* log (memory configuration):            Memory Configuration.
3918 98 jeremybenn
                                                              (line 149)
3919 19 jeremybenn
* log_enabled (verification API configuration): Verification API Configuration.
3920
                                                              (line  28)
3921 93 jeremybenn
* long:                                  Simulator Library.   (line  87)
3922 104 jeremybenn
* make file for tests:                   Regression Testing.  (line  27)
3923 19 jeremybenn
* mc (memory configuration):             Memory Configuration.
3924 98 jeremybenn
                                                              (line 126)
3925 19 jeremybenn
* memory configuration:                  Memory Configuration.
3926
                                                              (line   6)
3927
* memory controller configuration:       Memory Controller Configuration.
3928
                                                              (line   6)
3929
* memory copying (Interactive CLI):      Interactive Command Line.
3930
                                                              (line  54)
3931
* memory display (Interactive CLI):      Interactive Command Line.
3932
                                                              (line  31)
3933
* memory dump, hexadecimal (Interactive CLI): Interactive Command Line.
3934
                                                              (line 133)
3935
* memory dump, Verilog (Interactive CLI): Interactive Command Line.
3936
                                                              (line 124)
3937
* memory patching (Interactive CLI):     Interactive Command Line.
3938
                                                              (line  48)
3939
* memory profiling end address:          Memory Profiling Utility.
3940
                                                              (line  56)
3941
* memory profiling start address:        Memory Profiling Utility.
3942
                                                              (line  56)
3943
* memory profiling utility (Interactive CLI): Interactive Command Line.
3944
                                                              (line 173)
3945
* memory profiling version of Or1ksim:   Memory Profiling Utility.
3946
                                                              (line   6)
3947
* memory_order (CUC configuration):      CUC Configuration.   (line  15)
3948
* memory_order=exact (CUC configuration): CUC Configuration.  (line  27)
3949
* memory_order=none (CUC configuration): CUC Configuration.   (line  18)
3950
* memory_order=strong (CUC configuration): CUC Configuration. (line  25)
3951
* memory_order=weak (CUC configuration): CUC Configuration.   (line  21)
3952
* missdelay (branch prediction configuration): Branch Prediction Configuration.
3953
                                                              (line  37)
3954
* missdelay (instruction cache configuration): Cache Configuration.
3955
                                                              (line  42)
3956
* missdelay (MMU configuration):         Memory Management Configuration.
3957
                                                              (line  55)
3958
* MMU configuration:                     Memory Management Configuration.
3959
                                                              (line   6)
3960 82 jeremybenn
* mprof_file (simulator configuration):  Simulator Behavior.  (line  34)
3961 19 jeremybenn
* mprof_fn (simulator configuration - deprecated): Simulator Behavior.
3962 82 jeremybenn
                                                              (line  34)
3963 19 jeremybenn
* mprofile (Interactive CLI):            Interactive Command Line.
3964
                                                              (line 173)
3965 82 jeremybenn
* mprofile (simulator configuration):    Simulator Behavior.  (line  29)
3966 19 jeremybenn
* mwdma (ATA/ATAPI device configuration): Disc Interface Configuration.
3967
                                                              (line 128)
3968
* name (generic peripheral configuration): Generic Peripheral Configuration.
3969
                                                              (line  42)
3970
* name (memory configuration):           Memory Configuration.
3971 98 jeremybenn
                                                              (line 108)
3972 19 jeremybenn
* no_multicycle (CUC configuration):     CUC Configuration.   (line  42)
3973
* nsets (cache configuration):           Cache Configuration. (line  15)
3974
* nsets (MMU configuration):             Memory Management Configuration.
3975
                                                              (line  16)
3976
* nways (cache configuration):           Cache Configuration. (line  22)
3977
* nways (MMU configuration):             Memory Management Configuration.
3978
                                                              (line  22)
3979 93 jeremybenn
* or1ksim_get_time_period:               Simulator Library.   (line  77)
3980
* or1ksim_init:                          Simulator Library.   (line  14)
3981
* or1ksim_interrupt:                     Simulator Library.   (line  92)
3982
* or1ksim_interrupt_clear:               Simulator Library.   (line 110)
3983
* or1ksim_interrupt_set:                 Simulator Library.   (line 101)
3984
* or1ksim_is_le:                         Simulator Library.   (line  82)
3985 104 jeremybenn
* or1ksim_jtag_reset:                    Simulator Library.   (line 119)
3986
* or1ksim_jtag_shift_dr:                 Simulator Library.   (line 141)
3987
* or1ksim_jtag_shift_ir:                 Simulator Library.   (line 127)
3988 93 jeremybenn
* or1ksim_reset_duration:                Simulator Library.   (line  62)
3989
* or1ksim_run:                           Simulator Library.   (line  57)
3990
* or1ksim_set_time_point:                Simulator Library.   (line  73)
3991 19 jeremybenn
* output rediretion:                     Concepts.            (line   7)
3992
* overflow flag setting by instructions: Configuring the Build.
3993 127 jeremybenn
                                                              (line 133)
3994 19 jeremybenn
* packet (ATA/ATAPI device configuration): Disc Interface Configuration.
3995
                                                              (line 113)
3996
* pagesize (MMU configuration):          Memory Management Configuration.
3997
                                                              (line  27)
3998
* patching memory (Interactive CLI):     Interactive Command Line.
3999
                                                              (line  48)
4000
* patching registers (Interactive CLI):  Interactive Command Line.
4001
                                                              (line  28)
4002
* patching the program counter (Interactive CLI): Interactive Command Line.
4003
                                                              (line  51)
4004
* pattern (memory configuration):        Memory Configuration.
4005 98 jeremybenn
                                                              (line  75)
4006 19 jeremybenn
* pc (Interactive CLI):                  Interactive Command Line.
4007
                                                              (line  51)
4008
* PIC configuration:                     Interrupt Configuration.
4009
                                                              (line   6)
4010
* pio (ATA/ATAPI device configuration):  Disc Interface Configuration.
4011
                                                              (line 132)
4012
* pio_mode0_t1 (ATA/ATAPI configuration): Disc Interface Configuration.
4013
                                                              (line  51)
4014
* pio_mode0_t2 (ATA/ATAPI configuration): Disc Interface Configuration.
4015
                                                              (line  52)
4016
* pio_mode0_t4 (ATA/ATAPI configuration): Disc Interface Configuration.
4017
                                                              (line  53)
4018
* pio_mode0_teoc (ATA/ATAPI configuration): Disc Interface Configuration.
4019
                                                              (line  54)
4020
* pm (Interactive CLI):                  Interactive Command Line.
4021
                                                              (line  48)
4022
* PMR - DGCE:                            Power Management Configuration.
4023
                                                              (line  21)
4024
* PMR - DME:                             Power Management Configuration.
4025
                                                              (line  15)
4026
* PMR - SDF:                             Power Management Configuration.
4027
                                                              (line  12)
4028
* PMR - SME:                             Power Management Configuration.
4029
                                                              (line  16)
4030
* PMR - SUME:                            Power Management Configuration.
4031
                                                              (line  24)
4032
* PMU configuration:                     Power Management Configuration.
4033
                                                              (line   6)
4034
* poc (memory controller configuration): Memory Controller Configuration.
4035 98 jeremybenn
                                                              (line  55)
4036 19 jeremybenn
* port range for TCP/IP:                 Verification API Configuration.
4037
                                                              (line  23)
4038
* power management configuration:        Power Management Configuration.
4039
                                                              (line   6)
4040
* power management register, DGCE:       Power Management Configuration.
4041
                                                              (line  21)
4042
* power management register, DME:        Power Management Configuration.
4043
                                                              (line  15)
4044
* power management register, SDF:        Power Management Configuration.
4045
                                                              (line  12)
4046
* power management register, SME:        Power Management Configuration.
4047
                                                              (line  16)
4048
* power management register, SUME:       Power Management Configuration.
4049
                                                              (line  24)
4050
* pr (Interactive CLI):                  Interactive Command Line.
4051
                                                              (line  28)
4052
* private ports, use of:                 Verification API Configuration.
4053
                                                              (line  23)
4054
* processor configuration:               CPU Configuration.   (line   6)
4055
* processor stall (Interactive CLI):     Interactive Command Line.
4056
                                                              (line  72)
4057
* processor unstall (Interactive CLI):   Interactive Command Line.
4058
                                                              (line  78)
4059
* prof_file (simulator configuration):   Simulator Behavior.  (line  23)
4060
* prof_fn (simulator configuration - deprecated): Simulator Behavior.
4061
                                                              (line  23)
4062
* profile (simulator configuration):     Simulator Behavior.  (line  19)
4063
* profiling for Or1ksim:                 Profiling Utility.   (line   6)
4064
* profiling utility (Interactive CLI):   Interactive Command Line.
4065
                                                              (line 178)
4066
* program counter patching (Interactive CLI): Interactive Command Line.
4067
                                                              (line  51)
4068
* programmable interrupt controller configuration: Interrupt Configuration.
4069
                                                              (line   6)
4070
* PS2 configuration:                     Keyboard Configuration.
4071
                                                              (line   6)
4072
* q (Interactive CLI):                   Interactive Command Line.
4073
                                                              (line  11)
4074
* quitting (Interactive CLI):            Interactive Command Line.
4075
                                                              (line  11)
4076
* r (Interactive CLI):                   Interactive Command Line.
4077
                                                              (line  14)
4078
* random_seed (memory configuration):    Memory Configuration.
4079 98 jeremybenn
                                                              (line  65)
4080 19 jeremybenn
* refresh_rate (frame buffer configuration): Frame Buffer Configuration.
4081 82 jeremybenn
                                                              (line  30)
4082 19 jeremybenn
* refresh_rate (VGA configuration):      Display Interface Configuration.
4083
                                                              (line  41)
4084
* reg_sim_reset:                         Concepts.            (line  13)
4085
* register display (Interactive CLI):    Interactive Command Line.
4086
                                                              (line  14)
4087
* register over time statistics:         Configuring the Build.
4088 127 jeremybenn
                                                              (line  92)
4089 19 jeremybenn
* register patching (Interactive CLI):   Interactive Command Line.
4090
                                                              (line  28)
4091 104 jeremybenn
* regression testing:                    Regression Testing.  (line   6)
4092 19 jeremybenn
* Remote Serial Protocol:                Debug Interface Configuration.
4093
                                                              (line  20)
4094
* reset (Interactive CLI):               Interactive Command Line.
4095
                                                              (line  63)
4096
* reset hooks:                           Concepts.            (line  13)
4097
* reset the simulator (Interactive CLI): Interactive Command Line.
4098
                                                              (line  63)
4099
* rev (ATA/ATAPI configuration):         Disc Interface Configuration.
4100
                                                              (line  44)
4101
* rev (CPU configuration):               CPU Configuration.   (line  15)
4102
* rsp_enabled (debug interface configuration): Debug Interface Configuration.
4103
                                                              (line  20)
4104
* rsp_port (debug interface configuration): Debug Interface Configuration.
4105
                                                              (line  36)
4106
* rtx_type (Ethernet configuration):     Ethernet Configuration.
4107
                                                              (line  46)
4108
* run (Interactive CLI):                 Interactive Command Line.
4109
                                                              (line  23)
4110
* running code (Interactive CLI):        Interactive Command Line.
4111
                                                              (line  23)
4112
* running Or1ksim:                       Usage.               (line   6)
4113
* runtime:                               Global Data Structures.
4114
                                                              (line  58)
4115
* runtime global structure:              Global Data Structures.
4116
                                                              (line  58)
4117
* runtime.cpu:                           Global Data Structures.
4118
                                                              (line  62)
4119
* runtime.cpu.fout:                      Concepts.            (line   7)
4120
* runtime.cuc:                           Global Data Structures.
4121
                                                              (line  62)
4122
* runtime.vapi:                          Global Data Structures.
4123
                                                              (line  62)
4124
* rx_channel (Ethernet configuration):   Ethernet Configuration.
4125
                                                              (line  59)
4126
* rxfile (Ethernet configuration):       Ethernet Configuration.
4127
                                                              (line  68)
4128
* sbp_bf_fwd (branch prediction configuration): Branch Prediction Configuration.
4129
                                                              (line  23)
4130
* sbp_bnf_fwd (branch prediction configuration): Branch Prediction Configuration.
4131
                                                              (line  28)
4132 98 jeremybenn
* sbuf_len (CPU configuration):          CPU Configuration.   (line 101)
4133 19 jeremybenn
* SDF (power management register):       Power Management Configuration.
4134
                                                              (line  12)
4135
* section ata:                           Disc Interface Configuration.
4136
                                                              (line   6)
4137
* section bpb:                           Branch Prediction Configuration.
4138
                                                              (line   6)
4139
* section cpio:                          GPIO Configuration.  (line   6)
4140
* section cpu:                           CPU Configuration.   (line   6)
4141
* section cuc:                           CUC Configuration.   (line   6)
4142
* section dc:                            Cache Configuration. (line   6)
4143
* section debug:                         Debug Interface Configuration.
4144
                                                              (line   6)
4145
* section dma:                           DMA Configuration.   (line   6)
4146
* section dmmu:                          Memory Management Configuration.
4147
                                                              (line   6)
4148
* section ethernet:                      Ethernet Configuration.
4149
                                                              (line   6)
4150
* section fb:                            Frame Buffer Configuration.
4151
                                                              (line   6)
4152
* section generic:                       Generic Peripheral Configuration.
4153
                                                              (line   6)
4154
* section ic:                            Cache Configuration. (line   6)
4155
* section immu:                          Memory Management Configuration.
4156
                                                              (line   6)
4157
* section kb:                            Keyboard Configuration.
4158
                                                              (line   6)
4159
* section mc:                            Memory Controller Configuration.
4160
                                                              (line   6)
4161
* section memory:                        Memory Configuration.
4162
                                                              (line   6)
4163
* section pic:                           Interrupt Configuration.
4164
                                                              (line   6)
4165
* section pmu:                           Power Management Configuration.
4166
                                                              (line   6)
4167
* section sim:                           Simulator Behavior.  (line   6)
4168
* section uart:                          UART Configuration.  (line   6)
4169
* section vapi:                          Verification API Configuration.
4170
                                                              (line   6)
4171
* section vga:                           Display Interface Configuration.
4172
                                                              (line   6)
4173
* sections:                              Global Data Structures.
4174
                                                              (line  49)
4175
* sectors (ATA/ATAPI device configuration): Disc Interface Configuration.
4176
                                                              (line 125)
4177
* server_port (debug interface configuration): Debug Interface Configuration.
4178
                                                              (line  69)
4179
* server_port (verification API configuration): Verification API Configuration.
4180
                                                              (line  19)
4181
* set (Interactive CLI):                 Interactive Command Line.
4182
                                                              (line 146)
4183
* set breakpoint (Interactive CLI):      Interactive Command Line.
4184
                                                              (line  57)
4185
* setdbch (Interactive CLI):             Interactive Command Line.
4186
                                                              (line 141)
4187
* simple model:                          Configuring the Build.
4188 104 jeremybenn
                                                              (line  37)
4189 19 jeremybenn
* simulator configuration:               Simulator Behavior.  (line   6)
4190
* simulator configuration info (Interactive CLI): Interactive Command Line.
4191
                                                              (line 119)
4192
* simulator reset (Interactive CLI):     Interactive Command Line.
4193
                                                              (line  63)
4194
* simulator statistics (Interactive CLI): Interactive Command Line.
4195
                                                              (line  83)
4196
* size (ATA/ATAPI device configuration): Disc Interface Configuration.
4197
                                                              (line 109)
4198
* size (generic peripheral configuration): Generic Peripheral Configuration.
4199
                                                              (line  30)
4200
* size (memory configuration):           Memory Configuration.
4201 98 jeremybenn
                                                              (line  92)
4202 19 jeremybenn
* sleep mode (power management register): Power Management Configuration.
4203
                                                              (line  16)
4204
* slow down factor (power management register): Power Management Configuration.
4205
                                                              (line  12)
4206
* SME (power management register):       Power Management Configuration.
4207
                                                              (line  16)
4208
* sockif (Ethernet configuration):       Ethernet Configuration.
4209
                                                              (line  83)
4210
* sr (CPU configuration):                CPU Configuration.   (line  53)
4211
* stall (Interactive CLI):               Interactive Command Line.
4212
                                                              (line  72)
4213
* stall the processor (Interactive CLI): Interactive Command Line.
4214
                                                              (line  72)
4215
* statistics, register over time:        Configuring the Build.
4216 127 jeremybenn
                                                              (line  92)
4217 19 jeremybenn
* statistics, simulation (Interactive CLI): Interactive Command Line.
4218
                                                              (line  83)
4219
* stats (Interactive CLI):               Interactive Command Line.
4220
                                                              (line  83)
4221
* stepping code (Interactive CLI):       Interactive Command Line.
4222
                                                              (line  19)
4223
* store_hitdelay (data cache configuration): Cache Configuration.
4224
                                                              (line  54)
4225
* store_missdelay (data cache configuration): Cache Configuration.
4226
                                                              (line  58)
4227
* SUME (power management register):      Power Management Configuration.
4228
                                                              (line  24)
4229 98 jeremybenn
* superscalar (CPU configuration):       CPU Configuration.   (line  63)
4230 19 jeremybenn
* suspend mode (power management register): Power Management Configuration.
4231
                                                              (line  24)
4232
* t (Interactive CLI):                   Interactive Command Line.
4233
                                                              (line  19)
4234 104 jeremybenn
* target test code:                      Regression Testing.  (line  63)
4235 19 jeremybenn
* TCP/IP port range:                     Verification API Configuration.
4236
                                                              (line  23)
4237
* TCP/IP port range for or1ksim service: Debug Interface Configuration.
4238
                                                              (line  74)
4239
* TCP/IP port range for or1ksim-rsp service: Debug Interface Configuration.
4240
                                                              (line  41)
4241 104 jeremybenn
* test code for host:                    Regression Testing.  (line  57)
4242
* test code for target:                  Regression Testing.  (line  63)
4243
* test make file:                        Regression Testing.  (line  27)
4244
* test README:                           Regression Testing.  (line  32)
4245
* testing:                               Regression Testing.  (line   6)
4246 82 jeremybenn
* tests, all enabled.:                   Configuring the Build.
4247 127 jeremybenn
                                                              (line 105)
4248 19 jeremybenn
* timings_file (CUC configuration):      CUC Configuration.   (line  46)
4249
* timings_fn (CUC configuration - deprecated): CUC Configuration.
4250
                                                              (line  46)
4251
* toggle breakpoint (Interactive CLI):   Interactive Command Line.
4252
                                                              (line  57)
4253
* toggle debug channels (Interactive CLI): Interactive Command Line.
4254
                                                              (line 141)
4255
* toggle debug mode (Interactive CLI):   Interactive Command Line.
4256
                                                              (line 151)
4257
* tx_channel (Ethernet configuration):   Ethernet Configuration.
4258
                                                              (line  60)
4259
* txfile (Ethernet configuration):       Ethernet Configuration.
4260
                                                              (line  69)
4261
* txfile (frame buffer configuration):   Frame Buffer Configuration.
4262 82 jeremybenn
                                                              (line  36)
4263 19 jeremybenn
* txfile (VGA configuration):            Display Interface Configuration.
4264
                                                              (line  47)
4265
* type (ATA/ATAPI device configuration): Disc Interface Configuration.
4266
                                                              (line  99)
4267
* type (memory configuration):           Memory Configuration.
4268 98 jeremybenn
                                                              (line  36)
4269 19 jeremybenn
* type=pattern (memory configuration):   Memory Configuration.
4270 98 jeremybenn
                                                              (line  46)
4271 19 jeremybenn
* type=random (memory configuration):    Memory Configuration.
4272 98 jeremybenn
                                                              (line  40)
4273 19 jeremybenn
* type=unknown (memory configuration):   Memory Configuration.
4274 98 jeremybenn
                                                              (line  50)
4275 19 jeremybenn
* type=zero (memory configuration):      Memory Configuration.
4276 98 jeremybenn
                                                              (line  54)
4277 19 jeremybenn
* UART configuration:                    UART Configuration.  (line   6)
4278
* UART I/O from/to a physical serial port: UART Configuration.
4279
                                                              (line  62)
4280
* UART I/O from/to an xterm:             UART Configuration.  (line  38)
4281
* UART I/O from/to files:                UART Configuration.  (line  33)
4282
* UART I/O from/to open file descriptors: UART Configuration. (line  58)
4283
* UART I/O from/to TCP/IP:               UART Configuration.  (line  45)
4284
* UART verification (VAPI):              Verification API.    (line  41)
4285
* unstall (Interactive CLI):             Interactive Command Line.
4286
                                                              (line  78)
4287
* unstall the processor (Interactive CLI): Interactive Command Line.
4288
                                                              (line  78)
4289
* upr (CPU configuration):               CPU Configuration.   (line  21)
4290
* ustates (cache configuration):         Cache Configuration. (line  33)
4291
* ustates (MMU configuration):           Memory Management Configuration.
4292
                                                              (line  41)
4293
* VAPI configuration:                    Verification API Configuration.
4294
                                                              (line   6)
4295
* VAPI for Debug Unit:                   Verification API.    (line  34)
4296
* VAPI for DMA:                          Verification API.    (line  73)
4297
* VAPI for Ethernet:                     Verification API.    (line  78)
4298
* VAPI for GPIO:                         Verification API.    (line  88)
4299
* VAPI for UART:                         Verification API.    (line  41)
4300
* vapi_id (debug interface configuration): Debug Interface Configuration.
4301
                                                              (line  80)
4302
* vapi_id (DMA configuration) <1>:       Ethernet Configuration.
4303
                                                              (line  88)
4304
* vapi_id (DMA configuration):           DMA Configuration.   (line  38)
4305
* vapi_id (GPIO configuration):          GPIO Configuration.  (line  32)
4306
* vapi_id (UART configuration):          UART Configuration.  (line  85)
4307
* vapi_log_file (verification API configuration): Verification API Configuration.
4308
                                                              (line  41)
4309
* vapi_log_fn (verification API configuration - deprecated): Verification API Configuration.
4310
                                                              (line  41)
4311
* ver (CPU configuration):               CPU Configuration.   (line  15)
4312
* verbose (simulator configuration):     Simulator Behavior.  (line  10)
4313
* Verification API configuration:        Verification API Configuration.
4314
                                                              (line   6)
4315
* Verilog memory dump (Interactive CLI): Interactive Command Line.
4316
                                                              (line 124)
4317
* VGA configuration:                     Display Interface Configuration.
4318
 
4319
 
4320
                                                              (line  50)
4321
4322
4323

4324
Tag Table:
4325 233 julius
Node: Top830
4326
Node: Installation1240
4327
Node: Preparation1487
4328
Node: Configuring the Build1782
4329
Node: Build and Install7896
4330
Node: Known Issues8742
4331
Node: Usage11804
4332
Node: Standalone Simulator12018
4333
Node: Profiling Utility14921
4334
Node: Memory Profiling Utility15831
4335
Node: Simulator Library17196
4336
Node: Configuration24974
4337
Node: Configuration File Format25586
4338
Node: Configuration File Preprocessing25878
4339
Node: Configuration File Syntax26175
4340
Node: Simulator Configuration28960
4341
Node: Simulator Behavior29251
4342
Node: Verification API Configuration33780
4343
Node: CUC Configuration35720
4344
Node: Core OpenRISC Configuration37637
4345
Node: CPU Configuration38139
4346
Node: Memory Configuration42257
4347
Node: Memory Management Configuration48715
4348
Node: Cache Configuration51092
4349
Node: Interrupt Configuration53478
4350
Node: Power Management Configuration54214
4351
Node: Branch Prediction Configuration55491
4352
Node: Debug Interface Configuration56851
4353
Node: Peripheral Configuration61071
4354
Node: Memory Controller Configuration61697
4355
Node: UART Configuration65111
4356
Node: DMA Configuration68630
4357
Node: Ethernet Configuration70497
4358
Node: GPIO Configuration74473
4359
Node: Display Interface Configuration76106
4360
Node: Frame Buffer Configuration78415
4361
Node: Keyboard Configuration80279
4362
Node: Disc Interface Configuration82517
4363
Node: Generic Peripheral Configuration87460
4364
Node: Interactive Command Line89755
4365
Node: Verification API96729
4366
Node: Code Internals101159
4367
Node: Coding Conventions101742
4368
Node: Global Data Structures106169
4369
Node: Concepts108826
4370
Ref: Output Redirection108971
4371
Node: Internal Debugging109510
4372
Node: Regression Testing110034
4373
Node: GNU Free Documentation License113829

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