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This is ../../doc/or1ksim.info, produced by makeinfo version 4.13 from
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../../doc/or1ksim.texi.
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INFO-DIR-SECTION Embedded development
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START-INFO-DIR-ENTRY
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* Or1ksim: (or32-elf-or1ksim).  The OpenRISC 1000 Architectural
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                                        Simulator
8
END-INFO-DIR-ENTRY
9
 
10
This file documents the OpenRISC Architectural Simulator, Or1ksim.
11
 
12
Copyright (C) 2008, 2009 Embecosm Limited.
13
 
14
     Permission is granted to copy, distribute and/or modify this
15
     document under the terms of the GNU Free Documentation License,
16
     Version 1.2 or any later version published by the Free Software
17
     Foundation; with no Invariant Sections, with no Front-Cover Texts,
18
     and with no Back-Cover Texts.  A copy of the license is included
19
     in the section entitled "GNU Free Documentation License".
20
 
21

22
File: or1ksim.info,  Node: Top,  Next: Installation,  Up: (dir)
23
 
24
Scope of this Document
25
**********************
26
 
27
This document is the user guide for Or1ksim, the OpenRISC 1000
28
Architectural Simulator.
29
 
30
* Menu:
31
 
32
* Installation::
33
* Usage::
34
* Configuration::
35
* Interactive Command Line::
36
* Verification API::
37
 
38
* Code Internals::
39
 
40
* GNU Free Documentation License::  The license for this documentation
41
* Index::
42
 
43

44
File: or1ksim.info,  Node: Installation,  Next: Usage,  Prev: Top,  Up: Top
45
 
46
1 Installation
47
**************
48
 
49
Installation follows standard GNU protocols.
50
 
51
* Menu:
52
 
53
* Preparation::
54
* Configuring the Build::
55
* Build and Install::
56
* Known Issues::
57
 
58

59
File: or1ksim.info,  Node: Preparation,  Next: Configuring the Build,  Up: Installation
60
 
61
1.1 Preparation
62
===============
63
 
64
Unpack the software and create a _separate_ directory in which to build
65
it:
66
 
67 460 jeremybenn
     tar jxf or1ksim-2011-01-05.tar.bz2
68 19 jeremybenn
     mkdir builddir_or1ksim
69
     cd builddir_or1ksim
70
 
71

72
File: or1ksim.info,  Node: Configuring the Build,  Next: Build and Install,  Prev: Preparation,  Up: Installation
73
 
74
1.2 Configuring the Build
75
=========================
76
 
77
Configure the software using the `configure' script in the main
78
directory.
79
 
80
The most significant argument is `--target', which should specify the
81 82 jeremybenn
OpenRISC 1000 32-bit architecture.  If this argument is omitted, it will
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default to OpenRISC 1000 32-bit with a warning
83
 
84 460 jeremybenn
     ../or1ksim-2011-01-05/configure --target=or32-elf ...
85 19 jeremybenn
 
86
There are several other options available, many of which are standard
87 82 jeremybenn
to GNU `configure' scripts.  Use `configure --help' to see all the
88
options.  The most useful is `--prefix' to specify a directory for
89 19 jeremybenn
installation of the tools.
90
 
91 385 jeremybenn
For testing (using `make check'), the `--target' parameter may be
92
specified, to allow the target tool chain to be selected.  If not
93
specified, it will default to `or32-elf', which is the same prefix used
94
with the standard OpenRISC toolchain installation script.
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96 104 jeremybenn
A number of Or1ksim specific features in the simulator do require
97
enabling at configuration.  These include
98
 
99 19 jeremybenn
`--enable-profiling'
100
`--disable-profiling'
101 82 jeremybenn
     If enabled, Or1ksim is compiled for profiling with `gprof'.  This
102
     is disabled by default.  Only really of value for developers of
103 19 jeremybenn
     Or1ksim.
104
 
105
`--enable-execution=simple'
106
`--enable-execution=complex'
107
`--enable-execution=dynamic'
108
     Or1ksim has developed to improve functionality and performance.
109
     This feature allows three versions of Or1ksim to be built
110
 
111
    `--enable-execution=simple'
112
          Build the original simple interpreting simulator
113
 
114
    `--enable-execution=complex'
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          Build a more complex interpreting simulator.  Experiments
116
          suggest this is 50% faster than the simple simulator.  This
117
          is the default.
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119
    `--enable-execution=dynamic'
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          Build a dynamically compiling simulator.  This is the way
121
          many modern ISS are built.  This represents a work in
122
          progress.  Currently Or1ksim will compile, but segfaults if
123
          configured with this option.
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125
 
126
     The default is `--enable-execution=complex'.
127
 
128
`--enable-ethphy'
129
`--disable-ethphy'
130
     If enabled, this option allows the Ethernet to be simulated by
131
     connecting via a socket (the alternative reads and writes, from
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     and to files).  This must then be configured using the relevant
133
     fields in the `ethernet' section of the configuration file.  *Note
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     Ethernet Configuration: Ethernet Configuration.
135
 
136
     The default is for this to be disabled.
137
 
138 127 jeremybenn
`--enable-unsigned-xori'
139
`--disable-unsigned-xori'
140 346 jeremybenn
     Historically, `l.xori', has sign extended its operand.  This is
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     inconsistent with the other logical opcodes (`l.andi', `l.ori'),
142
     but in the absence of `l.not', it allows a register to be inverted
143
     in a single instruction using:
144
 
145
          `l.xori  rD,rA,-1'
146
 
147
     This flag causes Or1ksim to treat the immediate operand as
148
     unsigned (i.e to zero-extend rather than sign-extend).
149
 
150
     The default is to sign-extend, so that existing code will continue
151
     to work.
152
 
153
          Caution: The GNU compiler tool chain makes heavy use of this
154
          instruction.  Using unsigned behavior will require the
155
          compiler to be modified accordingly.
156
 
157
          This option is provided for experimentation.  A future
158
          version of OpenRISC may adopt this more consistent behavior
159
          and also provide a `l.not' opcode.
160
 
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`--enable-range-stats'
162
`--disable-range-stats'
163
     If enabled, this option allows statistics to be collected to
164 82 jeremybenn
     analyse register access over time.  The default is for this to be
165 19 jeremybenn
     disabled.
166
 
167
`--enable-debug'
168
`--disable-debug'
169
     This is a feature of the Argtable2 package used to process
170 82 jeremybenn
     arguments.  If enabled, some debugging features are turned on in
171
     Argtable2.  It is provided for completeness, but there is no
172
     reason why this feature should ever be needed by any Or1ksim user.
173 19 jeremybenn
 
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`--enable-all-tests'
175
`--disable-all-tests'
176
     Some of the tests (at the time of writing just one) will not
177
     compile without error.  If enabled with this flag, all test
178
     programs will be compiled with `make check'.
179 19 jeremybenn
 
180 82 jeremybenn
     This flag is intended for those working on the test package, who
181
     wish to get the missing test(s) working.
182
 
183
 
184 112 jeremybenn
A number of configuration flags have been removed since version 0.3.0,
185 346 jeremybenn
because they led to invalid behavior of Or1ksim.  Those removed are:
186 112 jeremybenn
 
187 124 jeremybenn
`--enable-arith-flag'
188
`--disable-arith-flag'
189
     If enabled, this option caused certain instructions to set the flag
190
     (`F' bit) in the supervision register if the result were zero.
191
     The instructions affected by this were `l.add', `l.addc',
192
     `l.addi', `l.and' and `l.andi'.
193
 
194 346 jeremybenn
     If set, this caused incorrect behavior.  Whether or not flags are
195 124 jeremybenn
     set is part of the OpenRISC 1000 architectural specification.  The
196
     only flags which should set this are the "set flag" instructions:
197
     `l.sfeq', `l.sfeqi', `l.sfges', `l.sfgesi', `l.sfgeu', `l.sfgeui',
198
     `l.sfgts', `l.sfgtsi', `l.sfgtu', `l.sfgtui', `l.sfles',
199
     `l.sflesi', `l.sfleu', `l.sfleui', `l.sflts', `l.sfltsi',
200
     `l.sfltu', `l.sfltui', `l.sfne' and `l.sfnei'.
201
 
202 112 jeremybenn
`--enable-ov-flag'
203
`--disable-ov-flag'
204 124 jeremybenn
     This flag caused certain instructions to set the overflow flag.
205
     If not, those instructions would not set the overflow flat.  The
206
     instructions affected by this were `l.add', `l.addc', `l.addi',
207
     `l.and', `l.andi', `l.div', `l.divu', `l.mul', `l.muli', `l.or',
208
     `l.ori', `l.sll', `l.slli', `l.srl', `l.srli', `l.sra', `l.srai',
209
     `l.sub', `l.xor' and `l.xori'.
210 112 jeremybenn
 
211
     This guaranteed incorrect behavior.  The OpenRISC 1000 architecture
212
     specification defines which flags are set by which instructions.
213
 
214
     Within the above list, the arithmetic instructions (`l.add',
215
     `l.addc', `l.addi', `l.div', `l.divu', `l.mul', `l.muli' and
216
     `l.sub'), together with `l.addic' which is missed out, set the
217
     overflow flag.  All the others (`l.and', `l.andi', `l.or',
218
     `l.ori', `l.sll', `l.slli', `l.srl', `l.srli', `l.sra', `l.srai',
219
     `l.xor' and `l.xori') do not.
220
 
221
 
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223
File: or1ksim.info,  Node: Build and Install,  Next: Known Issues,  Prev: Configuring the Build,  Up: Installation
224
 
225
1.3 Building and Installing
226
===========================
227
 
228 82 jeremybenn
Build the tool with:
229 19 jeremybenn
 
230
     make all
231 82 jeremybenn
 
232
If you have the OpenRISC tool chain and DejaGNU installed, you can
233
verify the tool as follows (otherwise omit this step):
234
 
235
     make check
236
 
237
Install the tool with:
238
 
239 19 jeremybenn
     make install
240
 
241
This will install the three variations of the Or1ksim tool,
242 442 julius
`or32-elf-sim', `or32-elf-psim' and `or32-elf-mpsim', the Or1ksim
243
library, `libsim', the header file, `or1ksim.h' and this documentation
244
in `info' format.
245 19 jeremybenn
 
246
The documentation may be created and installed in alternative formats
247
(PDF, Postscript, DVI, HTML) with for example:
248
 
249
     make pdf
250
     make install-pdf
251
 
252

253
File: or1ksim.info,  Node: Known Issues,  Prev: Build and Install,  Up: Installation
254
 
255
1.4 Known Problems and Issues
256
=============================
257
 
258 346 jeremybenn
Full details of outstanding issues may be found in the `NEWS' file in
259
the main directory of the distribution.  The OpenRISC tracker may be
260
used to see the current state of these issues and to raise new problems
261
and feature requests.  It may be found at bugtracker.
262 19 jeremybenn
 
263 346 jeremybenn
The following issues are long standing and unlikely to be fixed in
264
Or1ksim in the near future.
265
 
266 19 jeremybenn
   * The Supervision Register Little Endian Enable (LEE) bit is
267 82 jeremybenn
     ignored.  Or1ksim can be built for either little endian or big
268 19 jeremybenn
     endian use, but that behavior cannot be changed dynamically.
269
 
270
   * Or1ksim is not reentrant, so a program cannot instantiate multiple
271 82 jeremybenn
     instances using the library.  This is clearly a problem when
272
     considering multi-core applications.  However it stems from the
273
     original design, and can only be fixed by a complete rewrite.  The
274 19 jeremybenn
     entire source code uses static global constants liberally!
275
 
276
 
277

278
File: or1ksim.info,  Node: Usage,  Next: Configuration,  Prev: Installation,  Up: Top
279
 
280
2 Usage
281
*******
282
 
283
* Menu:
284
 
285
* Standalone Simulator::
286
* Profiling Utility::
287
* Memory Profiling Utility::
288 442 julius
* Trace Generation::
289 19 jeremybenn
* Simulator Library::
290 440 jeremybenn
* Ethernet TUN/TAP Interface::
291 460 jeremybenn
* l.nop Support::
292 19 jeremybenn
 
293

294
File: or1ksim.info,  Node: Standalone Simulator,  Next: Profiling Utility,  Up: Usage
295
 
296
2.1 Standalone Simulator
297
========================
298
 
299
The general form the standalone command is:
300
 
301 442 julius
     or32-elf-sim [-vhiqVt] [-f FILE] [--nosrv] [--srv=[N]]
302 346 jeremybenn
                      [-m ][-d STR]
303 19 jeremybenn
                      [--enable-profile] [--enable-mprofile] [FILE]
304
 
305 82 jeremybenn
Many of the options have both a short and a long form.  For example
306
`-h' or `--help'.
307 19 jeremybenn
 
308
`-v'
309
`--version'
310
     Print out the version and copyright notice for Or1ksim and exit.
311
 
312
`-h'
313
`--help'
314
     Print out help about the command line options and what they mean.
315
 
316 346 jeremybenn
`-i'
317
`--interactive'
318
     After starting, drop into the Or1ksim interactive command shell.
319
 
320
`-q'
321
`--quiet'
322
     Do not generate any information messages, only error messages.
323
 
324
`-V'
325
`--verbose'
326
     Generate extra output messages (equivalent of specifying the
327
     "verbose" option in the simulator configuration section (see *note
328
     Simulator Behavior: Simulator Behavior.).
329
 
330 385 jeremybenn
`-t'
331
`--trace'
332 420 jeremybenn
     Dump instruction just executed and any register/memory location
333
     chaged after each instruction (one line per instruction).
334 385 jeremybenn
 
335 472 jeremybenn
`--trace-physical'
336
`--trace-virtual'
337
     When tracing instructions, show the physical address
338
     (`--trace-physical') and/or the virtual address
339
     (`--trace-virtual') of the instruction being executed.  Both flags
340
     may be specified, in which case both physical and virtual
341
     addresses are shown, physical first.
342
 
343
          Note: Either or both flags may be specified without
344
          `--trace', to indicate how addresses should be shown if
345
          subsequently enabled by a `SIGUSER1' signal or `l.nop 8'
346
          opcode (*note Trace Generation: Trace Generation.).
347
 
348 19 jeremybenn
`-f FILE'
349 385 jeremybenn
`--file=FILE'
350 19 jeremybenn
     Read configuration commands from the specified file, looking first
351
     in the current directory, and otherwise in the `$HOME/.or1k'
352 82 jeremybenn
     directory.  If this argument is not specified, the file `sim.cfg'
353
     in those two locations is used.  Failure to find the file is a
354
     fatal error.  *Note Configuration: Configuration, for detailed
355
     information on configuring Or1ksim.
356 19 jeremybenn
 
357
`--nosrv'
358 235 jeremybenn
     Do not start up the "Remote Serial Protocol" debug server.  This
359
     overrides any setting specified in the configuration file.  This
360
     option may not be specified with `--srv'.  If it is, a rude
361
     message is printed and the `--nosrv' option is ignored.
362 19 jeremybenn
 
363
`--srv'
364
 
365
`--srv=N'
366 235 jeremybenn
     Start up the "Remote Serial Protocol" debug server.  This
367
     overrides any setting specified in the configuration file.  If the
368
     parameter, N, is specified, use that as the TCP/IP port for the
369
     server, otherwise a random value from the private port range
370
     (41920-65535) will be used.  This option may not be specified with
371
     `--nosrv'.  If it is, a rude message is printed and the `--nosrv'
372
     option is ignored.
373 19 jeremybenn
 
374 385 jeremybenn
`-m SIZE'
375 346 jeremybenn
`--memory=SIZE'
376
     Configure a memory block of SIZE bytes, starting at address zero.
377
     The size may be followed by `k', `K', `m', `M', `g', `G', to
378
     indicate kilobytes (2^10 bytes), megabytes (2^20 bytes) and
379
     gigabytes (2^30 bytes).
380
 
381
     This is mainly intended for use when Or1ksim is used without a
382
     configuration file, to allow just the processor and memory to be
383
     set up.  This is the equivalent of specifying a configuration
384
     memory section with `baseaddr = 0' and `size = SIZE' and all other
385
     parameters taking their default value.
386
 
387
     If a configuration file is also used, it should be sure not to
388
     specify an overlapping memory block.
389
 
390 385 jeremybenn
`-d CONFIG_STRING'
391 19 jeremybenn
`--debug-config=CONFIG_STRING'
392 82 jeremybenn
     Enable selected debug messages in Or1ksim.  This parameter is for
393
     use by developers only, and is not covered further here.  See the
394 19 jeremybenn
     source code for more details.
395
 
396 346 jeremybenn
`--report-memory-errors'
397
     By default all exceptions are now handled silently.  If this
398
     option is specified, bus exceptions will be reported with a
399
     message to standard error indicating the address at which the
400
     exception occurred.
401 19 jeremybenn
 
402 346 jeremybenn
     This was the default behaviour up to Or1ksim 0.4.0.  This flag is
403
     provided for those who wish to keep that behavior.
404
 
405 19 jeremybenn
`--strict-npc'
406
     In real hardware, setting the next program counter (NPC, SPR 16),
407 82 jeremybenn
     flushes the processor pipeline.  The consequence of this is that
408
     until the pipeline refills, reading the NPC will return zero.
409
     This is typically the case when debugging, since the processor is
410 19 jeremybenn
     stalled.
411
 
412
     Historically, Or1ksim has always returned the value of the NPC,
413 82 jeremybenn
     irrespective of when it is changed.  If the `--strict-npc' option
414
     is used, then Or1ksim will mirror real hardware more accurately.
415
     If the NPC is changed while the processor is stalled, subsequent
416 19 jeremybenn
     reads of its value will return 0 until the processor is unstalled.
417
 
418
     This is not currently the default behavior, since tools such as
419
     GDB have been implemented assuming the historic Or1ksim behavior.
420
     However at some time in the future it will become the default.
421
 
422
`--enable-profile'
423
     Enable instruction profiling.
424
 
425
`--enable-mprofile'
426
     Enable memory profiling.
427
 
428
 
429

430
File: or1ksim.info,  Node: Profiling Utility,  Next: Memory Profiling Utility,  Prev: Standalone Simulator,  Up: Usage
431
 
432
2.2 Profiling Utility
433
=====================
434
 
435 82 jeremybenn
This utility analyses instruction profile data generated by Or1ksim.
436
It may be invoked as a standalone command, or from the Or1ksim CLI.
437
The general form the standalone command is:
438 19 jeremybenn
 
439 442 julius
     or32-elf-profile [-vhcq] [-g=FILE]
440 19 jeremybenn
 
441 82 jeremybenn
Many of the options have both a short and a long form.  For example
442
`-h' or `--help'.
443 19 jeremybenn
 
444
`-v'
445
`--version'
446
     Print out the version and copyright notice for the Or1ksim
447
     profiling utility and exit.
448
 
449
`-h'
450
`--help'
451
     Print out help about the command line options and what they mean.
452
 
453
`-c'
454
`--cumulative'
455
     Show cumulative sum of cycles in functions
456
 
457
`-q'
458
`--quiet'
459
     Suppress messages
460
 
461
`-g=FILE'
462
`--generate=FILE'
463 82 jeremybenn
     The data file to analyse.  If omitted, the default file,
464 19 jeremybenn
     `sim.profile' is used.
465
 
466
 
467

468 442 julius
File: or1ksim.info,  Node: Memory Profiling Utility,  Next: Trace Generation,  Prev: Profiling Utility,  Up: Usage
469 19 jeremybenn
 
470
2.3 Memory Profiling Utility
471
============================
472
 
473 82 jeremybenn
This utility analyses memory profile data generated by Or1ksim.  It may
474
be invoked as a standalone command, or from the Or1ksim CLI.  The
475 19 jeremybenn
general form the standalone command is:
476
 
477 442 julius
     or32-elf-mprofile  [-vh] [-m=M] [-g=N] [-f=FILE] FROM TO
478 19 jeremybenn
 
479 82 jeremybenn
Many of the options have both a short and a long form.  For example
480
`-h' or `--help'.
481 19 jeremybenn
 
482
`-v'
483
`--version'
484
     Print out the version and copyright notice for the Or1ksim memory
485
     profiling utility and exit.
486
 
487
`-h'
488
`--help'
489
     Print out help about the command line options and what they mean.
490
 
491
`-m=M'
492
`--mode=M'
493 82 jeremybenn
     Specify the mode out output.  Permitted options are
494 19 jeremybenn
 
495
    `detailed'
496
    `d'
497 82 jeremybenn
          Detailed output.  This is the default if no mode is specified.
498 19 jeremybenn
 
499
    `pretty'
500
    `p'
501
          Pretty printed output.
502
 
503
    `access'
504
    `a'
505
          Memory accesses only.
506
 
507
    `width'
508
    `w'
509
          Access width only.
510
 
511
 
512
`-g=N'
513
`--group=N'
514
     Group 2^n bits of successive addresses together.
515
 
516
`-f=FILE'
517
`--filename=FILE'
518 82 jeremybenn
     The data file to analyse.  If not specified, the default,
519 19 jeremybenn
     `sim.profile' is used.
520
 
521
`FROM'
522
`TO'
523
     FROM and TO are respectively the start and end address of the
524
     region of memory to be analysed.
525
 
526
 
527

528 442 julius
File: or1ksim.info,  Node: Trace Generation,  Next: Simulator Library,  Prev: Memory Profiling Utility,  Up: Usage
529 19 jeremybenn
 
530 442 julius
2.4 Trace Generation
531
====================
532
 
533
An execution trace can be generated at run time with options passed by
534
the command line, or via the operating system's signal passing
535 472 jeremybenn
mechanism, or by `l.nop' opcodes in an application program.
536 442 julius
 
537 472 jeremybenn
The following flag can be used to create an execution dump.
538 450 jeremybenn
 
539 442 julius
`-t'
540
`--trace'
541
     Dump instruction just executed and any register/memory location
542 472 jeremybenn
     changed after each instruction (one line per instruction).  Each
543
     line starts with either "S" or "U" to indicate whether the
544
     processor was in supervisor or user mode _when the instruction
545
     completed_.  It is worth bearing in mind that tracing happens at
546
     completion of instruction execution and shows the state at that
547
     time.
548 442 julius
 
549 450 jeremybenn
Passing a signal `SIGUSR1' while the simulator is running toggles trace
550
generation. This can be done with the following command, assuming
551
Or1ksim's executable name is `or32-elf-sim':
552
 
553
     pkill -SIGUSR1 or32-elf-sim
554
 
555
This is useful in the case where trace output is desired after a
556
significant amount of simulation time, where it would be inconvenient to
557
generate trace up to that point.
558
 
559
If the `pkill' utility is not available, the `kill' utility can be used
560
if Or1ksim's process number is known. Use the following to determine
561
the process ID of the `or32-elf-sim' and then send the `SIGUSR1'
562
command to toggle execution trace generation:
563
 
564
     ps a | grep or32-elf-sim
565
     kill -SIGUSR1 _process-number_
566
 
567 472 jeremybenn
Tracing can also be enabled and disabled from within a target program
568
using the `l.nop 8' and `l.nop 9' opcodes to enable and disable tracing
569
respectively.
570
 
571
By default tracing will show the virtual address of each instruction
572
traced.  This may be controlled by two options, `--trace-physical' to
573
show the physical address and/or `--trace-virtual' to show the virtual
574
address. If neither is specified, the virtual address is shown.
575
 
576
     Note: Either or both flags may be specified without `--trace', to
577
     indicate how addresses should be shown if subsequently enabled by a
578
     `SIGUSER1' signal or `l.nop 8' opcode.
579
 
580 442 julius

581
File: or1ksim.info,  Node: Simulator Library,  Next: Ethernet TUN/TAP Interface,  Prev: Trace Generation,  Up: Usage
582
 
583
2.5 Simulator Library
584 19 jeremybenn
=====================
585
 
586
Or1ksim may be used as a static of dynamic library, `libsim.a' or
587 82 jeremybenn
`libsim.so'.  When compiling with the static library, the flag, `-lsim'
588 19 jeremybenn
should be added to the link command.
589
 
590
The header file `or1ksim.h' contains appropriate declarations of the
591 82 jeremybenn
functions exported by the Or1ksim library.  These are:
592 19 jeremybenn
 
593 346 jeremybenn
 -- `or1ksim.h': int or1ksim_init (int ARGC, char *ARGV, void
594 432 jeremybenn
          *CLASS_PTR, int (*UPR)(void *CLASS_PTR, unsigned long int
595
          ADDR, unsigned char MASK[], unsigned char RDATA[], int
596
          DATA_LEN), int (*UPW)(void *CLASS_PTR, unsigned long int
597
          ADDR, unsigned char MASK[], unsigned char WDATA[], int
598
          DATA_LEN))
599 346 jeremybenn
     The initialization function is supplied with a vector of arguments,
600
     which are interpreted as arguments to the standalone version (see
601
     *note Standalone Simulator: Standalone Simulator.), a pointer to
602
     the calling class, CLASS_PTR (since the library may be used from
603
     C++) and two up-call functions, one for reads, UPR, and one for
604
     writes, UPW.
605 19 jeremybenn
 
606
     UPW is called for any write to an address external to the model
607 82 jeremybenn
     (determined by a `generic' section in the configuration file).
608
     UPR is called for any reads to an external address.  The CLASS_PTR
609
     is passed back with these upcalls, allowing the function to
610
     associate the call with the class which originally initialized the
611 93 jeremybenn
     library.  Both UPW and UPR should return zero on success and
612
     non-zero otherwise.  At the present time the meaning of non-zero
613
     values is not defined but this may change in the future.
614 19 jeremybenn
 
615 93 jeremybenn
     MASK indicates which bytes in the data are to be written or read.
616 82 jeremybenn
     Bytes to be read/written should have 0xff set in MASK.  Otherwise
617 93 jeremybenn
     the byte should be zero.  The adddress, ADDR, is the _full_
618
     address, since the upcall function must handle all generic
619
     devices, using the full address for decoding.
620 19 jeremybenn
 
621 346 jeremybenn
     Endianness is not a concern, since Or1ksim is transferring byte
622
     vectors, not multi-byte values.
623 19 jeremybenn
 
624 346 jeremybenn
     The result indicates whether the initialization was successful.
625
     The integer values are available as an `enum or1ksim', with
626
     possible values `OR1KSIM_RC_OK' and `OR1KSIM_RC_BADINIT'.
627 19 jeremybenn
 
628 346 jeremybenn
          Caution: This is a change from versions 0.3.0 and 0.4.0.  It
629
          further simplifies the interface, and makes Or1ksim more
630
          consistent with payload representation in SystemC TLM 2.0.
631
 
632 93 jeremybenn
          Note: The current implementation of Or1ksim always transfers
633
          single words (4 bytes), using masks if smaller values are
634
          required.  In this it mimcs the behavior of the WishBone bus.
635
 
636
 
637 19 jeremybenn
 -- `or1ksim.h': int or1ksim_run (double DURATION)
638
     Run the simulator for the simulated duration specified (in
639 346 jeremybenn
     seconds).  A duration of -1 indicates `run forever'
640 19 jeremybenn
 
641 346 jeremybenn
     The result indicates how the run terminated.  The integer values
642
     are available as an `enum or1ksim', with possible values
643
     `OR1KSIM_RC_OK' (ran for the full duration), `OR1KSIM_RC_BRKPT'
644
     (terminated early due to hitting a breakpoint) and
645
     `OR1KSIM_RC_HALTED' (terminated early due to hitting `l.nop 1').
646 19 jeremybenn
 
647 346 jeremybenn
 
648 19 jeremybenn
 -- `or1ksim.h': void or1ksim_reset_duration (double DURATION)
649
     Change the duration of a run specified in an earlier call to
650 82 jeremybenn
     `or1ksim_run'.  Typically this is called from an upcall, which
651 19 jeremybenn
     realizes it needs to change the duration of the run specified in
652
     the call to `or1ksim_run' that has been interrupted by the upcall.
653
 
654
     The time specified is the amount of time that the run must continue
655
     for (i.e the duration from _now_, not the duration from the
656
     original call to `or1ksim_run').
657
 
658
 
659
 -- `or1ksim.h': void or1ksim_set_time_point ()
660 82 jeremybenn
     Set a timing point.  For use with `or1ksim_get_time_period'.
661 19 jeremybenn
 
662
 
663
 -- `or1ksim.h': double or1ksim_get_time_period ()
664
     Return the simulated time (in seconds) that has elapsed since the
665
     last call to `or1ksim_set_time_point'.
666
 
667
 
668
 -- `or1ksim.h': int or1ksim_is_le ()
669
     Return 1 (logical true) if the Or1ksim simulation is
670
     little-endian, 0 otherwise.
671
 
672
 
673
 -- `or1ksim.h': unsigned long int or1ksim_clock_rate ()
674 82 jeremybenn
     Return the Or1ksim clock rate (in Hz).  This is the value
675
     specified in the configuration file.
676 19 jeremybenn
 
677
 
678
 -- `or1ksim.h': void or1ksim_interrupt (int I)
679 82 jeremybenn
     Generate an edge-triggered interrupt on interrupt line I.  The
680 432 jeremybenn
     interrupt must be cleared separately by clearing the corresponding
681
     bit in the PICSR SPR.  Until the interrupt is cleared, any further
682
     interrupts on the same line will be ignored with a warning.  A
683
     warning will be generated and the interrupt request ignored if
684
     level sensitive interrupts have been configured with the
685
     programmable interrupt controller (*note Interrupt Configuration:
686
     Interrupt Configuration.).
687 19 jeremybenn
 
688
 
689
 -- `or1ksim.h': void or1ksim_interrupt_set (int I)
690 82 jeremybenn
     Assert a level-triggered interrupt on interrupt line I.  The
691 19 jeremybenn
     interrupt must be cleared separately by an explicit call to
692 432 jeremybenn
     `or1ksim_interrupt_clear'.  Until the interrupt is cleared, any
693
     further setting of interrupts on the same line will be ignored
694
     with a warning.  A warning will be generated, and the interrupt
695
     request ignored if edge sensitive interrupts have been configured
696
     with the programmable interrupt controller (*note Interrupt
697
     Configuration: Interrupt Configuration.).
698 19 jeremybenn
 
699
 
700
 -- `or1ksim.h': void or1ksim_interrupt_clear (int I)
701
     Clear a level-triggered interrupt on interrupt line I, which was
702 82 jeremybenn
     previously asserted by a call to `or1ksim_interrupt_set'.  A
703 19 jeremybenn
     warning will be generated, and the interrupt request ignored if
704
     edge sensitive interrupts have been configured with the
705
     programmable interrupt controller (*note Interrupt Configuration:
706
     Interrupt Configuration.).
707
 
708
 
709 104 jeremybenn
 -- `or1ksim.h': double or1ksim_jtag_reset ()
710 346 jeremybenn
     Drive a reset sequence through the JTAG interface.  Return the
711 104 jeremybenn
     (model) time taken for this action.  Remember that the JTAG has
712
     its own clock, which can be an order of magnitude slower than the
713
     main clock, so even a reset (5 JTAG cycles) could take 50
714
     processor clock cycles to complete.
715
 
716
 
717 432 jeremybenn
 -- `or1ksim.h': double or1ksim_jtag_shift_ir (unsigned char *JREG, int
718
          NUM_BITS)
719 104 jeremybenn
     Shift the supplied register through the JTAG instruction register.
720 346 jeremybenn
     Return the (model) time taken for this action.  The register is
721 104 jeremybenn
     supplied as a byte vector, with the least significant bits in the
722
     least significant byte.  If the total number of bits is not an
723
     exact number of bytes, then the odd bits are found in the least
724
     significant end of the highest numbered byte.
725
 
726
     For example a 12-bit register would have bits 0-7 in byte 0 and
727
     bits 11-8 in the least significant 4 bits of byte 1.
728
 
729
 
730 432 jeremybenn
 -- `or1ksim.h': double or1ksim_jtag_shift_dr (unsigned char *JREG, int
731
          NUM_BITS)
732 104 jeremybenn
     Shift the supplied register through the JTAG data register.
733 346 jeremybenn
     Return the (model) time taken for this action.  The register is
734 104 jeremybenn
     supplied as a byte vector, with the least significant bits in the
735
     least significant byte.  If the total number of bits is not an
736
     exact number of bytes, then the odd bits are found in the least
737
     significant end of the highest numbered byte.
738
 
739
     For example a 12-bit register would have bits 0-7 in byte 0 and
740
     bits 11-8 in the least significant 4 bits of byte 1.
741
 
742
 
743 432 jeremybenn
 -- `or1ksim.h': int or1ksim_read_mem (unsigned long int ADDR, unsigned
744
          char *BUF, int LEN)
745 346 jeremybenn
     Read LEN bytes from ADDR, placing the result in BUF.  Return LEN
746
     on success and 0 on failure.
747
 
748
          Note: This function was added in Or1ksim 0.5.0.
749
 
750
 
751 432 jeremybenn
 -- `or1ksim.h': int or1ksim_write_mem (unsigned long int ADDR, const
752
          unsigned char *BUF, int LEN)
753 346 jeremybenn
     Write LEN bytes to ADDR, taking the data from BUF.  Return LEN on
754
     success and 0 on failure.
755
 
756
          Note: This function was added in Or1ksim 0.5.0.
757
 
758
 
759 432 jeremybenn
 -- `or1ksim.h': int or1ksim_read_spr (int SPRNUM, unsigned long int
760
          *SPRVAL_PTR)
761 346 jeremybenn
     Read the SPR specified by SPRNUM, placing the result in
762
     SPRVAL_PTR.  Return non-zero on success and 0 on failure.
763
 
764
          Note: This function was added in Or1ksim 0.5.0.
765
 
766
 
767 432 jeremybenn
 -- `or1ksim.h': int or1ksim_write_spr (int SPRNUM, unsigned long int
768
          SPRVA)
769 346 jeremybenn
     Write SPRVAL to the SPR specified by SPRNUM.  Return non-zero on
770
     success and 0 on failure.
771
 
772
          Note: This function was added in Or1ksim 0.5.0.
773
 
774
 
775 432 jeremybenn
 -- `or1ksim.h': int or1ksim_read_reg (int REGNUM, unsigned long int
776
          *REGVAL_PTR)
777 346 jeremybenn
     Read the general purpose register specified by REGNUM, placing the
778
     result in REGVAL_PTR.  Return non-zero on success and 0 on failure.
779
 
780
          Note: This function was added in Or1ksim 0.5.0.
781
 
782
 
783 432 jeremybenn
 -- `or1ksim.h': int or1ksim_write_reg (int REGNUM, unsigned long int
784
          REGVA)
785 346 jeremybenn
     Write REGVAL to the general purpose register specified by REGNUM.
786
     Return non-zero on success and 0 on failure.
787
 
788
          Note: This function was added in Or1ksim 0.5.0.
789
 
790
 
791 432 jeremybenn
 -- `or1ksim.h': void or1ksim_set_stall_state (int STATE)
792 346 jeremybenn
     Set the processor's state according to STATE (1 = stalled, 0 = not
793
     stalled).
794
 
795
          Note: This function was added in Or1ksim 0.5.0.
796
 
797
 
798 19 jeremybenn
The libraries will be installed in the `lib' sub-directory of the main
799
installation directory (as specified with the `--prefix' option to the
800
`configure' script).
801
 
802
For example if the main installation directory is `/opt/or1ksim', the
803 82 jeremybenn
library will be found in the `/opt/or1ksim/lib' directory.  It is
804 19 jeremybenn
available as both a static library (`libsim.a') and a shared object
805
(`libsim.so').
806
 
807
To link against the library add the `-lsim' flag when linking and do
808
one of the following:
809
 
810
   * Add the library directory to the `LD_LIBRARY_PATH' environment
811 82 jeremybenn
     variable during execution.  For example:
812 19 jeremybenn
 
813
          export LD_LIBRARY_PATH=/opt/or1ksim/lib:$LD_LIBRARY_PATH
814
 
815
   * Add the library directory to the `LD_RUN_PATH' environment
816 82 jeremybenn
     variable during linking.  For example:
817 19 jeremybenn
 
818
          export LD_RUN_PATH=/opt/or1ksim/lib:$LD_RUN_PATH
819
 
820
   * Use the linker `--rpath' option and specify the library directory
821 82 jeremybenn
     when linking your program.  For example
822 19 jeremybenn
 
823 82 jeremybenn
          gcc ...  -Wl,--rpath -Wl,/opt/or1ksim/lib ...
824 19 jeremybenn
 
825
   * Add the library directory to `/etc/ld.so.conf'
826
 
827
 
828

829 460 jeremybenn
File: or1ksim.info,  Node: Ethernet TUN/TAP Interface,  Next: l.nop Support,  Prev: Simulator Library,  Up: Usage
830 440 jeremybenn
 
831 442 julius
2.6 Ethernet TUN/TAP Interface
832 440 jeremybenn
==============================
833
 
834
When an Ethernet peripheral is configured (*note Ethernet
835
Configuration: Ethernet Configuration.), one option is to tunnel
836
traffic through a TUN/TAP interface.  The low level TAP interface is
837
used to tunnel raw Ethernet datagrams.
838
 
839
The TAP interface can then be connected to a physical Ethernet through a
840
bridge, allowing the Or1ksim model to connect to a physical network.
841
This is particularly when Or1ksim is running the OpenRISC Linux kernel
842
image.
843
 
844
This section explains how to set up a bridge for use by Or1ksim. It does
845
require superuser access to the host machine (or at least the relevant
846
network capabilities). A system administrator can modify these
847
guidelines so they are executed on reboot if appropriate.
848
 
849
* Menu:
850
 
851
* Setting Up a Persistent TAP device::
852
* Establishing a Bridge::
853
* Opening the Firewall::
854
* Disabling Ethernet Filtering::
855
* Networking from OpenRISC Linux and BusyBox::
856
* Tearing Down a Bridge::
857
 
858

859
File: or1ksim.info,  Node: Setting Up a Persistent TAP device,  Next: Establishing a Bridge,  Up: Ethernet TUN/TAP Interface
860
 
861 442 julius
2.6.1 Setting Up a Persistent TAP device
862 440 jeremybenn
----------------------------------------
863
 
864
TUN/TAP devices can be created dynamically, but this requires superuser
865
privileges (or at least `CAP_NET_ADMIN' capability).  The solution is
866
to create a persistent TAP device.  This can be done using either
867
`openvpn' or `tunctl'.  In either case the package must be installed on
868
the host system.  Using `openvpn', the following would set up a TAP
869
interface for a specified user and group.
870
 
871
     openvpn --mktun --dev tap_n_ --user _username_ --group _groupname_
872
 
873

874
File: or1ksim.info,  Node: Establishing a Bridge,  Next: Opening the Firewall,  Prev: Setting Up a Persistent TAP device,  Up: Ethernet TUN/TAP Interface
875
 
876 442 julius
2.6.2 Establishing a Bridge
877 440 jeremybenn
---------------------------
878
 
879
A bridge is a "virtual" local area network interfaces, subsuming two or
880
more existing network interfaces.  In this case we will bridge the
881
physical Ethernet interface of the host with the TAP interface that
882
will be used by Or1ksim.
883
 
884
The Ethernet and TAP must lose their own individual IP addresses (by
885
setting them to 0.0.0.0) and are replaced by the IP address of the
886
bridge interface. To do this we use the `bridge-utils' package, which
887
must be installed on the host system. These commands are require
888
superuser privileges or `CAP_NET_ADMIN' capability. To create a new
889
interface `br_n_' the following commands are appropriate.
890
 
891
     brctl addbr br_n_
892
     brctl addif br_n_ eth_x_
893
     brctl addif br_n_ tap_y_
894
 
895
     ifconfig eth_x_ 0.0.0.0 promisc up
896
     ifconfig tap_y_ 0.0.0.0 promisc up
897
 
898
     dhclient br_n_
899
 
900
The last command instructs the bridge to obtain its IP address, netmask,
901
broadcast address, gateway and nameserver information using DHCP.  In a
902
network without DHCP it should be replaced by `ifconfig' to set a
903
static IP address, netmask and broadcast address.
904
 
905
     Note: This will leave a spare dhclient process running in the
906
     background, which should be killed for tidiness. There is a
907
     technique to avoid this using `omshell', but that is beyond the
908
     scope of this guide.
909
 
910
     Note: It is not clear to the author why the existing interfaces
911
     need to be brought up in promiscuous mode, but it seems to cure
912
     various problems.
913
 
914

915
File: or1ksim.info,  Node: Opening the Firewall,  Next: Disabling Ethernet Filtering,  Prev: Establishing a Bridge,  Up: Ethernet TUN/TAP Interface
916
 
917 442 julius
2.6.3 Opening the Firewall
918 440 jeremybenn
--------------------------
919
 
920
Firewall rules should be added to ensure traffic flows freely through
921
the TAP and bridge interfaces. As superuser the following commands are
922
appropriate.
923
 
924
     iptables -A INPUT -i tap_y_ -j ACCEPT
925
     iptables -A INPUT -i br_n_ -j ACCEPT
926
     iptables -A FORWARD -i br_n_ -j ACCEPT
927
 
928

929
File: or1ksim.info,  Node: Disabling Ethernet Filtering,  Next: Networking from OpenRISC Linux and BusyBox,  Prev: Opening the Firewall,  Up: Ethernet TUN/TAP Interface
930
 
931 442 julius
2.6.4 Disabling Ethernet Filtering
932 440 jeremybenn
----------------------------------
933
 
934
Some systems may have ethernet filtering enabled (`ebtables',
935
`bridge-nf', `arptables') which will stop traffic flowing through the
936
bridge.
937
 
938
The easiest way to disable this is by writing zero to all `bridge-nf-*'
939
entries in `/proc/sys/net/bridge'. As superuser the following commands
940
will achieve this.
941
 
942
     cd /proc/sys/net/bridge
943
     for f in bridge-nf-*; do echo 0 > $f; done
944
 
945

946
File: or1ksim.info,  Node: Networking from OpenRISC Linux and BusyBox,  Next: Tearing Down a Bridge,  Prev: Disabling Ethernet Filtering,  Up: Ethernet TUN/TAP Interface
947
 
948 442 julius
2.6.5 Networking from OpenRISC Linux and BusyBox
949 440 jeremybenn
------------------------------------------------
950
 
951
The main use of this style of Ethernet interface to Or1ksim is when
952
running the OpenRISC Linux kernel with BusyBox. The following commands
953
in the BusyBox console window will configure the Ethernet interface
954
(assumed to be `eth0') and bring it up with a DHCP assigned address.
955
 
956
     ifconfig eth0
957
     ifup eth0
958
 
959
At this stage interface to IP addresses will work correctly.
960
 
961
For DNS to work the BusyBox system needs to know where to find a
962
nameserver.  Under BusyBox, `udhcp' does not configure
963
`/etc/resolv.conf' automatically.
964
 
965
The solution is to duplicate the nameserver entry from the
966
`/etc/resolv.conf' file of the host on the BusyBox system. A typical
967
file might be as follows:
968
 
969
     `nameserver 192.168.0.1'
970
 
971
It is convenient to make this permanent within the Linux initramfs. Add
972
the file as `arch/openrisc/support/initramfs/etc/resolv.conf' within
973
the Linux source tree and rebuild `vmlinux'. It will then be present
974
automatically.
975
 
976
One of the most useful functions that is possible is to mount the host
977
file system through NFS. For example, from the BusyBox console:
978
 
979
     mount -t nfs -o nolock 192.168.0.60:/home /mnt
980
 
981
Another useful technique is to telnet into the BusyBox system from the
982
host. This is particularly valuable when a console process locks up,
983
since the `xterm' console will not recognize ctrl-C. Instead the rogue
984
process can be killed from a telnet connection.
985
 
986

987
File: or1ksim.info,  Node: Tearing Down a Bridge,  Prev: Networking from OpenRISC Linux and BusyBox,  Up: Ethernet TUN/TAP Interface
988
 
989 442 julius
2.6.6 Tearing Down a Bridge
990 440 jeremybenn
---------------------------
991
 
992
There is little reason why a bridge should ever need to be torn down,
993
but if desired, the following commands will achieve the effect.
994
 
995
     ifconfig br_n_ down
996
     brctl delbr br_n_
997
 
998
     dhclient eth_x_
999
 
1000
As before this will leave a spare `dhclient' process in the background
1001
which should be killed.
1002
 
1003
If desired the TAP interface can be deleted using
1004
 
1005
     openvpn --rmtun -dev tap_y_
1006
 
1007
     Caution: The TAP interface should not be in use when running this
1008
     command. For example any OpenRISC Linux/BusyBox sessions should be
1009
     closed first.
1010
 
1011

1012 460 jeremybenn
File: or1ksim.info,  Node: l.nop Support,  Prev: Ethernet TUN/TAP Interface,  Up: Usage
1013
 
1014
2.7 l.nop Opcode Support
1015
========================
1016
 
1017
The OpenRISC `l.nop' opcode can take a parameter.  This has no effect
1018
on the semantics of the opcode, but can be used to trigger side effect
1019
behavior in a simulator.  Within Or1ksim, the following parameters are
1020
supported.
1021
 
1022
`l.nop 0'
1023
     The equivalent to `l.nop' with no parameter. Has no side effects.
1024
 
1025
`l.nop 1'
1026
     Execution of Or1ksim is terminated. This is used to implement the
1027
     library `exit' functions.
1028
 
1029
`l.nop 2'
1030
     Report the value in `r3' on the console as a 32-bit hex value.
1031
 
1032
`l.nop 3'
1033
     In earlier versions of Or1ksim this treated `r3' as a pointer to a
1034
     `printf' style format string, and regsiters `r4' through `r8' as
1035
     parameters for that format string.
1036
 
1037
     This opcode is no longer supported, and has no effect if used.
1038
 
1039
`l.nop 4'
1040
     The value in `r3' is printed to standard output as an ASCII
1041
     character.  All library output routines are implemented using this
1042
     opcode.
1043
 
1044
`l.nop 5'
1045
     The statistics counters are reset.
1046
 
1047
`l.nop 6'
1048
     The number of clock ticks since start of execution (a 64-bit
1049
     value) is returned in `r11' (low 32 bits) and `r12' (high 32 bits).
1050
 
1051
`l.nop 7'
1052
     The number of picoseconds per clock cycle is returned in `r11'.
1053
     This is used with `l.nop 6' to implement timing functions.
1054
 
1055
`l.nop 8'
1056
     Instruction tracing is turned on.
1057
 
1058
`l.nop 9'
1059
     Instruction tracing is turned off.
1060
 
1061
 
1062

1063 19 jeremybenn
File: or1ksim.info,  Node: Configuration,  Next: Interactive Command Line,  Prev: Usage,  Up: Top
1064
 
1065
3 Configuration
1066
***************
1067
 
1068 82 jeremybenn
Or1ksim is configured through a configuration file.  This is specified
1069 19 jeremybenn
through the `-f' parameter to the Or1ksim command, or passed as a
1070 82 jeremybenn
string when initializing the Or1ksim library.  If no file is specified,
1071
the default `sim.cfg' is used.  The file is looked for first in the
1072 224 jeremybenn
current directory, then in the `$HOME/.or1ksim' directory of the user.
1073 19 jeremybenn
 
1074
* Menu:
1075
 
1076
* Configuration File Format::
1077
* Simulator Configuration::
1078
* Core OpenRISC Configuration::
1079
* Peripheral Configuration::
1080
 
1081

1082
File: or1ksim.info,  Node: Configuration File Format,  Next: Simulator Configuration,  Up: Configuration
1083
 
1084
3.1 Configuration File Format
1085
=============================
1086
 
1087 346 jeremybenn
The configuration file is a plain text file.  A reference example,
1088
`sim.cfg', is included in the top level directory of the distribution.
1089 19 jeremybenn
 
1090
* Menu:
1091
 
1092
* Configuration File Preprocessing::
1093
* Configuration File Syntax::
1094
 
1095

1096
File: or1ksim.info,  Node: Configuration File Preprocessing,  Next: Configuration File Syntax,  Up: Configuration File Format
1097
 
1098
3.1.1 Configuration File Preprocessing
1099
--------------------------------------
1100
 
1101 82 jeremybenn
The configuration file may include C style comments (i.e.  delimited by
1102 19 jeremybenn
`/*' and `*/').
1103
 
1104

1105
File: or1ksim.info,  Node: Configuration File Syntax,  Prev: Configuration File Preprocessing,  Up: Configuration File Format
1106
 
1107
3.1.2 Configuration File Syntax
1108
-------------------------------
1109
 
1110
The configuration file is divided into a series of sections, with the
1111
general form:
1112
 
1113
     section SECTION_NAME
1114
 
1115
       ...
1116
 
1117
     end
1118
 
1119
Sections may also have sub-sections within them (currently only the
1120
ATA/ATAPI disc interface uses this).
1121
 
1122
Within a section, or sub-section are a series of parameter assignments,
1123
one per line, withe the general form
1124
 
1125
       PARAMETER = VALUE
1126
 
1127
Depending on the parameter, the value may be a named value (an
1128
enumeration), an integer (specified in any format acceptable in C) or a
1129 82 jeremybenn
string in doubple quotes.  For flag parameters, the value 1 is used to
1130
mean "true" or "on" and the value "0" to mean "false" or "off".  An
1131 19 jeremybenn
example from a memory section shows each of these
1132
 
1133
     section memory
1134
       type    = random
1135
       pattern = 0x00
1136
       name    = "FLASH"
1137
       ...
1138
     end
1139
 
1140
Many parameters are optional and take reasonable default values if not
1141 82 jeremybenn
specified.  However there are some parameters (for example the `ce'
1142 19 jeremybenn
parameter in `section memory') _must_ be specified.
1143
 
1144
Subsections are introduced by a keyword, with a parameter value (no `='
1145 82 jeremybenn
sign), and end with the same keyword prefixed by `end'.  Thus the
1146 19 jeremybenn
ATA/ATAPI inteface (`section ata') has a `device' subsection, thus:
1147
 
1148
     section ata
1149
       ...
1150
       device 0
1151
         type    = 1
1152
         file = "FILENAME"
1153
         ...
1154
       enddevice
1155
       ...
1156
     end
1157
 
1158
Some sections (for example `section sim') should appear only once.
1159
Others (for example `section memory' may appear multiple times.
1160
 
1161
Sections may be omitted, _unless they contain parameters which are
1162 82 jeremybenn
non-optional_.  If the section describes a part of the simulator which
1163 19 jeremybenn
is optional (for example whether it has a UART), then that
1164 82 jeremybenn
functionality will not be provided.  If the section describes a part of
1165 19 jeremybenn
the simulator which is not optional (for example the CPU), then all the
1166
parameters of that section will take their default values.
1167
 
1168
All optional parts of the functionality are always described by
1169
sections including a `enabled' parameter, which can be set to 0 to
1170
ensure that functionality is explicitly omitted.
1171
 
1172
Even if a section is disabled, all its parameters will be read and
1173 82 jeremybenn
stored.  This is helpful if the section is subsequently enabled from
1174
the Or1ksim command line (*note Interactive Command Line: Interactive
1175 19 jeremybenn
Command Line.).
1176
 
1177
     Tip: It generally clearer to have sections describing _all_
1178
     components, with omitted functionality explicitly indicated by
1179
     setting the `enabled' parameter to 0
1180
 
1181
The following sections describe the various configuration sections and
1182
the parameters which may be set in each.
1183
 
1184

1185
File: or1ksim.info,  Node: Simulator Configuration,  Next: Core OpenRISC Configuration,  Prev: Configuration File Format,  Up: Configuration
1186
 
1187
3.2 Simulator Configuration
1188
===========================
1189
 
1190
* Menu:
1191
 
1192
* Simulator Behavior::
1193
* Verification API Configuration::
1194
* CUC Configuration::
1195
 
1196

1197
File: or1ksim.info,  Node: Simulator Behavior,  Next: Verification API Configuration,  Up: Simulator Configuration
1198
 
1199
3.2.1 Simulator Behavior
1200
------------------------
1201
 
1202 82 jeremybenn
Simulator behavior is described in `section sim'.  This section should
1203
appear only once.  The following parameters may be specified.
1204 19 jeremybenn
 
1205
`verbose = 0|1'
1206 82 jeremybenn
     If 1 (true), print extra messages.  Default 0.
1207 19 jeremybenn
 
1208
`debug = 0-9'
1209 82 jeremybenn
 
1210
     higher the value the greater the number of messages.  Default 0.
1211
     Negative values will be treated as 0 (with a warning).  Values
1212
     that are too large will be treated as 9 (with a warning).
1213 19 jeremybenn
 
1214
`profile = 0|1'
1215
     If 1 (true) generate a profiling file using the file specified in
1216 82 jeremybenn
     the `prof_file' parameter or otherwise `sim.profile'.  Default 0.
1217 19 jeremybenn
 
1218
`prof_file = ``FILENAME'''
1219 82 jeremybenn
     Specifies the file to be used with the `profile' parameter.
1220
     Default `sim.profile'.  For backwards compatibility, the
1221
     alternative name `prof_fn' is supported for this parameter, but
1222 346 jeremybenn
     deprecated.  Default `sim.profile'.
1223 19 jeremybenn
 
1224
`mprofile = 0|1'
1225
     If 1 (true) generate a memory profiling file using the file
1226
     specified in the `mprof_file' parameter or otherwise
1227 82 jeremybenn
     `sim.mprofile'.  Default 0.
1228 19 jeremybenn
 
1229 346 jeremybenn
`mprof_file = ``FILENAME'''
1230 19 jeremybenn
     Specifies the file to be used with the `mprofile' parameter.
1231 82 jeremybenn
     Default `sim.mprofile'.  For backwards compatibility, the
1232 19 jeremybenn
     alternative name `mprof_fn' is supported for this parameter, but
1233 346 jeremybenn
     deprecated.  Default `sim.mprofile'.
1234 19 jeremybenn
 
1235
`history = 0|1'
1236 82 jeremybenn
     If 1 (true) track execution flow.  Default 0.
1237 19 jeremybenn
 
1238
          Note: Setting this parameter seriously degrades performance.
1239
 
1240
          Note: If this execution flow tracking is enabled, then
1241
          `dependstats' must be enabled in the CPU configuration
1242
          section (*note CPU Configuration: CPU Configuration.).
1243
 
1244
`exe_log = 0|1'
1245 82 jeremybenn
     If 1 (true), generate an execution log.  Log is written to the
1246
     file specified in parameter `exe_log_file'.  Default 0.
1247 19 jeremybenn
 
1248
          Note: Setting this parameter seriously degrades performance.
1249
 
1250
`exe_log_type = default|hardware|simple|software'
1251
     Type of execution log to produce.
1252
 
1253
    `default'
1254 82 jeremybenn
          Produce default output for the execution log.  In the current
1255 19 jeremybenn
          implementation this is the equivalent of `hardware'.
1256
 
1257
    `hardware'
1258
          After each instruction execution, log the number of
1259
          instructions executed so far, the next instruction to execute
1260
          (in hex), the general purpose registers (GPRs), status
1261
          register, exception program counter, exception, effective
1262
          address register and exception status register.
1263
 
1264
    `simple'
1265
          After each instruction execution, log the number of
1266
          instructions executed so far and the next instruction to
1267
          execute, symbolically disassembled.
1268
 
1269
    `software'
1270
          After each instruction execution, log the number of
1271
          instructions executed so far and the next instruction to
1272 82 jeremybenn
          execute, symbolically disassembled.  Also show the value of
1273 19 jeremybenn
          each operand to the instruction.
1274
 
1275
 
1276 82 jeremybenn
     Default value `hardware'.  Any unrecognized keyword (case
1277 19 jeremybenn
     insensitive) will be treated as the default with a warning.
1278
 
1279
          Note: Execution logs can be _very_ big.
1280
 
1281
`exe_log_start = VALUE'
1282 82 jeremybenn
     Address of the first instruction to start logging.  Default 0.
1283 19 jeremybenn
 
1284
`exe_log_end = VALUE'
1285 82 jeremybenn
     Address of the last instruction to log.  Default no limit (i.e
1286
     once started logging will continue until the simulator exits).
1287 19 jeremybenn
 
1288
`exe_log_marker = VALUE'
1289
     Specifies the number of instructions between printing horizontal
1290 82 jeremybenn
     markers.  Default is to produce no markers.
1291 19 jeremybenn
 
1292
`exe_log_file = FILENAME'
1293
     Filename for the execution log filename if `exe_log' is enabled.
1294 82 jeremybenn
     Default `executed.log'.  For backwards compatibility, the
1295 19 jeremybenn
     alternative name `exe_log_fn' is supported for this parameter, but
1296
     deprecated.
1297
 
1298 202 julius
`exe_bin_insn_log = 0|1'
1299 346 jeremybenn
     Enable logging of executed instructions to a file in binary format.
1300
     This is helpful for off-line dynamic execution analysis.
1301 202 julius
 
1302 346 jeremybenn
          Note: Execution logs can be _very_ big.  For example, while
1303 220 jeremybenn
          booting the Linux kernel, version 2.6.34, a log file 1.2GB in
1304
          size was generated.
1305 202 julius
 
1306
`exe_bin_insn_log_file = FILENAME'
1307
     Filename for the binary execution log filename if
1308
     `exe_bin_insn_log' is enabled.  Default `exe-insn.bin'.
1309
 
1310 19 jeremybenn
`clkcycle = VALUE[ps|ns|us|ms]'
1311 82 jeremybenn
     Specify the time taken by one clock cycle.  If no units are
1312
     specified, `ps' is assumed.  Default 4000ps (250MHz).
1313 19 jeremybenn
 
1314
 
1315

1316
File: or1ksim.info,  Node: Verification API Configuration,  Next: CUC Configuration,  Prev: Simulator Behavior,  Up: Simulator Configuration
1317
 
1318
3.2.2 Verification API (VAPI) Configuration
1319
-------------------------------------------
1320
 
1321
The Verification API (VAPI) provides a TCP/IP interface to allow
1322 82 jeremybenn
components of the simulation to be controlled externally.  *Note
1323 19 jeremybenn
Verification API: Verification API, for more details.
1324
 
1325 82 jeremybenn
Verification API configuration is described in `section vapi'.  This
1326
section may appear at most once.  The following parameters may be
1327 19 jeremybenn
specified.
1328
 
1329
`enabled = 0|1'
1330
     If 1 (true), verification API is enabled and its server started.
1331
     If 0 (the default), it is disabled.
1332
 
1333
`server_port = VALUE'
1334
     When VAPI is enabled, communication will be via TCP/IP on the port
1335 82 jeremybenn
     specified by VALUE.  The value must lie in the range 1 to 65535.
1336 19 jeremybenn
     The default value is 50000.
1337
 
1338 82 jeremybenn
          Tip: There is no registered port for Or1ksim VAPI.  Good
1339 19 jeremybenn
          practice suggests users should adopt port values in the
1340 82 jeremybenn
          "Dynamic" or "Private" port range, i.e.  49152-65535.
1341 19 jeremybenn
 
1342
`log_enabled = 0|1'
1343
     If 1 (true), all VAPI requests and sent commands will be logged.
1344 82 jeremybenn
     If 0 (the default), logging is diabled.  Logs are written to the
1345 19 jeremybenn
     file specified by the `vapi_log_file' field (see below).
1346
 
1347
          Caution: This can generate a substantial amount of file I/O
1348
          and seriously degrade simulator performance.
1349
 
1350
`hide_device_id = 0|1'
1351 82 jeremybenn
     If 1 (true) don't log the device ID.  If 0 (the default), log the
1352
     device ID.  This feature (when set to 1) is provided for backwards
1353 19 jeremybenn
     compatibility with an old version of VAPI.
1354
 
1355
`vapi_log_file = "FILENAME"'
1356
     Use `filename' as the file for logged data is logging is enabled
1357 82 jeremybenn
     (see `log_enabled' above).  The default is `"vapi.log"'.  For
1358 19 jeremybenn
     backwards compatibility, the alternative name `vapi_log_fn' is
1359
     supported for this parameter, but deprecated.
1360
 
1361
 
1362

1363
File: or1ksim.info,  Node: CUC Configuration,  Prev: Verification API Configuration,  Up: Simulator Configuration
1364
 
1365
3.2.3 Custom Unit Compiler (CUC) Configuration
1366
----------------------------------------------
1367
 
1368
The Custom Unit Compiler (CUC) was a project by Marko Mlinar to generate
1369 82 jeremybenn
Verilog from ANSI C functions.  The project seems to not have progressed
1370
beyond the initial prototype phase.  The configuration parameters are
1371 19 jeremybenn
described here for the record.
1372
 
1373 82 jeremybenn
CUC configuration is described in `section cuc'.  This section may
1374
appear at most once.  The following parameters may be specified.
1375 19 jeremybenn
 
1376
`memory_order = none|weak|strong|exact'
1377
     This parameter specifies the memory ordering required:
1378
 
1379
    `memory_order=none'
1380
          Different memory ordering, even if there are dependencies.
1381
          Bursts can be made, width can change.
1382
 
1383 346 jeremybenn
    `memory_order=weak'
1384 82 jeremybenn
          Different memory ordering, even if there are dependencies.  If
1385 19 jeremybenn
          dependencies cannot occur, then bursts can be made, width can
1386
          change.
1387
 
1388 346 jeremybenn
    `memory_order=strong'
1389 82 jeremybenn
          Same memory ordering.  Bursts can be made, width can change.
1390 19 jeremybenn
 
1391 346 jeremybenn
    `memory_order=exact'
1392 19 jeremybenn
          Exactly the same memory ordering and widths.
1393
 
1394
 
1395 82 jeremybenn
     The default value is `memory_order=exact'.  Invalid memory
1396 19 jeremybenn
     orderings are ignored with a warning.
1397
 
1398
`calling_convention = 0|1'
1399 82 jeremybenn
     If 1 (true), programs follow OpenRISC calling conventions.  If 0
1400 19 jeremybenn
     (the default), they may use other convenitions.
1401
 
1402
`enable_bursts = 0 | 1'
1403 82 jeremybenn
     If 1 (true), bursts are detected.  If 0 (the default), bursts are
1404 19 jeremybenn
     not detected.
1405
 
1406
`no_multicycle = 0 | 1'
1407 82 jeremybenn
     If 1 (true), no multicycle logic paths will be generated.  If 0
1408
     (the default), multicycle logic paths will be generated.
1409 19 jeremybenn
 
1410
`timings_file = "FILENAME"'
1411 82 jeremybenn
     FILENAME specifies a file containing timing information.  The
1412
     default value is `"virtex.tim"'.  For backwards compatibility, the
1413 19 jeremybenn
     alternative name `timings_fn' is supported for this parameter, but
1414
     deprecated.
1415
 
1416
 
1417

1418
File: or1ksim.info,  Node: Core OpenRISC Configuration,  Next: Peripheral Configuration,  Prev: Simulator Configuration,  Up: Configuration
1419
 
1420
3.3 Configuring the OpenRISC Architectural Components
1421
=====================================================
1422
 
1423
* Menu:
1424
 
1425
* CPU Configuration::
1426
* Memory Configuration::
1427
* Memory Management Configuration::
1428
* Cache Configuration::
1429
* Interrupt Configuration::
1430
* Power Management Configuration::
1431
* Branch Prediction Configuration::
1432
* Debug Interface Configuration::
1433
 
1434

1435
File: or1ksim.info,  Node: CPU Configuration,  Next: Memory Configuration,  Up: Core OpenRISC Configuration
1436
 
1437
3.3.1 CPU Configuration
1438
-----------------------
1439
 
1440 82 jeremybenn
CPU configuration is described in `section cpu'.  This section should
1441
appear only once.  At present Or1ksim does not model multi-CPU systems.
1442 19 jeremybenn
The following parameters may be specified.
1443
 
1444
`ver = VALUE'
1445
 
1446
`cfg = VALUE'
1447
 
1448
`rev = VALUE'
1449
     The values are used to form the corresponding fields in the `VR'
1450 82 jeremybenn
     Special Purpose Register (SPR 0).  Default values 0.  A warning is
1451 19 jeremybenn
     given and the value truncated if it is too large (8 bits for `ver'
1452
     and `cfg', 6 bits for `rev').
1453
 
1454
`upr = VALUE'
1455
     Used as the value of the Unit Present Register (UPR) Special
1456 82 jeremybenn
     Purpose Register (SPR 1) to VALUE.  Default value is 0x0000075f,
1457 19 jeremybenn
     i.e.
1458
        * UPR present (0x00000001)
1459
 
1460
        * Data cache present (0x00000002)
1461
 
1462
        * Instruction cache present (0x00000004)
1463
 
1464
        * Data MMY present (0x00000008)
1465
 
1466
        * Instruction MMU present (0x00000010)
1467
 
1468
        * Debug unit present (0x00000040)
1469
 
1470
        * Power management unit present (0x00000100)
1471
 
1472
        * Programmable interrupt controller present (0x00000200)
1473
 
1474
        * Tick timer present (0x00000400)
1475
 
1476
     However, with the exection of the UPR present (0x00000001) and tick
1477
     timer present, the various fields will be modified with the values
1478
     specified in their corresponding configuration sections.
1479
 
1480
`cfgr = VALUE'
1481
     Sets the CPU configuration register (Special Purpose Register 2) to
1482 82 jeremybenn
     VALUE.  Default value is 0x00000020, i.e.  support for the ORBIS32
1483
     instruction set.  Attempts to set any other value are accepted, but
1484 19 jeremybenn
     issue a warning that there is no support for the instruction set.
1485
 
1486
`sr = VALUE'
1487
     Sets the supervision register Special Purpose Register (SPR 0x11)
1488 82 jeremybenn
     to VALUE.  Default value is 0x00008001, i.e.  start in supervision
1489 19 jeremybenn
     mode (0x00000001) and set the "Fixed One" bit (0x00008000).
1490
 
1491 98 jeremybenn
          Note: This is particularly useful when an image is held in
1492
          Flash at high memory (0xf0000000).  The EPH  bit can be set,
1493
          so that interrupt vectors are basedf at 0xf0000000, rather
1494
          than 0x0.
1495
 
1496 19 jeremybenn
`superscalar = 0|1'
1497 82 jeremybenn
     If 1, the processor operates in superscalar mode.  Default value is
1498 19 jeremybenn
     0.
1499
 
1500
     In the current simulator, the only functional effect of superscalar
1501
     mode is to affect the calculation of the number of cycles taken to
1502
     execute an instruction.
1503
 
1504
          Caution: The code for this does not appear to be complete or
1505
          well tested, so users are advised not to use this option.
1506
 
1507
`hazards = 0|1'
1508 82 jeremybenn
     If 1, data hazards are tracked in a superscalar CPU.  Default
1509
     value is 0.
1510 19 jeremybenn
 
1511
     In the current simulator, the only functional effect is to cause
1512
     logging of hazard waiting information if the CPU is superscalar.
1513
     However nowhere in the simulator is this data actually computed,
1514
     so the net result is probably to have no effect.
1515
 
1516
     if harzards are tracked, current hazards can be displayed using the
1517
     simulator's `r' command.
1518
 
1519
          Caution: The code for this does not appear to be complete or
1520
          well tested, so users are advised not to use this option.
1521
 
1522
`dependstats = 0|1'
1523 82 jeremybenn
     If 1, inter-instruction dependencies are calculated.  Default
1524
     value 0.
1525 19 jeremybenn
 
1526
     If these values are calculated, the depencies can be displayed
1527
     using the simulator's `stat' command.
1528
 
1529
          Note: This field must be enabled, if execution execution flow
1530
          tracking (field `history') has been requested in the simulator
1531
          configuration section (*note Simulator Behavior: Simulator
1532
          Behavior.).
1533
 
1534
`sbuf_len = VALUE'
1535
     The length of the store buffer is set to VALUE, which must be no
1536 82 jeremybenn
     greater than 256.  Larger values will be truncated to 256 with a
1537
     warning.  Negative values will be treated as 0 with a warning.
1538
     Use 0 to disable the store buffer.
1539 19 jeremybenn
 
1540
     When the store buffer is active, stores are accumulated and
1541
     committed when I/O is idle.
1542
 
1543 100 julius
`hardfloat = 0|1'
1544 346 jeremybenn
     If 1, hardfloat instructions are enabled.  Default value 0.
1545 19 jeremybenn
 
1546 104 jeremybenn
 
1547 19 jeremybenn

1548
File: or1ksim.info,  Node: Memory Configuration,  Next: Memory Management Configuration,  Prev: CPU Configuration,  Up: Core OpenRISC Configuration
1549
 
1550
3.3.2 Memory Configuration
1551
--------------------------
1552
 
1553 82 jeremybenn
Memory configuration is described in `section memory'.  This section
1554 98 jeremybenn
may appear multiple times, specifying multiple blocks of memory.
1555 19 jeremybenn
 
1556 98 jeremybenn
     Caution: The user may choose whether or not to enable a memory
1557 385 jeremybenn
     controller.  If a memory controller is enabled, then appropriate
1558
     initalization code must be provided.  The section describing
1559
     memory controller configuration describes the steps necessary for
1560
     using smaller or larger memory sections (*note Memory Controller
1561
     Configuration: Memory Controller Configuration.).
1562 98 jeremybenn
 
1563 385 jeremybenn
     The "uClibc" startup code initalizes a memory controller, assumed
1564
     to be mapped at 0x93000000.  If a memory controller is _not_
1565
     enabled, then the standard C library code will generate memory
1566
     access errors.  The solution is to declare an additional writable
1567
     memory block, mimicing the memory controller's register bank as
1568
     follows.
1569 98 jeremybenn
 
1570
          section memory
1571
            pattern = 0x00
1572
            type = unknown
1573
            name = "MC shadow"
1574
            baseaddr = 0x93000000
1575
            size     = 0x00000080
1576
            delayr = 2
1577
            delayw = 4
1578
          end
1579
 
1580
 
1581
The following parameters may be specified.
1582
 
1583 418 julius
`type=random|pattern|unknown|zero|exitnops'
1584 82 jeremybenn
     Specifies the values to which memory should be initialized.  The
1585 19 jeremybenn
     default value is `unknown'.
1586
 
1587
    `random'
1588 82 jeremybenn
          Set the memory values to be a random value.  A seed for the
1589 19 jeremybenn
          random generator may be set using the `random_seed' field in
1590
          this section (see below), thus ensuring the same "random"
1591
          values are used each time.
1592
 
1593
    `pattern'
1594
          Set the memory values to be a pattern value, which is set
1595
          using the `pattern' field in this section (see below).
1596
 
1597
    `unknown'
1598 82 jeremybenn
          The memory values are not initialized (i.e.  left "unknown").
1599 240 julius
          This option will yield faster initialization of the
1600 346 jeremybenn
          simulator.  This is the default.
1601 19 jeremybenn
 
1602
    `zero'
1603 82 jeremybenn
          Set the memory values to be 0.  This is the equivalent of
1604 19 jeremybenn
          `type=pattern' and a `pattern' value of 0, and implemented as
1605
          such.
1606
 
1607 420 jeremybenn
               Note: As a consequence, if the `pattern' field is
1608
               _subsequently_ specified in this section, the value in
1609
               that field will be used instead of zero to initialize
1610
               the memory.
1611
 
1612 418 julius
    `exitnops'
1613
          Set the memory values to be an instruction used to signal end
1614
          of simulation. This is useful for causing immediate end of
1615
          simulation when PC corruption occurs.
1616
 
1617 19 jeremybenn
 
1618
`random_seed = VALUE'
1619 82 jeremybenn
     Set the seed for the random number generator to VALUE.  This only
1620 19 jeremybenn
     has any effect for memory type `random'.
1621
 
1622
     The default value is -1, which means the seed will be set from a
1623
     call to the `time' function, thus ensuring different random values
1624 82 jeremybenn
     are used on each run.  The simulator prints out the seed used in
1625 19 jeremybenn
     this case, allowing repeat runs to regenerate the same random
1626
     values used in any particular run.
1627
 
1628
`pattern = VALUE'
1629 82 jeremybenn
     Set the pattern to be used when initializing memory to VALUE.  The
1630
     default value is 0.  This only has any effect for memory type
1631
     `pattern'.  The least significant 8 bits of this value is used to
1632
     initialize each byte.  More than 8 bits can be specified, but will
1633 19 jeremybenn
     ignored with a warning.
1634
 
1635
          Tip: The default value, is equivalent to setting the memory
1636 82 jeremybenn
          `type' to be `zero'.  If that is what is intended, then using
1637 19 jeremybenn
          `type=zero' explicitly is better than using `type=pattern'
1638
          and not specifying a value for `pattern'.
1639
 
1640
`baseaddr = VALUE'
1641 82 jeremybenn
     Set the base address of the memory to VALUE.  It should be aligned
1642 19 jeremybenn
     to a multiple of the memory size rounded up to the nearest 2^n.
1643
     The default value is 0.
1644
 
1645
`size = VALUE'
1646 82 jeremybenn
     Set the size of the memory block to be VALUE bytes.  This should
1647
     be a multiple of 4 (i.e.  word aligned).  The default value is
1648
     1024.
1649 19 jeremybenn
 
1650
          Note: When allocating memory, the simulator will allocate the
1651
          nearest 2^n bytes greater than or equal to VALUE, and will not
1652
          notice memory misses in any part of the memory between VALUE
1653
          and the amount allocated.
1654
 
1655
          As a consequence users are strongly recommended to specify
1656 82 jeremybenn
          memory sizes that are an exact power of 2.  If some other
1657 19 jeremybenn
          amount of memory is required, it should be specified as
1658
          separate, contiguous blocks, each of which is a power of 2 in
1659
          size.
1660
 
1661
`name = "TEXT"'
1662 82 jeremybenn
     Name the block.  Typically these describe the type of memory being
1663
     modeled (thus `"SRAM"' or `"Flash"'.  The default is
1664 19 jeremybenn
     `"anonymous memory block"'.
1665
 
1666
          Note: It is not clear that this information is currently ever
1667 82 jeremybenn
          used in normal operation of the simulator.  Even the `info'
1668 19 jeremybenn
          command of the simulator ignores it.
1669
 
1670
`ce = VALUE'
1671 82 jeremybenn
     Set the chip enable index of the memory instance.  Each memory
1672 19 jeremybenn
     instance should have a unique chip enable index, which should be
1673 82 jeremybenn
     greater than or equal to zero.  This is used by the memory
1674 19 jeremybenn
     controller when identifying different memory instances.
1675
 
1676 346 jeremybenn
     There is no requirement to set `ce' if a memory controller is not
1677
     enabled.  The default value is -1 (invalid).
1678 19 jeremybenn
 
1679
`mc = VALUE'
1680 82 jeremybenn
     Specifies the memory controller this memory is connected to.  It
1681 19 jeremybenn
     should correspond to the `index' field specified in a `section mc'
1682
     for a memory controller (*note Memory Controller Configuration:
1683
     Memory Controller Configuration.).
1684
 
1685 346 jeremybenn
     There is no requirement to set `mc' if a memory controller is not
1686
     enabled.  Default value is 0, which is also the default value of a
1687 98 jeremybenn
     memory controller `index' field.  This is suitable therefore for
1688
     designs with just one memory controller.
1689 19 jeremybenn
 
1690
`delayr = VALUE'
1691 82 jeremybenn
     The number of cycles required for a read access.  Set to -1 if the
1692
     memory does not support reading.  Default value 1.  The simulator
1693 19 jeremybenn
     will add this number of cycles to the total instruction cycle
1694
     count when reading from main memory.
1695
 
1696
`delayw = VALUE'
1697 82 jeremybenn
     The number of cycles required for a write access.  Set to -1 if the
1698
     memory does not support writing.  Default value 1.  The simulator
1699 19 jeremybenn
     will add this number of cycles to the total instruction cycle
1700
     count when writing to main memory.
1701
 
1702
`log = "FILE"'
1703
     If specified, `file' names a file for all memory accesses to be
1704 82 jeremybenn
     logged.  If not specified, the default value, NULL is used, meaning
1705 19 jeremybenn
     that the memory is not logged.
1706
 
1707
 
1708

1709
File: or1ksim.info,  Node: Memory Management Configuration,  Next: Cache Configuration,  Prev: Memory Configuration,  Up: Core OpenRISC Configuration
1710
 
1711
3.3.3 Memory Management Configuration
1712
-------------------------------------
1713
 
1714
Memory Management Unit (MMU) configuration is described in `section
1715
dmmu' (for the data MMU) and `section immu' (for the instruction MMU).
1716 82 jeremybenn
Each section should appear at most once.  The following parameters may
1717 19 jeremybenn
be specified.
1718
 
1719
`enabled = 0|1'
1720
     If 1 (true), the data or instruction (as appropriate) MMU is
1721 82 jeremybenn
     enabled.  If 0 (the default), it is disabled.
1722 19 jeremybenn
 
1723
`nsets = VALUE'
1724
     Sets the number of data or instruction (as appropriate) TLB sets to
1725 82 jeremybenn
     VALUE, which must be a power of two, not exceeding 128.  Values
1726
     which do not fit these criteria are ignored with a warning.  The
1727 19 jeremybenn
     default value is 1.
1728
 
1729
`nways = VALUE'
1730
     Sets the number of data or instruction (as appropriate) TLB ways to
1731 82 jeremybenn
     VALUE.  The value must be in the range 1 to 4.  Values outside
1732
     this range are ignored with a warning.  The default value is 1.
1733 19 jeremybenn
 
1734
`pagesize = VALUE'
1735
     The data or instruction (as appropriate) MMU page size is set to
1736 82 jeremybenn
     VALUE, which must be a power of 2.  Values which are not a power
1737
     of 2 are ignored with a warning.  The default is 8192 (0x2000).
1738 19 jeremybenn
 
1739
`entrysize = VALUE'
1740
     The data or instruction (as appropriate) MMU entry size is set to
1741 82 jeremybenn
     VALUE, which must be a power of 2.  Values which are not a power
1742
     of 2 are ignored with a warning.  The default value is 1.
1743 19 jeremybenn
 
1744
          Note: Or1ksim does not appear to use the `entrysize' parameter
1745 82 jeremybenn
          in its simulation of the MMUs.  Thus setting this value does
1746 19 jeremybenn
          not seem to matter.
1747
 
1748
`ustates = VALUE'
1749
     The number of instruction usage states for the data or instruction
1750
     (as appropriate) MMU is set to VALUE, which must be 2, 3 or 4.
1751 82 jeremybenn
     Values outside this range are ignored with a warning.  The default
1752 19 jeremybenn
     value is 2.
1753
 
1754
          Note: Or1ksim does not appear to use the `ustates' parameter
1755 82 jeremybenn
          in its simulation of the MMUs.  Thus setting this value does
1756 19 jeremybenn
          not seem to matter.
1757
 
1758
`hitdelay = VALUE'
1759
     Set the number of cycles a data or instruction (as appropriate) MMU
1760 82 jeremybenn
     hit costs.  Default value 1.
1761 19 jeremybenn
 
1762
`missdelay = VALUE'
1763
     Set the number of cycles a data or instruction (as appropriate) MMU
1764 82 jeremybenn
     miss costs.  Default value 1.
1765 19 jeremybenn
 
1766
 
1767

1768
File: or1ksim.info,  Node: Cache Configuration,  Next: Interrupt Configuration,  Prev: Memory Management Configuration,  Up: Core OpenRISC Configuration
1769
 
1770
3.3.4 Cache Configuration
1771
-------------------------
1772
 
1773
Cache configuration is described in `section dc' (for the data cache)
1774 82 jeremybenn
and `seciton ic' (for the instruction cache).  Each section should
1775
appear at most once.  The following parameters may be specified.
1776 19 jeremybenn
 
1777
`enabled = 0|1'
1778
     If 1 (true), the data or instruction (as appropriate) cache is
1779 82 jeremybenn
     enabled.  If 0 (the default), it is disabled.
1780 19 jeremybenn
 
1781
`nsets = VALUE'
1782
     Sets the number of data or instruction (as appropriate) cache sets
1783
     to VALUE, which must be a power of two, not exceeding
1784
     `MAX_DC_SETS' (for the data cache) or `MAX_IC_SETS' (for the
1785 82 jeremybenn
     instruction cache).  At the time of writing, these constants are
1786
     both defined in the code to be 1024).  The default value is 1.
1787 19 jeremybenn
 
1788
`nways = VALUE'
1789
     Sets the number of data or instruction (as appropriate) cache ways
1790
     to VALUE, which must be a power of two, not exceeding
1791
     `MAX_DC_WAYS' (for the data cache) or `MAX_IC_WAYS' (for the
1792 82 jeremybenn
     instruction cache).  At the time of writing, these constants are
1793
     both defined in the code to be 32).  The default value is 1.
1794 19 jeremybenn
 
1795
`blocksize = VALUE'
1796
     The data or instruction (as appropriate) cache block size is set to
1797 82 jeremybenn
     VALUE bytes, which must be either 16 or 32.  The default is 16.
1798 19 jeremybenn
 
1799
`ustates = VALUE'
1800
     The number of instruction usage states for the data or instruction
1801
     (as appropriate) cache is set to VALUE, which must be 2, 3 or 4.
1802
     The default value is 2.
1803
 
1804
`hitdelay = VALUE'
1805 82 jeremybenn
     _Instruction cache only_.  Set the number of cycles an instruction
1806
     cache hit costs.  Default value 1.
1807 19 jeremybenn
 
1808
`missdelay = VALUE'
1809 82 jeremybenn
     _Instruction cache only_.  Set the number of cycles an instruction
1810
     cache miss costs.  Default value 1.
1811 19 jeremybenn
 
1812
`load_hitdelay = VALUE'
1813 82 jeremybenn
     _Data cache only_.  Set the number of cycles a data load cache hit
1814
     costs.  Default value 2.
1815 19 jeremybenn
 
1816
`load_missdelay = VALUE'
1817 82 jeremybenn
     _Data cache only_.  Set the number of cycles a data load cache
1818
     miss costs.  Default value 2.
1819 19 jeremybenn
 
1820
`store_hitdelay = VALUE'
1821 82 jeremybenn
     _Data cache only_.  Set the number of cycles a data store cache hit
1822
     costs.  Default value 0.
1823 19 jeremybenn
 
1824
`store_missdelay = VALUE'
1825 82 jeremybenn
     _Data cache only_.  Set the number of cycles a data store cache
1826
     miss costs.  Default value 0.
1827 19 jeremybenn
 
1828
 
1829

1830
File: or1ksim.info,  Node: Interrupt Configuration,  Next: Power Management Configuration,  Prev: Cache Configuration,  Up: Core OpenRISC Configuration
1831
 
1832
3.3.5 Interrupt Configuration
1833
-----------------------------
1834
 
1835
Programmable Interrupt Controller (PIC) configuration is described in
1836 82 jeremybenn
`section pic'.  This section may appear at most once--Or1ksim has no
1837
mechanism for handling multiple interrupt controllers.  The following
1838 19 jeremybenn
parameters may be specified.
1839
 
1840
`enabled = 0|1'
1841 82 jeremybenn
     If 1 (true), the programmable interrupt controller is enabled.  If
1842
 
1843 19 jeremybenn
 
1844
`edge_trigger = 0|1'
1845
     If 1 (true, the default), the programmable interrupt controller is
1846 82 jeremybenn
     edge triggered.  If 0 (false), it is level triggered.
1847 19 jeremybenn
 
1848 432 jeremybenn
     The library interface (*note Simulator Library: Simulator Library.)
1849
     provides different functions for setting the different types of
1850
     interrupt, and a function to clear level sensitive interrupts. Edge
1851
     sensitive interrupts must be cleared by clearing the corresponding
1852
     bit in the PICSR SPR.
1853 19 jeremybenn
 
1854 432 jeremybenn
     Internal functions to set and clear interrupts are also provided
1855
     for peripherals implemented within Or1ksim. *Note Interrupts
1856
     Internal: Interrupts Internal for more details.
1857 430 julius
 
1858 432 jeremybenn
`use_nmi = 0|1'
1859
     If 1 (true, the default), interrupt lines 0 and 1 are
1860
     non-maskable. In other words the least significant 2 bits of the
1861
     PICMR SPR are hard-wired to 1.  If 0 (false), all interrupt lines
1862
     are treated as equivalent.
1863 430 julius
 
1864 432 jeremybenn
          Note: These are not non-maskable in the true sense that they
1865
          will pre-empt other interrupts.  Rather they can never be
1866
          masked out using the PICMR register. It is up the interrupt
1867
          exception handler to give these interrupt lines priority, and
1868
          indeed to decide on the priority order in general.
1869 430 julius
 
1870 432 jeremybenn
 
1871 19 jeremybenn

1872
File: or1ksim.info,  Node: Power Management Configuration,  Next: Branch Prediction Configuration,  Prev: Interrupt Configuration,  Up: Core OpenRISC Configuration
1873
 
1874
3.3.6 Power Management Configuration
1875
------------------------------------
1876
 
1877 82 jeremybenn
Power management implementation is incomplete.  At present the effect
1878 19 jeremybenn
(which only happens when the power management unit is enabled) of
1879
setting the different bits in the power management Special Purpose
1880
Register (PMR, SPR 0x4000) is
1881
 
1882
`SDF (bit mask 0x0000000f)'
1883
     No effect - these bits are ignored
1884
 
1885
`DME (bit mask 0x00000010)'
1886
`SME (bit mask 0x00000020)'
1887
     Both these bits cause the processor to stop executing
1888 82 jeremybenn
     instructions.  However all other functions (debug interaction, CLI,
1889 19 jeremybenn
     VAPI etc) carry on as normal.
1890
 
1891
`DCGE (bit mask 0x00000004)'
1892
     No effect - this bit is ignored
1893
 
1894
`SUME (bit mask 0x00000008)'
1895
     Enabling this bit causes a message to be printed, advising that the
1896
     processor is suspending and the simulator exits.
1897
 
1898
 
1899
On reset all bits are cleared.
1900
 
1901 82 jeremybenn
Power management configuration is described in `section pm'.  This
1902
section may appear at most once.  The following parameter may be
1903 19 jeremybenn
specified.
1904
 
1905
`enabled = 0|1'
1906 82 jeremybenn
     If 1 (true), power management is enabled.  If 0 (the default), it
1907
     is disabled.
1908 19 jeremybenn
 
1909
 
1910

1911
File: or1ksim.info,  Node: Branch Prediction Configuration,  Next: Debug Interface Configuration,  Prev: Power Management Configuration,  Up: Core OpenRISC Configuration
1912
 
1913
3.3.7 Branch Prediction Configuration
1914
-------------------------------------
1915
 
1916
From examining the code base, it seems the branch prediction function
1917 82 jeremybenn
is not fully implemented.  At present the functionality seems
1918
restricted to collection of statistics.
1919 19 jeremybenn
 
1920 82 jeremybenn
Branch prediction configuration is described in `section bpb'.  This
1921
section may appear at most once.  The following parameters may be
1922 19 jeremybenn
specified.
1923
 
1924
`enabled = 0|1'
1925 82 jeremybenn
     If 1 (true), branch prediction is enabled.  If 0 (the default), it
1926 19 jeremybenn
     is disabled.
1927
 
1928
`btic = 0|1'
1929
     If 1 (true), the branch target instruction cache model is enabled.
1930
     If 0 (the default), it is disabled.
1931
 
1932
`sbp_bf_fwd = 0|1'
1933 82 jeremybenn
     If 1 (true), use forward prediction for the `l.bf' instruction.  If
1934 19 jeremybenn
 
1935
     instruction.
1936
 
1937
`sbp_bnf_fwd = 0|1'
1938 82 jeremybenn
     If 1 (true), use forward prediction for the `l.bnf' instruction.
1939
     If 0 (the default), do not use forward prediction for this
1940 19 jeremybenn
     instruction.
1941
 
1942
`hitdelay = VALUE'
1943 82 jeremybenn
     Set the number of cycles a branch prediction hit costs.  Default
1944 19 jeremybenn
     value 0.
1945
 
1946
`missdelay = VALUE'
1947 82 jeremybenn
     Set the number of cycles a branch prediction miss costs.  Default
1948 19 jeremybenn
     value 0.
1949
 
1950
 
1951

1952
File: or1ksim.info,  Node: Debug Interface Configuration,  Prev: Branch Prediction Configuration,  Up: Core OpenRISC Configuration
1953
 
1954
3.3.8 Debug Interface Configuration
1955
-----------------------------------
1956
 
1957
The debug unit and debug interface configuration is described in
1958 82 jeremybenn
`section debug'.  This section may appear at most once.  The following
1959 19 jeremybenn
parameters may be specified.
1960
 
1961
`enabled = 0|1'
1962 82 jeremybenn
     If 1 (true), the debug unit is enabled.  If 0 (the default), it is
1963 19 jeremybenn
     disabled.
1964
 
1965
          Note: This enables the functionality of the debug unit (its
1966 82 jeremybenn
          registers etc) within the mode.  It does not provide any
1967
          external interface to the debug unit.  For that, see
1968 235 jeremybenn
          `rsp_enabled' below.
1969 19 jeremybenn
 
1970
`rsp_enabled = 0|1'
1971
     If 1 (true), the GDB "Remote Serial Protocol" server is started,
1972
     provding an interface to an external GNU debugger, using the port
1973
     specified in the `rsp_port' field (see below), or the
1974 82 jeremybenn
     `or1ksim-rsp' TCP/IP service.  If 0 (the default), the server is
1975 19 jeremybenn
     not started, and no external interface is provided.
1976
 
1977
     For more detailed information on the interface to the GNU Debugger
1978
     see Embecosm Application Note 2, `Howto: Porting the GNU Debugger
1979
     Practical Experience with the OpenRISC 1000 Architecture', by
1980
     Jeremy Bennett, published by Embecosm Limited (`www.embecosm.com').
1981
 
1982
`rsp_port = VALUE'
1983
     VALUE specifies the port to be used for the GDB "Remote Serial
1984 82 jeremybenn
     Protocol" interface to the GNU Debugger (GDB).  Default value
1985
     51000.  If the value 0 is specified, Or1ksim will instead look for
1986 19 jeremybenn
     a TCP/IP service named `or1ksim-rsp'.
1987
 
1988
          Tip: There is no registered port for Or1ksim "Remote Serial
1989 82 jeremybenn
          Protocol" service `or1ksim-rsp'.  Good practice suggests
1990
          users should adopt port values in the "Dynamic" or "Private"
1991
          port range, i.e.  49152-65535.
1992 19 jeremybenn
 
1993
`vapi_id = VALUE'
1994
     VALUE specifies the value of the Verification API (VAPI) base
1995 82 jeremybenn
     address to be used with the debug unit.  *Note Verification API:
1996 19 jeremybenn
     Verification API, for more details.
1997
 
1998
     If this is specified and VALUE is non-zero, all OpenRISC Remote
1999
     JTAG protocol transactions will be logged to the VAPI log file, if
2000 82 jeremybenn
     enabled.  This is the only functionality associated with VAPI for
2001
     the debug unit.  No VAPI commands are sent, nor requests handled.
2002 19 jeremybenn
 
2003
 
2004

2005
File: or1ksim.info,  Node: Peripheral Configuration,  Prev: Core OpenRISC Configuration,  Up: Configuration
2006
 
2007
3.4 Configuring Memory Mapped Peripherals
2008
=========================================
2009
 
2010 82 jeremybenn
All peripheral components are optional.  If they are specified, then
2011 19 jeremybenn
(unlike other components) by default they are enabled.
2012
 
2013
* Menu:
2014
 
2015
* Memory Controller Configuration::
2016
* UART Configuration::
2017
* DMA Configuration::
2018
* Ethernet Configuration::
2019
* GPIO Configuration::
2020
* Display Interface Configuration::
2021
* Frame Buffer Configuration::
2022
* Keyboard Configuration::
2023
* Disc Interface Configuration::
2024
* Generic Peripheral Configuration::
2025
 
2026

2027
File: or1ksim.info,  Node: Memory Controller Configuration,  Next: UART Configuration,  Up: Peripheral Configuration
2028
 
2029
3.4.1 Memory Controller Configuration
2030
-------------------------------------
2031
 
2032
The memory controller used in Or1ksim is the component implemented at
2033 98 jeremybenn
OpenCores, and found in the top level SVN directory, `mem_ctrl'.  It is
2034 19 jeremybenn
described in the document `Memory Controller IP Core' by Rudolf
2035 82 jeremybenn
Usselmann, which can be found in the `doc' subdirectory.  It is a
2036
memory mapped component, which resides on the main OpenRISC Wishbone
2037
data bus.
2038 19 jeremybenn
 
2039 82 jeremybenn
The memory controller configuration is described in `section mc'.  This
2040 19 jeremybenn
section may appear multiple times, specifying multiple memory
2041 98 jeremybenn
controllers.
2042 19 jeremybenn
 
2043 385 jeremybenn
     Warning: There are known to be problems with the current memory
2044
     controller, which currently is not included in the regression test
2045
     suite. Users are advised not to use the memory controller in the
2046
     current release.
2047 98 jeremybenn
 
2048 385 jeremybenn
     Caution: There is no initialization code in the standard "newlib"
2049
     library.
2050
 
2051
     The standard "uClibc" library assumes a memory controller mapped
2052
     at 0x93000000 and will initialize the memory controller to expect
2053
     64MB memory blocks, and any memory declarations _must_ reflect
2054
     this.
2055
 
2056 98 jeremybenn
     If smaller memory blocks are declared with a memory controller,
2057
     then sufficient memory will not be allocated by Or1ksim, but out of
2058 346 jeremybenn
     range memory accesses will not be trapped.  For example declaring a
2059 98 jeremybenn
     memory section from 0-4MB with a memory controller enabled would
2060
     mean that accesses between 4MB and 64MB would be permitted, but
2061
     having no allocated memory would likely cause a segmentation fault.
2062
 
2063
     If the user is determined to use smaller memories with the memory
2064
     controller, then custom initialization code must be provided, to
2065
     ensure the memory controller traps out-of-memory accesses.
2066
 
2067
The following parameters may be specified.
2068
 
2069 19 jeremybenn
`enabled = 0|1'
2070 82 jeremybenn
     If 1 (true, the default), this memory controller is enabled.  If
2071
     0, it is disabled.
2072 19 jeremybenn
 
2073
          Note: The memory controller can effectively also be disabled
2074
          by setting an appropriate power on control register value
2075 82 jeremybenn
          (see below).  However this should only be used if it is
2076 19 jeremybenn
          desired to specifically model this behavior of the memory
2077
          controller, not as a way of disabling the memory controller
2078
          in general.
2079
 
2080
`baseaddr = VALUE'
2081
     Set the base address of the memory controller's memory mapped
2082 82 jeremybenn
     registers to VALUE.  The default is 0, which is probably not a
2083 19 jeremybenn
     sensible value.
2084
 
2085
     The memory controller has a 7 bit address bus, with a total of 19
2086
     32-bit registers, at addresses 0x00 through 0x4c (address 0x0c and
2087
     addresses 0x50 through 0x7c are not used).
2088
 
2089
`poc = VALUE'
2090
     Specifies the value of the power on control register, The least
2091
     signficant two bits specify the bus width (use 0 for an 8-bit bus,
2092
     1 for a 16-bit bus and 2 for a 32-bit bus) and the next two bits
2093
     the type of memory connected (use 0 for a disabled interface, 1
2094
     for SSRAM, 2 for asyncrhonous devices and 3 for synchronous
2095
     devices).
2096
 
2097
     If other bits are specified, they are ignored with a warning.
2098
 
2099
          Caution: The default value, 0, corresponds to a disabled
2100
          8-bit bus, and is likely not the most suitable value
2101
 
2102
`index = VALUE'
2103
     Specify the index of this memory controller amongst all the memory
2104 82 jeremybenn
     controllers.  This value should be unique for each memory
2105 19 jeremybenn
     controller, and is used to associate specific memories with the
2106
     controller, through the `mc' field in the `section memory'
2107
     configuration (*note Memory Configuration: Memory Configuration.).
2108
 
2109
     The default value, 0, is suitable when there is only one memory
2110
     controller.
2111
 
2112
 
2113

2114
File: or1ksim.info,  Node: UART Configuration,  Next: DMA Configuration,  Prev: Memory Controller Configuration,  Up: Peripheral Configuration
2115
 
2116
3.4.2 UART Configuration
2117
------------------------
2118
 
2119
The UART implemented in Or1ksim follows the specification of the
2120 82 jeremybenn
National Semiconductor 16450 and 16550 parts.  It is a memory mapped
2121 19 jeremybenn
component, which resides on the main OpenRISC Wishbone data bus.
2122
 
2123
The component provides a number of interfaces to emulate the behavior
2124
of an external terminal connected to the UART.
2125
 
2126 82 jeremybenn
UART configuration is described in `section uart'.  This section may
2127
appear multiple times, specifying multiple UARTs.  The following
2128 19 jeremybenn
parameters may be specified.
2129
 
2130
`enabled = 0|1'
2131 82 jeremybenn
     If 1 (true, the default), this UART is enabled.  If 0, it is
2132 19 jeremybenn
     disabled.
2133
 
2134
`baseaddr = VALUE'
2135
     Set the base address of the UART's memory mapped registers to
2136 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
2137 19 jeremybenn
 
2138
     The UART has a 3 bit address bus, with a total of 8 8-bit
2139
     registers, at addresses 0x0 through 0x7.
2140
 
2141
`channel = "TYPE:ARGS"'
2142
     Specify the channel representing the terminal connected to the UART
2143
     Rx & Tx pins.
2144
 
2145
    `channel="file:`rxfile',`txfile'"'
2146
          Read input characters from the file `rxfile' and write output
2147
          characters to the file `txfile' (which will be created if
2148
          required).
2149
 
2150
    `channel="xterm:ARGS"'
2151
          Create an xterm on startup, write UART Tx traffic to the
2152
          xterm and take Rx traffic from the keyboard when the xterm
2153 82 jeremybenn
          window is selected.  Additional arguments to the xterm
2154
          command (for example specifying window size may be specified
2155
          in ARGS, or this may be left blank.
2156 19 jeremybenn
 
2157
    `channel="tcp:VALUE"'
2158
          Open the TCP/IP port specified by VALUE and read and write
2159
          UART traffic from and to it.
2160
 
2161
          Typically a telnet session is connected to the other end of
2162
          this port.
2163
 
2164
               Tip: There is no registered port for Or1ksim telnet UART
2165 82 jeremybenn
               connection.  Priviledged access is required to read
2166 19 jeremybenn
               traffic on the registered "well-known" telnet port (23).
2167 346 jeremybenn
               Instead users should use port values in the "Dynamic" or
2168
               "Private" port range, i.e.  49152-65535.
2169 19 jeremybenn
 
2170
    `channel="fd:`rxfd',`txfd'"'
2171
          Read and write characters from and to the existing open
2172
          numerical file descriptors, file `rxfd' and `txfd'.
2173
 
2174
    `channel="tty:device=/dev/ttyS0,baud=9600"'
2175
          Read and write characters from and to a physical serial port.
2176 346 jeremybenn
          The precise device (shown here as `/dev/ttyS0') may vary from
2177
          machine to machine.
2178 19 jeremybenn
 
2179
 
2180
     The default value for this field is `"xterm:"'.
2181
 
2182
`irq = VALUE'
2183 82 jeremybenn
     Use VALUE as the IRQ number of this UART.  Default value 0.
2184 19 jeremybenn
 
2185
`16550 = 0|1'
2186 82 jeremybenn
     If 1 (true), the UART has the functionality of a 16550.  If 0 (the
2187
     default), it has the functionality of a 16450.  The principal
2188 19 jeremybenn
     difference is that the 16550 can buffer multiple characters.
2189
 
2190
`jitter = VALUE'
2191
     Set the jitter, modeled as a time to block, to VALUE milliseconds.
2192 82 jeremybenn
     Set to -1 to disable jitter modeling.  Default value 0.
2193 19 jeremybenn
 
2194
          Note: This functionality has yet to be implemented, so this
2195
          parameter has no effect.
2196
 
2197
`vapi_id = VALUE'
2198
     VALUE specifies the value of the Verification API (VAPI) base
2199 82 jeremybenn
     address to be used with the UART.  *Note Verification API:
2200 19 jeremybenn
     Verification API, for more details, which details the use of the
2201
     VAPI with the UART.
2202
 
2203
 
2204

2205
File: or1ksim.info,  Node: DMA Configuration,  Next: Ethernet Configuration,  Prev: UART Configuration,  Up: Peripheral Configuration
2206
 
2207
3.4.3 DMA Configuration
2208
-----------------------
2209
 
2210
The DMA controller used in Or1ksim is the component implemented at
2211 98 jeremybenn
OpenCores, and found in the top level SVN directory, `wb_dma'.  It is
2212 19 jeremybenn
described in the document `Wishbone DMA/Bridge IP Core' by Rudolf
2213 82 jeremybenn
Usselmann, which can be found in the `doc' subdirectory.  It is a
2214
memory mapped component, which resides on the main OpenRISC Wishbone
2215
data bus.  The present implementation is incomplete, intended only to
2216
support the Ethernet interface (*note Ethernet Configuration::),
2217
although the Ethernet interface is not yet completed.
2218 19 jeremybenn
 
2219 82 jeremybenn
DMA configuration is described in `section dma'.  This section may
2220
appear multiple times, specifying multiple DMA controllers.  The
2221 19 jeremybenn
following parameters may be specified.
2222
 
2223
`enabled = 0|1'
2224 82 jeremybenn
     If 1 (true, the default), this DMA controller is enabled.  If 0,
2225
     it is disabled.
2226 19 jeremybenn
 
2227
`baseaddr = VALUE'
2228
     Set the base address of the DMA's memory mapped registers to
2229 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
2230 19 jeremybenn
 
2231
     The DMA controller has a 10 bit address bus, with a total of 253
2232 82 jeremybenn
     32-bit registers.  The first 5 registers at addresses 0x000 through
2233
     0x010 control the overall behavior of the DMA controller.  There
2234
     are then 31 blocks of 8 registers, controlling each of the 31 DMA
2235
     channels available.  Addresses 0x014 through 0x01c are not used.
2236 19 jeremybenn
 
2237
`irq = VALUE'
2238 82 jeremybenn
     Use VALUE as the IRQ number of this DMA controller.  Default value
2239 19 jeremybenn
     0.
2240
 
2241
`vapi_id = VALUE'
2242
     VALUE specifies the value of the Verification API (VAPI) base
2243 82 jeremybenn
     address to be used with the DMA controller.  *Note Verification
2244 19 jeremybenn
     API: Verification API, for more details, which details the use of
2245
     the VAPI with the DMA controller.
2246
 
2247
 
2248

2249
File: or1ksim.info,  Node: Ethernet Configuration,  Next: GPIO Configuration,  Prev: DMA Configuration,  Up: Peripheral Configuration
2250
 
2251
3.4.4 Ethernet Configuration
2252
----------------------------
2253
 
2254 82 jeremybenn
Ethernet configuration is described in `section ethernet'.  This
2255
section may appear multiple times, specifying multiple Ethernet
2256
interfaces.  The following parameters may be specified.
2257 19 jeremybenn
 
2258 440 jeremybenn
The Ethernet MAC used in Or1ksim corresponds to the Verilog
2259
implementation in project "ethmac". It's source code can be found in
2260
the top level SVN directory, `ethmac'.  It also forms part of the
2261
OpenRISC reference SoC, ORPSoC.  It is described in the document
2262
`Ethernet IP Core Specification' by Igor Mohor, which can be found in
2263
the `doc' subdirectory.  It is a memory mapped component, which resides
2264
on the main OpenRISC Wishbone data bus.
2265
 
2266 19 jeremybenn
`enabled = 0|1'
2267 82 jeremybenn
     If 1 (true, the default), this Ethernet MAC is enabled.  If 0, it
2268
     is disabled.
2269 19 jeremybenn
 
2270
`baseaddr = VALUE'
2271
     Set the base address of the MAC's memory mapped registers to
2272 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
2273 19 jeremybenn
 
2274
     The Ethernet MAC has a 7-bit address bus, with a total of 21
2275 82 jeremybenn
     32-bit registers.  Addresses 0x54 through 0x7c are not used.
2276 19 jeremybenn
 
2277
          Note: The Ethernet specification describes a Tx control
2278 82 jeremybenn
          register, `TXCTRL', at address 0x50.  However this register
2279
          is not implemented in the Or1ksim model.
2280 19 jeremybenn
 
2281
`dma = VALUE'
2282
     VALUE specifies the DMA controller with which this Ethernet is
2283 82 jeremybenn
     associated.  The default value is 0.
2284 19 jeremybenn
 
2285
          Note: Support for external DMA is not provided in the current
2286 82 jeremybenn
          implementation, and this value is ignored.  In any case there
2287 19 jeremybenn
          is no equivalent field to which this can be matched in the
2288
          current DMA component implementation (*note DMA
2289
          Configuration: DMA Configuration.).
2290
 
2291
`irq = VALUE'
2292 82 jeremybenn
     Use VALUE as the IRQ number of this Ethernet MAC.  Default value 0.
2293 19 jeremybenn
 
2294 440 jeremybenn
`rtx_type = "file"|"tap"'
2295
     Specifies whether to use a TUN/TAP interface or file interface
2296
     (the default) to model the external connection of the Ethernet.
2297 19 jeremybenn
 
2298 440 jeremybenn
     If a TUN/TAP interface is requested, Ethernet packets will be sent
2299
     and received through the pesistent TAP interface specified in
2300
     parameter `tap_dev' (see below).
2301 19 jeremybenn
 
2302 440 jeremybenn
     More details on configuring the TUN/TAP interface are given in the
2303
     Usage section (*note Ethernet TUN/TAP Interface: Ethernet TUN/TAP
2304
     Interface.).
2305 19 jeremybenn
 
2306 440 jeremybenn
     If a file interface (the default), is requested, the Ethernet will
2307
     be modelled by reading and writing from and to the files specified
2308
     in the `rxfile' and `txfile' parameters (see below).
2309
 
2310
          Caution: If a file interface is specified, Or1ksim will
2311
          terminate once the receive file specified by `rxfile' is
2312
          exhausted.
2313
 
2314 19 jeremybenn
`rx_channel = RXVALUE'
2315
`tx_channel = TXVALUE'
2316
     RXVALUE specifies the DMA channel to use for receive and TXVALUE
2317 82 jeremybenn
     the DMA channel to use for transmit.  Both default to 0.
2318 19 jeremybenn
 
2319
          Note: As noted above, support for external DMA is not
2320
          provided in the current implementation, and so these values
2321
          are ignored.
2322
 
2323
`rxfile = "RXFILE"'
2324
`txfile = "TXFILE"'
2325
     When `rtx_type' is 0 (see above), RXFILE specifies the file to use
2326
     as input and TXFILE specifies the fie to use as output.
2327
 
2328 82 jeremybenn
     The file contains a sequence of packets.  Each packet consists of a
2329
     packet length (32 bits), followed by that many bytes of data.
2330
     Once the input file is empty, the Ethernet MAC behaves as though
2331
     there were no data on the Ethernet.  The default values of these
2332 19 jeremybenn
     parameters are `"eth_rx"' and `"eth_tx"' respectively.
2333
 
2334 82 jeremybenn
     The input file must exist and be readable.  The output file must be
2335
     writable and will be created if necessary.  If either of these
2336 19 jeremybenn
     conditions is not met, a warning will be given.
2337
 
2338 440 jeremybenn
          Caution: Or1ksim will terminate once the RXFILE is exhausted.
2339 19 jeremybenn
 
2340 440 jeremybenn
`tap_dev = "TAP"'
2341
     When `rtx_type' is `"tap"' (see above), TAP_DEV specifies the TAP
2342
     device to use for communication.  This should be a persistent TAP
2343
     device configured for the system (*note Ethernet TUN/TAP
2344
     Interface: Ethernet TUN/TAP Interface.)
2345
 
2346 451 jeremybenn
`phy_addr = VALUE'
2347
     VALUE specifies the address for emulated ethernet PHY (default 0).
2348
     If there are multiple Ethernet peripherals, they should each have a
2349
     different PHY value.
2350
 
2351
`dummy_crc = 0|1'
2352
     If 1 (true, the default), the length of the data transferred to
2353
     the core will be increased by 4 bytes, as though the CRC were
2354
     included.
2355
 
2356
          Note: This is for historical consistency with the OpenRISC
2357
          Ethernet hardware MAC, which passes on the CRC in the data
2358
          packet. This is unusual behavior for a MAC, but the OpenRISC
2359
          Linux device drivers have been written to expect it.
2360
 
2361
`phy_addr = VALUE'
2362
     VALUE specifies the address for emulated ethernet PHY (default 0).
2363
     If there are multiple Ethernet peripherals, they should each have a
2364
     different PHY value.
2365
 
2366 19 jeremybenn
`vapi_id = VALUE'
2367
     VALUE specifies the value of the Verification API (VAPI) base
2368 82 jeremybenn
     address to be used with the Ethernet PHY.  *Note Verification API:
2369 19 jeremybenn
     Verification API, for more details, which details the use of the
2370
     VAPI with the DMA controller.
2371
 
2372
 
2373

2374
File: or1ksim.info,  Node: GPIO Configuration,  Next: Display Interface Configuration,  Prev: Ethernet Configuration,  Up: Peripheral Configuration
2375
 
2376
3.4.5 GPIO Configuration
2377
------------------------
2378
 
2379
The GPIO used in Or1ksim is the component implemented at OpenCores, and
2380 98 jeremybenn
found in the top level SVN directory, `gpio'.  It is described in the
2381 19 jeremybenn
document `GPIO IP Core Specification' by Damjan Lampret and Goran
2382 82 jeremybenn
Djakovic, which can be found in the `doc' subdirectory.  It is a memory
2383 19 jeremybenn
mapped component, which resides on the main OpenRISC Wishbone data bus.
2384
 
2385 82 jeremybenn
GPIO configuration is described in `section gpio'.  This section may
2386
appear multiple times, specifying multiple GPIO devices.  The following
2387 19 jeremybenn
parameters may be specified.
2388
 
2389
`enabled = 0|1'
2390 82 jeremybenn
     If 1 (true, the default), this GPIO is enabled.  If 0, it is
2391 19 jeremybenn
     disabled.
2392
 
2393
`baseaddr = VALUE'
2394
     Set the base address of the GPIO's memory mapped registers to
2395 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
2396 19 jeremybenn
 
2397
     The GPIO has a 6 bit address bus, with a total of 10 32-bit
2398
     registers, although the number of bits that are actively used
2399 82 jeremybenn
     varies.  Addresses 0x28 through 0x3c are not used.
2400 19 jeremybenn
 
2401
`irq = VALUE'
2402 82 jeremybenn
     Use VALUE as the IRQ number of this GPIO.  Default value 0.
2403 19 jeremybenn
 
2404
`vapi_id = VALUE'
2405
     VALUE specifies the value of the Verification API (VAPI) base
2406 82 jeremybenn
     address to be used with the GPIO.  *Note Verification API:
2407 19 jeremybenn
     Verification API, for more details, which details the use of the
2408 82 jeremybenn
     VAPI with the GPIO controller.  For backwards compatibility, the
2409 19 jeremybenn
     alternative name `base_vapi_id' is supported for this parameter,
2410
     but deprecated.
2411
 
2412
 
2413

2414
File: or1ksim.info,  Node: Display Interface Configuration,  Next: Frame Buffer Configuration,  Prev: GPIO Configuration,  Up: Peripheral Configuration
2415
 
2416
3.4.6 Display Interface Configuration
2417
-------------------------------------
2418
 
2419
Or1ksim models a VGA interface to an external monitor.  The VGA
2420
controller used in Or1ksim is the component implemented at OpenCores,
2421 98 jeremybenn
and found in the top level SVN directory, `vga_lcd', with no support
2422 82 jeremybenn
for the optional hardware cursors.  It is described in the document
2423 19 jeremybenn
`VGA/LCD Core v2.0 Specifications' by Richard Herveille, which can be
2424 82 jeremybenn
found in the `doc' subdirectory.  It is a memory mapped component,
2425
which resides on the main OpenRISC Wishbone data bus.
2426 19 jeremybenn
 
2427
The current implementation provides only functionality to dump the
2428
screen to a file at intervals.
2429
 
2430 82 jeremybenn
VGA controller configuration is described in `section vga'.  This
2431 19 jeremybenn
section may appear multiple times, specifying multiple VGA controllers.
2432
The following parameters may be specified.
2433
 
2434
`enabled = 0|1'
2435 82 jeremybenn
     If 1 (true, the default), this VGA is enabled.  If 0, it is
2436 19 jeremybenn
     disabled.
2437
 
2438
`baseaddr = VALUE'
2439
     Set the base address of the VGA controller's memory mapped
2440 82 jeremybenn
     registers to VALUE.  The default is 0, which is probably not a
2441 19 jeremybenn
     sensible value.
2442
 
2443
     The VGA controller has a 12-bit address bus, with 7 32-bit
2444
     registers, at addresses 0x000 through 0x018, and two color lookup
2445 82 jeremybenn
     tables at addresses 0x800 through 0xfff.  The hardware cursor
2446 19 jeremybenn
     registers are not implemented, so addresses 0x01c through 0x7fc
2447
     are not used.
2448
 
2449
`irq = VALUE'
2450 82 jeremybenn
     Use VALUE as the IRQ number of this VGA controller.  Default value
2451 19 jeremybenn
     0.
2452
 
2453
`refresh_rate = VALUE'
2454 82 jeremybenn
     VALUE specifies number of cycles between screen dumps.  Default
2455 19 jeremybenn
     value is derived from the simulation clock cycle time (*note
2456
     Simulator Behavior: Simulator Behavior.), to correspond to dumping
2457
     50 times per simulated second.
2458
 
2459
`txfile = "FILE"'
2460
     FILE specifies the base of the filename for screen dumps.
2461
     Successive screen dumps will be in BMP format, in files with the
2462
     name `FILENNNN.bmp', where NNNN is a sequential count of the
2463 82 jeremybenn
     screen dumps starting at zero.  The default value is `"vga_out"'.
2464 19 jeremybenn
     For backwards compatibility, the alternative name `filename' is
2465
     supported for this parameter, but deprecated.
2466
 
2467
 
2468

2469
File: or1ksim.info,  Node: Frame Buffer Configuration,  Next: Keyboard Configuration,  Prev: Display Interface Configuration,  Up: Peripheral Configuration
2470
 
2471
3.4.7 Frame Buffer Configuration
2472
--------------------------------
2473
 
2474 82 jeremybenn
     Caution: The frame buffer is only partially implemented.  Its
2475 19 jeremybenn
     configuration fields are described here, but the component should
2476 82 jeremybenn
     not be used at this time.  Like the VGA controller, it is designed
2477 19 jeremybenn
     to make screen dumps to file.
2478
 
2479 82 jeremybenn
Frame buffer configuration is described in `section fb'.  This section
2480
may appear multiple times, specifying multiple frame buffers.  The
2481 19 jeremybenn
following parameters may be specified.
2482
 
2483
`enabled = 0|1'
2484 82 jeremybenn
     If 1 (true, the default), this frame buffer is enabled.  If 0, it
2485 19 jeremybenn
     is disabled.
2486
 
2487
`baseaddr = VALUE'
2488
     Set the base address of the frame buffer's memory mapped registers
2489 82 jeremybenn
     to VALUE.  The default is 0, which is probably not a sensible
2490
     value.
2491 19 jeremybenn
 
2492
     The frame buffer has an 121-bit address bus, with 4 32-bit
2493
     registers, at addresses 0x000 through 0x00c, and a PAL lookup
2494 82 jeremybenn
     table at addresses 0x400 through 0x4ff.  Addresses 0x010 through
2495 19 jeremybenn
     0x3fc and addresses 0x500 through 0x7ff are not used.
2496
 
2497
`refresh_rate = VALUE'
2498 82 jeremybenn
     VALUE specifies number of cycles between screen dumps.  Default
2499 19 jeremybenn
     value is derived from the simulation clock cycle time (*note
2500
     Simulator Behavior: Simulator Behavior.), to correspond to dumping
2501
     50 times per simulated second.
2502
 
2503
`txfile = "FILE"'
2504
     FILE specifies the base of the filename for screen dumps.
2505
     Successive screen dumps will be in BMP format, in files with the
2506
     name `FILENNNN.bmp', where NNNN is a sequential count of the
2507 82 jeremybenn
     screen dumps starting at zero.  The default value is `"fb_out"'.
2508 19 jeremybenn
     For backwards compatibility, the alternative name `filename' is
2509
     supported for this parameter, but deprecated.
2510
 
2511
 
2512

2513
File: or1ksim.info,  Node: Keyboard Configuration,  Next: Disc Interface Configuration,  Prev: Frame Buffer Configuration,  Up: Peripheral Configuration
2514
 
2515
3.4.8 Keyboard Configuration (PS2)
2516
----------------------------------
2517
 
2518 82 jeremybenn
The PS2 interface provided by Or1ksim is not documented.  It may be
2519 98 jeremybenn
based on the PS2 project at OpenCores, and found in the top level SVN
2520 82 jeremybenn
directory, `ps2'.  However this project lacks any documentation beyond
2521
its project webpage.  Since most PS2 interfaces follow the Intel i8042
2522 19 jeremybenn
standard, this is presumably what is expected with this device.
2523
 
2524
The implementation only provides for keyboard support, which is
2525 82 jeremybenn
modelled as a file of keystrokes.  There is no mouse support.
2526 19 jeremybenn
 
2527
     Caution: A standard i8042 device has two registers at addresses
2528 82 jeremybenn
     0x60 (command) and 0x64 (status).  Inspection of the code,
2529
     suggests that the Or1ksim component places these registers at
2530
     addresses 0x00 and 0x04.
2531 19 jeremybenn
 
2532
     The port of Linux for the OpenRISC 1000, which runs on Or1ksim
2533
     implements the i8042 device driver, anticipating these registers
2534 82 jeremybenn
     reside at their conventional address.  It seems unlikel that this
2535 19 jeremybenn
     code will work.
2536
 
2537
     This component should be used with caution.
2538
 
2539 82 jeremybenn
Keyboard configuration is described in `section kbd'.  This section may
2540
appear multiple times, specifying multiple keyboard interfaces.  The
2541 19 jeremybenn
following parameters may be specified.
2542
 
2543
`enabled = 0|1'
2544 82 jeremybenn
     If 1 (true, the default), this keyboard is enabled.  If 0, it is
2545 19 jeremybenn
     disabled.
2546
 
2547
`baseaddr = VALUE'
2548
     Set the base address of the keyboard's memory mapped registers to
2549 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
2550 19 jeremybenn
 
2551
     The keyboard PS/2 interface has an 3-bit address bus, with 2 8-bit
2552
     registers, at addresses 0x000 and 0x004.
2553
 
2554
          Caution: As noted above, a standard Intel 8042 interface
2555
          would expect to find these registers at locations 0x60 and
2556
          0x64, thus requiring at least a 7-bit bus.
2557
 
2558
`irq = VALUE'
2559 82 jeremybenn
     Use VALUE as the IRQ number of this Keyboard interface.  Default
2560 19 jeremybenn
     value 0.
2561
 
2562
`rxfile = "FILE"'
2563
     `file' specifies a file containing raw key stroke data, which
2564 82 jeremybenn
     models the input from a physical keyboard.  The default value is
2565 19 jeremybenn
     `"kbd_in"'.
2566
 
2567
 
2568

2569
File: or1ksim.info,  Node: Disc Interface Configuration,  Next: Generic Peripheral Configuration,  Prev: Keyboard Configuration,  Up: Peripheral Configuration
2570
 
2571
3.4.9 Disc Interface Configuration
2572
----------------------------------
2573
 
2574
The ATA/ATAPI disc controller used in Or1ksim is the OCIDEC (OpenCores
2575
IDE Controller) component implemented at OpenCores, and found in the
2576 98 jeremybenn
top level SVN directory, `ata'.  It is described in the document
2577 19 jeremybenn
`ATA/ATAPI-5 Core Specification' by Richard Herveille, which can be
2578 82 jeremybenn
found in the `doc' subdirectory.  It is a memory mapped component,
2579
which resides on the main OpenRISC Wishbone data bus.
2580 19 jeremybenn
 
2581 385 jeremybenn
     Warning: In the current release of Or1ksim, parsing of the ATA
2582
     section is broken. Users should not configure the disc interface
2583
     in this release.
2584
 
2585 82 jeremybenn
ATA/ATAPI configuration is described in `section ata'.  This section
2586
may appear multiple times, specifying multiple disc controllers.  The
2587 19 jeremybenn
following parameters may be specified.
2588
 
2589
`enabled = 0|1'
2590 82 jeremybenn
     If 1 (true, the default), this ATA/ATAPI interface is enabled.  If
2591 19 jeremybenn
     0, it is disabled.
2592
 
2593
`baseaddr = VALUE'
2594
     Set the base address of the ATA/ATAPI interface's memory mapped
2595 82 jeremybenn
     registers to VALUE.  The default is 0, which is probably not a
2596 19 jeremybenn
     sensible value.
2597
 
2598
     The ATA/ATAPI PS/2 interface has an 5-bit address bus, with 8
2599 82 jeremybenn
     32-bit registers.  Depending on the version of the OCIDEC
2600
     ATA/ATAPI interface selected (see `dev_id' below), not all
2601
     registers will be available.
2602 19 jeremybenn
 
2603
`irq = VALUE'
2604 82 jeremybenn
     Use VALUE as the IRQ number of this ATA/ATAPI interface.  Default
2605 19 jeremybenn
     value 0.
2606
 
2607
`dev_id = 1|2|3'
2608
     This parameter specifies which version of the OCIDEC ATA/ATAPI
2609 82 jeremybenn
     interface to model.  The default value is 1.
2610 19 jeremybenn
 
2611
     Version 1 supports only the `CTRL', `STAT' and `PCTR' registers.
2612
     Versions 2 & 3 add the `FCTR' registers, Version 3 adds the `DTR'
2613
     registers and the `RXD'/`TXD' registers.
2614
 
2615
`rev = VALUE'
2616
     Set the VALUE as the revision of the OCIDEC ATA/ATAPI interface.
2617 82 jeremybenn
     The default value is 1.  The default value is 0.  Its value should
2618
     be in the range 0-15.  Larger values are truncated with a warning.
2619 346 jeremybenn
     This only affects the reset value of the `STAT' register, where it
2620
     forms bits 24-27.
2621 19 jeremybenn
 
2622
`pio_mode0_t1 = VALUE'
2623
`pio_mode0_t2 = VALUE'
2624
`pio_mode0_t4 = VALUE'
2625
`pio_mode0_teoc = VALUE'
2626
     These parameters specify the timings for use with Programmed
2627 82 jeremybenn
     Input/Output (PIO) transfers.  They are specified as the number of
2628 19 jeremybenn
     clock cycles - 2, rounded up to the next highest integer, or zero
2629 82 jeremybenn
     if that would be negative.  The values should not exceed 255.  If
2630 19 jeremybenn
     they do, they will be ignored with a warning.
2631
 
2632
     See the ATA/ATAPI-5 specification for explanations of each of these
2633 82 jeremybenn
     timing parameters.  The default values are:
2634 19 jeremybenn
 
2635
          pio_mode0_t1   =  6
2636
          pio_mode0_t2   = 28
2637
          pio_mode0_t4   =  2
2638
          pio_mode0_teoc = 23
2639
 
2640
`dma_mode0_tm = VALUE'
2641
`dma_mode0_td = VALUE'
2642
`dma_mode0_teoc = VALUE'
2643
     These parameters specify the timings for use with DMA transfers.
2644
     They are specified as the number of clock cycles - 2, rounded up
2645
     to the next highest integer, or zero if that would be negative.
2646 82 jeremybenn
     The values should not exceed 255.  If they do, they will be
2647
     ignored with a warning.
2648 19 jeremybenn
 
2649
     See the ATA/ATAPI-5 specification for explanations of each of these
2650 82 jeremybenn
     timing parameters.  The default values are:
2651 19 jeremybenn
 
2652
          dma_mode0_tm   =  4
2653
          dma_mode0_td   = 21
2654
          dma_mode0_teoc = 21
2655
 
2656
 
2657
3.4.9.1 ATA/ATAPI Device Configuration
2658
......................................
2659
 
2660 82 jeremybenn
Within the `section ata', each device is specified separately.  The
2661 19 jeremybenn
device subsection is introduced by
2662
 
2663
     device VALUE
2664
 
2665 82 jeremybenn
VALUE is the device number, which should be 0 or 1.  The subsection
2666
ends with `enddevice'.  Note that if the same device number is
2667
specified more than once, the previous values will be overwritten.
2668
Within the `device' subsection, the following parameters may appear:
2669 19 jeremybenn
 
2670
`type = VALUE'
2671
     VALUEspecifies the type of device: 0 (the default) for "not
2672
     connected", 1 for hard disk simulated in a file and 2 for local
2673
     system hard disk.
2674
 
2675
`file = "FILENAME"'
2676
     `filename' specifies the file to be used for a simulated ATA
2677 82 jeremybenn
     device if the file type (see `type' above) is 1.  Default value
2678 346 jeremybenn
     `"ata_fileN"', where N is the device number.
2679 19 jeremybenn
 
2680
`size = VALUE'
2681
     VALUE specifies the size of a simulated ATA device if the file
2682 82 jeremybenn
     type (see `type' above) is 1.  The default value is zero.
2683 19 jeremybenn
 
2684
`packet = 0|1'
2685 82 jeremybenn
     If 1 (true), implement the PACKET command feature set.  If 0 (the
2686 19 jeremybenn
     default), do not implement the PACKET command feature set.
2687
 
2688
`firmware = "STR"'
2689
     Firmware to report in response to the "Identify Device" command.
2690
     Default `"02207031"'.
2691
 
2692
`heads = VALUE'
2693 82 jeremybenn
     Number of heads in the device.  Default 7, use -1 to disable all
2694 19 jeremybenn
     heads.
2695
 
2696
`sectors = VALUE'
2697 82 jeremybenn
     Number of sectors per track in the device.  Default 32.
2698 19 jeremybenn
 
2699
`mwdma = 0|1|2|-1'
2700 82 jeremybenn
     Highest multi-word DMA mode supported.  Default 2, use -1 to
2701 19 jeremybenn
     disable.
2702
 
2703
`pio = 0|1|2|3|4'
2704 82 jeremybenn
     Highest PIO mode supported.  Default 4.
2705 19 jeremybenn
 
2706
 
2707

2708
File: or1ksim.info,  Node: Generic Peripheral Configuration,  Prev: Disc Interface Configuration,  Up: Peripheral Configuration
2709
 
2710
3.4.10 Generic Peripheral Configuration
2711
---------------------------------------
2712
 
2713
When used as a library (*note Simulator Library: Simulator Library.),
2714
Or1ksim makes provision for any additional peripheral to be implemented
2715 82 jeremybenn
externally.  Any read or write access to this peripheral's memory map
2716
generates "upcall"s to an external handler.  This interface can support
2717 19 jeremybenn
either C or C++, and was particularly designed to facilitate support
2718
for OSCI SystemC (see `http://www.systemc.org').
2719
 
2720
Generic peripheral configuration is described in `section generic'.
2721
This section may appear multiple times, specifying multiple external
2722 82 jeremybenn
peripherals.  The following parameters may be specified.
2723 19 jeremybenn
 
2724
`enabled = 0|1'
2725 82 jeremybenn
     If 1 (true, the default), this ATA/ATAPI interface is enabled.  If
2726 19 jeremybenn
     0, it is disabled.
2727
 
2728
`baseaddr = VALUE'
2729
     Set the base address of the generic peripheral's memory mapped
2730 82 jeremybenn
     registers to VALUE.  The default is 0, which is probably not a
2731 19 jeremybenn
     sensible value.
2732
 
2733
     The size of the memory mapped register space is controlled by the
2734
     `size' paramter, described below.
2735
 
2736
`size = VALUE'
2737
     Set the size of the generic peripheral's memory mapped register
2738 82 jeremybenn
     space to VALUE bytes.  Any read or write accesses to addresses with
2739 19 jeremybenn
     offsets of 0 to VALUE-1 bytes from the base address specified in
2740
     parameter `baseaddr' (see above) will be directed to the external
2741
     interface.
2742
 
2743 82 jeremybenn
     VALUE will be rounded up the nearest power of 2.  It's default
2744
     value is zero.  If VALUE is not an exact power of two, accesses to
2745 19 jeremybenn
     address offsets of VALUE or above up to the next power of 2 will
2746
     generate a warning, and have no effect (reads will return zero).
2747
 
2748
`name = "STR"'
2749 82 jeremybenn
     This gives the peripheral the name `"STR"'.  This is used to
2750 19 jeremybenn
     identify the peripheral in error messages and warnings, and when
2751 82 jeremybenn
     reporting its status.  The default value is
2752 19 jeremybenn
     `"anonymous external peripheral"'.
2753
 
2754
`byte_enabled = 0|1'
2755
`hw_enabled = 0|1'
2756
`word_enabled = 0|1'
2757
     If 1 (true, the default), these parameters respectively enable the
2758 82 jeremybenn
     device for byte wide, half-word wide and word wide accesses.  If 0,
2759 19 jeremybenn
     accesses of that width will fail.
2760
 
2761
 
2762

2763
File: or1ksim.info,  Node: Interactive Command Line,  Next: Verification API,  Prev: Configuration,  Up: Top
2764
 
2765
4 Interactive Command Line
2766
**************************
2767
 
2768
If started with the `-f' flag, or if interrupted with `ctrl-C', Or1ksim
2769 82 jeremybenn
provides the user with an interactive command line.  The commands
2770 19 jeremybenn
available, which may not be abbreviated, are:
2771
 
2772
`q'
2773
     Exit the simulator
2774
 
2775
`r'
2776 82 jeremybenn
     Display all the General Purpose Registers (GPRs).  Also shows the
2777 19 jeremybenn
     just executed and next to be executed instructions symbolically
2778
     and the state of the flag in the Supervision Register.
2779
 
2780
`t'
2781
     Execute the next instruction and then display register/instruction
2782
     information as with the `r' command (see above).
2783
 
2784
`run NUM [ hush ]'
2785 82 jeremybenn
     Execute NUM instructions.  The register/instruction information is
2786 19 jeremybenn
     displayed after each instruction, as with the `r' command (see
2787
     above) _unless_ `hush' is specified.
2788
 
2789
`pr REG VALUE'
2790
     Patch register REG with VALUE.
2791
 
2792
`dm FROMADDR [ TOADDR ]'
2793 82 jeremybenn
     Display memory bytes between FROMADDR and TOADDR.  If TOADDR is
2794
     not given, 64 bytes are displayed, starting at FROMADDR.
2795 19 jeremybenn
 
2796
          Caution: The output from this command is broken (a bug).
2797 82 jeremybenn
          Or1ksim attempts to print out 16 bytes per row.  However,
2798 19 jeremybenn
          instead of printing out the address at the start of each row,
2799
          it prints the address (of the first of the 16 bytes) before
2800
          _each_ byte.
2801
 
2802
`de FROMADDR [ TOADDR ]'
2803 82 jeremybenn
     Disassemble code between FROMADDR and TOADDR.  If TOADDR is not
2804 19 jeremybenn
     given, 16 instructions are disassembled.
2805
 
2806
     The disassembly is entirely numerical, and gives no symbolic
2807
     information.
2808
 
2809
`pm ADDR VALUE'
2810
     Patch the 4 bytes in memory starting at ADDR with the 32-bit VALUE.
2811
 
2812
`pc VALUE'
2813
     Patch the program counter with VALUE.
2814
 
2815
`cm FROMADDR TOADDR SIZE'
2816
     Copy SIZE bytes in memory from FROMADDR to TOADDR.
2817
 
2818
`break ADDR'
2819
     Toggle the breakpoint set at ADDR.
2820
 
2821
`breaks'
2822
     List all set breakpoints
2823
 
2824
`reset'
2825 82 jeremybenn
     Reset the simulator.  Includes modeling a reset of the processor,
2826
     so execution will restart from the reset vector location, 0x100.
2827 19 jeremybenn
 
2828
`hist'
2829
     If saving the execution history has been configured (*note
2830
     Simulator Behavior: Simulator Behavior.), display the execution
2831
     history.
2832
 
2833
`stall'
2834
     Stall the processor, so that control is passed to the debug unit.
2835 82 jeremybenn
     When stalled, the processor can execute no instructions.  This
2836 19 jeremybenn
     command is useful when debugging the JTAG interface, used by
2837
     debuggers such as GDB.
2838
 
2839
`unstall'
2840 82 jeremybenn
     Unstall the processor, so that normal execution can continue.
2841
     This command is useful when debugging the JTAG interface, used by
2842 19 jeremybenn
     debuggers such as GDB.
2843
 
2844
`stats CATEGORY | clear'
2845
     Print the statistics for the given CATEGORY, if available, or
2846 82 jeremybenn
     clear if `clear' is specified.  The categories are:
2847 19 jeremybenn
 
2848
    1
2849
          Miscellaneous statistics: branch predictions (if branch
2850
          predictions are enabled), branch target cache model (if
2851
          enabled), cache (if enbaled), MMU (if enabled) and number of
2852
          addtional load & store cycles.
2853
 
2854
          *Note Configuring the OpenRisc Achitectural Components: Core
2855
          OpenRISC Configuration, for details of how to enable these
2856
          various features.
2857
 
2858
    2
2859 82 jeremybenn
          Instruction usage statistics.  Requires hazard analysis to be
2860 19 jeremybenn
          enabled (*note CPU Configuration: CPU Configuration.).
2861
 
2862
    3
2863 82 jeremybenn
          Instruction dependency statistics.  Requires hazard analysis
2864 19 jeremybenn
          to be enabled (*note CPU Configuration: CPU Configuration.).
2865
 
2866
    4
2867 82 jeremybenn
          Functional unit dependency statistics.  Requires hazard
2868 19 jeremybenn
          analysis to be enabled (*note CPU Configuration: CPU
2869
          Configuration.).
2870
 
2871
    5
2872 82 jeremybenn
          Raw register usage over time.  Requires hazard analysis to be
2873 19 jeremybenn
          enabled (*note CPU Configuration: CPU Configuration.).
2874
 
2875
    6
2876 82 jeremybenn
          Store buffer statistics.  Requires the store buffer to be
2877 19 jeremybenn
          enabled (*note CPU Configuration: CPU Configuration.).
2878
 
2879
 
2880
`info'
2881
     Display detailed information about the simulator configuration.
2882
     This is quite a lengthy about, because all MMU TLB information is
2883
     displayed.
2884
 
2885
`dv FROMADDR [ TOADDR ] [ MODULE ]'
2886
     Dump the area of memory between FROMADDR and TOADDR as Verilog
2887 82 jeremybenn
     code for a synchronous, 23-bit wide SRAM module, named MODULE.  If
2888 19 jeremybenn
     TOADDR is not specified, then 64 bytes are dumped (as 16 32-bit
2889 82 jeremybenn
     words).  If MODULE is not specified, `or1k_mem' is used.
2890 19 jeremybenn
 
2891
     To save to a file, use the redirection function (described after
2892
     this table, below).
2893
 
2894
`dh FROMADDR [ TOADDR ]'
2895
     Dump the area of memory between FROMADDR and TOADDR as 32-bit hex
2896 82 jeremybenn
     numbers (no `0x', or `32'h' prefix).  If TOADDR is not specified,
2897 19 jeremybenn
     then 64 bytes are dumped (as 16 32-bit words).
2898
 
2899
     To save to a file, use the redirection function (described after
2900
     this table, below).
2901
 
2902
`setdbch'
2903 82 jeremybenn
     Toggle debug channels on/off.  *Note Standalone Simulator:
2904 19 jeremybenn
     Standalone Simulator, for a description of specifying debug
2905
     channels on the command line.
2906
 
2907
`set SECTION PARAM = VALUE'
2908
     Set the configuration parameter PARA in section SECTION to VALUE.
2909
     *Note Configuration: Configuration, for details of configuration
2910
     parameters and their settings.
2911
 
2912
`debug'
2913 82 jeremybenn
     Toggle the simulator debug mode.  *Note Debug Interface
2914 19 jeremybenn
     Configuration: Debug Interface Configuration, for information on
2915
     this parameter.
2916
 
2917
          Caution: This is effectively enabling or disabling the debug
2918 82 jeremybenn
          unit.  It does not effect the remote GDB debug interface.
2919 19 jeremybenn
          However using the remote debug interface while the debug unit
2920
          is disabled will lead to undefined behavior and likely crash
2921
          Or1ksim
2922
 
2923
`cuc'
2924
     Enter the the Custom Unit Compiler command prompt (*note CUC
2925
     Configuration: CUC Configuration.).
2926
 
2927
          Caution: The CUC must be properly configured, for this to
2928 82 jeremybenn
          succeed.  In particular a timing file must be available and
2929
          readable.  Otherwise Or1ksim will crash.
2930 19 jeremybenn
 
2931
`help'
2932
     Print out brief information about each command available.
2933
 
2934
`mprofile [-vh] [-m M] [-g N] [-f FILE] FROM TO'
2935 82 jeremybenn
     Run the memory profiling utility.  This follows the same usage as
2936 19 jeremybenn
     the standalone command (*note Memory Profiling Utility: Memory
2937
     Profiling Utility.).
2938
 
2939
`profile [-vhcq] [-g FILE]'
2940 82 jeremybenn
     Run the instruction profiling utility.  This follows the same
2941
     usage as the standalone command (*note Profiling Utility:
2942
     Profiling Utility.).
2943 19 jeremybenn
 
2944
 
2945
For all commands, it is possible to redirect the output to a file, by
2946
using the redirection operator, `>'.
2947
 
2948
     COMMAND > FILENAME
2949
 
2950
This is particularly useful for commands dumping a large amount of
2951
output, such as `dv'.
2952
 
2953
     Caution: Unfortunately there is a serious bug with the redirection
2954 82 jeremybenn
     operator.  It does not return output to standard output after the
2955
     command completes.  Until this bug is fixed, file redirection
2956 19 jeremybenn
     should not be used.
2957
 
2958

2959
File: or1ksim.info,  Node: Verification API,  Next: Code Internals,  Prev: Interactive Command Line,  Up: Top
2960
 
2961
5 Verification API (VAPI)
2962
*************************
2963
 
2964
The Verification API (VAPI) provides a TCP/IP interface to allow
2965 82 jeremybenn
components of the simulation to be controlled externally.  The
2966
interface is polled for new requests on each simulated clock cycle.
2967
Components within the simulator may send responses to such requests.
2968 19 jeremybenn
 
2969 82 jeremybenn
The inteface is an asynchronous duplex protocol.  On the request side
2970
it provides for simple commands, known as VAPI IDs (a 32 bit integer),
2971
with a single piece of data (also a 32 bit integer).  On the send side,
2972
it provides for sending a single VAPI ID and data.  However there is no
2973
explicit command-response structure.  Some components just accept
2974
requests (e.g.  to set values), some just generate sends (to report
2975 19 jeremybenn
values), and some do both.
2976
 
2977
Each component has a base ID (32 bit) and its commands will start from
2978 82 jeremybenn
that base ID.  This provides a simple partitioning of the command space
2979
amongst components.  Request commands will be directed to the component
2980 19 jeremybenn
with the closest base ID lower than the VAPI ID of the command.
2981
 
2982
Thus if there are two components with base IDs of 0x200 and 0x300, and
2983
a request with VAPI ID of 0x203 is received, it will be directed to the
2984
first component as its command #3.
2985
 
2986
The results of VAPI interactions are logged (by default in `vapi.log'
2987
unless an alternative is specified in `section vapi').
2988
 
2989
Currently the following components support VAPI:
2990
 
2991
Debug Unit
2992
     Although the Debug Unit can specify a base VAPI ID, it is not used
2993
     to send commands or receive requests.
2994
 
2995
     Instead, if the base VAPI ID is set, all remote JTAG protocol
2996
     exchanges are logged in the VAPI log file.
2997
 
2998
UART
2999
     If a base VAPI ID is specified, the UART sends details of any
3000
     chars or break characters sent, with dteails of the line control
3001
     register etc encoded in the data packet sent.
3002
 
3003
     This supports a single VAPI command request, but encodes a
3004
     sub-command in the top 8 bits of the associated data.
3005
 
3006
    `0x00'
3007
          This stuffs the least significant 8 bits of the data into the
3008
          serial register of the UART and the next 8 bits into the line
3009
          control register, effectively providing control of the next
3010
          character to be sent or received.
3011
 
3012
    `0x01'
3013
          The divisor latch bytes are set from the least significant 16
3014
          bits of the data.
3015
 
3016
    `0x02'
3017
          The line control register is set from bits 15-8 of the data.
3018
 
3019
    `0x03'
3020
          The UART skew is set from the least significant 16 bits of
3021
          the data
3022
 
3023
    `0x04'
3024
          If the 16th most significant bit of the data is 1, start
3025 82 jeremybenn
          sending breaks, otherwise stop sending breaks.  The breaks
3026
          are sent or cleared after the number of UART clock divider
3027
          ticks specified by the data (immediately if the data is zero).
3028 19 jeremybenn
 
3029
 
3030
DMA
3031
     Although the DMA unit supports a base VAPI ID in its configuration
3032
     (`section dma'), no VAPI data is sent, nor VAPI requests currently
3033
     implemented.
3034
 
3035
Ethernet
3036 82 jeremybenn
     The following requests are handled by the Ethernet.  Specified
3037 19 jeremybenn
     symbolically, these are the increments from the base VAPI ID of the
3038 82 jeremybenn
     Ethernet.  At present no implementation is provided behind these
3039 19 jeremybenn
     VAPI requests.
3040
 
3041
    `ETH_VAPI_DATA (0)'
3042
 
3043
    `ETH_VAPI_CTRL (0)'
3044
 
3045
GPIO
3046
     If a base VAPI ID is specified, the GPIO sends out on its base
3047
     VAPI ID (symbolically, GPIO_VAPI_DATA (0) offset from the base
3048
     VAPI ID) any changes in outputs.
3049
 
3050 82 jeremybenn
     The following requests are handled by the GPIO.  Specified
3051 19 jeremybenn
     symbolically, these are the increments from the VAPI base ID of the
3052
     GPIO.
3053
 
3054
    `GPIO_VAPI_DATA (0)'
3055
          Set the next input to the commands data field
3056
 
3057
    `GPIO_VAPI_AUX (1)'
3058
          Set the GPIO auxiliary inputs to the data field
3059
 
3060
    `GPIO_VAPI_CLOCK (2)'
3061
          Add an external GPIO clock trigger of period specified in the
3062
          data field.
3063
 
3064
    `GPIO_VAPI_RGPIO_OE (3)'
3065
          Set the GPIO output enable to the data field
3066
 
3067
    `GPIO_VAPI_RGPIO_INTE (4)'
3068
          Set the next interrupt to the data field
3069
 
3070
    `GPIO_VAPI_RGPIO_PTRIG (5)'
3071
          Set the next trigger to the data field
3072
 
3073
    `GPIO_VAPI_RGPIO_AUX (6)'
3074
          Set the next auxiliary input to the data field
3075
 
3076
    `GPIO_VAPI_RGPIO_CTRL (7)'
3077
          Set th next control input to the data field
3078
 
3079
 
3080
 
3081

3082
File: or1ksim.info,  Node: Code Internals,  Next: GNU Free Documentation License,  Prev: Verification API,  Up: Top
3083
 
3084
6 A Guide to Or1ksim Internals
3085
******************************
3086
 
3087 82 jeremybenn
These are notes to help those wanting to extend Or1ksim.  This section
3088 19 jeremybenn
assumes the use of a tag file, so file locations of entities'
3089 82 jeremybenn
definitions are not in general provided.  For more on tags, see the
3090
Linux manual page for `etags'.  A tag file can be created with:
3091 19 jeremybenn
 
3092
     make tags
3093
 
3094
* Menu:
3095
 
3096
* Coding Conventions::
3097
* Global Data Structures::
3098
* Concepts::
3099
* Internal Debugging::
3100 104 jeremybenn
* Regression Testing::
3101 19 jeremybenn
 
3102

3103
File: or1ksim.info,  Node: Coding Conventions,  Next: Global Data Structures,  Up: Code Internals
3104
 
3105
6.1 Coding Conventions for Or1ksim
3106
==================================
3107
 
3108
This chapter provides some guidelines for coding, to facilitate
3109
extensions to Or1ksim
3110
 
3111
_GNU Coding Standard_
3112
     Code should follow the GNU coding standard for C
3113 82 jeremybenn
     (`http://www.gnu.org/prep/standards/'.  If in doubt, put your code
3114 19 jeremybenn
     through the `indent' program.
3115
 
3116
_`#include' headers_
3117
     All C source code files should include `config.h' before any other
3118
     file.
3119
 
3120
     This should be followed by inclusion of any system headers (but see
3121
     the comments about portability and `port.h' below) and then by any
3122
     Or1ksim package headers.
3123
 
3124
     If `port.h' is required, it should be the first package header to
3125
     be included after the system headers.
3126
 
3127
     All C source code and header files should directly include any
3128 82 jeremybenn
     system or package header they depend on, i.e.  not rely on any
3129
     other header having already included it.  The two exceptions are
3130 19 jeremybenn
 
3131
       1. All header files may assume that `config.h' has already been
3132
          included.
3133
 
3134
       2. System headers which impose portability problems should be
3135
          included by using the package header `port.h', rather than
3136 82 jeremybenn
          the system headers themselves.  This is the case for code
3137 19 jeremybenn
          requiring
3138
 
3139
             * `strndup' (from `string.h')
3140
 
3141
             * Integer types (`intN_t', `uintN_t') (from `inttypes.h').
3142
 
3143
             * `isblank' (from `ctype.h')
3144
 
3145
 
3146
 
3147
_`#include' files once only_
3148
     All include files should be protected by `#ifndef' to ensure their
3149 82 jeremybenn
     definitions are only included once.  For instance a header file
3150 19 jeremybenn
     `X-Y.H' should surround its contents with:
3151
 
3152
          #ifndef X_Y__H
3153
          #define X_Y__H
3154
 
3155
          
3156
 
3157
          #endif  /* X_Y__H */
3158
 
3159
_Avoid `typedef'_
3160
     The GNU coding style for C does not have a clear way to distinguish
3161 82 jeremybenn
     between user type name and user variables.  For this reason
3162 19 jeremybenn
     `typedef' should be avoided except for the most ubiquitous user
3163 82 jeremybenn
     defined types.  This makes the code much easier to read.
3164 19 jeremybenn
 
3165
     There are some `typedef' declarations in the `argtable2' library
3166
     and the ELF and COFF headers, because this code is taken from
3167
     other places.
3168
 
3169
     Within Or1ksim legacy uses of `typedef' have largely been purged,
3170
     except in the Custom Unit Compiler (*note Custom Unit Compiler
3171
     (CUC) Configuration: CUC Configuration.).
3172
 
3173
     The remaining uses of `typedef' occur in two places:
3174
 
3175
        * `port/port.h' defines types to replace those in header files
3176
          that are not available (character functions, string
3177
          duplication, integer types).
3178
 
3179
          `cpu/or1k/arch.h' defines types for the key Or1ksim entities:
3180
          addresses (`oraddr_t'), unsigned register values (`uorreg_t')
3181
          and signed register (`orreg_t') values.
3182
 
3183
 
3184
     Where new types are defined, they should appear in one of these two
3185 82 jeremybenn
     files as appropriate.  Or1ksim specific types appearing in
3186
     `arch.h' should always have the suffix `_h'.
3187 19 jeremybenn
 
3188
_Don't begin names with underscore_
3189
     Names beginning with `_' are intended to be part of the C
3190 82 jeremybenn
     infrastructure.  They should not be used in the simulator code.
3191 19 jeremybenn
 
3192
_Keep Non-global top level entities static_
3193
     All top level entities (functions, variables), which are not
3194
     explicitly part of a global interface should be declared static.
3195
     This ensures that unwanted connections are not inadvertently built
3196
     across the program.
3197
 
3198
_Use of `inline'_
3199 82 jeremybenn
     Code should not be declared `inline'.  Modern compilers can work
3200 19 jeremybenn
     out for themselves what is best in this respect.
3201
 
3202
_Initialization_
3203 82 jeremybenn
     All data structures should be explicitly initialized.  In
3204
     particular code should not rely on static data structures being
3205
     initialized to zero.
3206 19 jeremybenn
 
3207
     The rationale is that in future static data structures may become
3208 82 jeremybenn
     dynamic.  This has been a particular source of bugs in Or1ksim
3209 19 jeremybenn
     historically.
3210
 
3211
     A specific case is with new peripherals, which should always
3212
     include a `start' function to pre-initialize all configuration
3213
     parameters to sensible defaults
3214
 
3215
_Configuration Validation_
3216
     All configuration values should be validated, preferably when
3217
     encountered, if not when the `section' is closed, or otherwise at
3218
     run time when the parameter is first used.
3219
 
3220
 
3221

3222
File: or1ksim.info,  Node: Global Data Structures,  Next: Concepts,  Prev: Coding Conventions,  Up: Code Internals
3223
 
3224
6.2 Global Data Structures
3225
==========================
3226
 
3227
`config'
3228
     The global variable `config' of type `struct config' holds the
3229
     configuration data for some of the Or1ksim components which are
3230 82 jeremybenn
     always present.  At present the components are:
3231 19 jeremybenn
 
3232
        * The simulator defined in `section sim' (*note Simulator
3233
          Configuration: Simulator Configuration.).
3234
 
3235
        * The Verification API (VAPI) defined  in `section vapi' (*note
3236
          Verification API (VAPI) Configuration: Verification API
3237
          Configuration.).
3238
 
3239
        * The Custom Unit Compiler (CUC), defined in `section cuc'
3240
          (*note Custom Unit Compiler (CUC) Configuration: CUC
3241
          Configuration.).
3242
 
3243
        * The CPU, defined in `section cpu' (*note CPU Configuration:
3244
          CPU Configuration.).
3245
 
3246
        * The data cache (but not the instruction cache), defined in
3247
          `section dc' (*note Cache Configuration: Cache
3248
          Configuration.).
3249
 
3250
        * The power management unit, defined in `section pm' (*note
3251
          Power Management Configuration: Power Management
3252
          Configuration.).
3253
 
3254
        * The programmable interrupt controller, defined in
3255
          `section pic' (*note Interrupt Configuration: Interrupt
3256
          Configuration.).
3257
 
3258
        * Branch prediciton, defined in `section bpb' (*note Branch
3259
          Prediction Configuration: Branch Prediction Configuration.).
3260
 
3261
        * The debug unit, defined in `section debug' (*note Debug
3262
          Interface Configuration: Debug Interface Configuration.).
3263
 
3264
 
3265
     This struct is made of a collection of structs, one for each
3266 82 jeremybenn
     component.  For example the simulator configuration is held in
3267 19 jeremybenn
     `config.sim'.
3268
 
3269
`config'
3270
     This is a linked list of data structures holding configuration data
3271
     for all sections which are not held in the main `config' data
3272 82 jeremybenn
     structure.  In general these are components (such as peripherals
3273
     and memory) which may occur multiple times.  However it also
3274
     handles some architectural components which may occur only once,
3275
     such as the memory management units, the instruction cache, the
3276
     interrupt controller and branch prediction.
3277 19 jeremybenn
 
3278
`runtime'
3279
     The global variable `runtime' of type `struct runtime' holds all
3280 82 jeremybenn
     the runtime information about the simulation.  To access this
3281 19 jeremybenn
     variable, `sim-config.h' must be included.
3282
 
3283
     This struct is itself made of 3 other structs, `cpu' (for CPU run
3284
     time state), `vapi' (for Verification API state) and `cuc' (for
3285
     Custom Unit Compiler state).
3286
 
3287
 
3288

3289
File: or1ksim.info,  Node: Concepts,  Next: Internal Debugging,  Prev: Global Data Structures,  Up: Code Internals
3290
 
3291
6.3 Concepts
3292
============
3293
 
3294
_Output Redirection_
3295 82 jeremybenn
     The current output stream is held in `runtime.cpu.fout'.  Output
3296 19 jeremybenn
     should be explicitly written to this stream, or may use the
3297
     `PRINTF' macro, which will write its arguments to this output
3298
     stream.
3299
 
3300
_Reset Hooks_
3301
     Any peripheral may register a routine to be called when the the
3302
     processor is reset by calling `reg_sim_reset', providing a
3303 82 jeremybenn
     function and pointer to a data structure as arguments.  On reset
3304 19 jeremybenn
     that function will be called with the data stucture pointer as
3305
     argument.
3306
 
3307 432 jeremybenn
_Interrupts_
3308
     An internal peripheral can model the effect of an interrupt being
3309
     asserted by calling `report_interrupt'.  This is used for both edge
3310
     and level sensitive interrupts.
3311 19 jeremybenn
 
3312 432 jeremybenn
     The effect is to set the corresponding bit in the PICSR SPR and to
3313
     queue an interrupt exception to take place after the current
3314
     instruction completes execution.
3315
 
3316
     Externally, the different interrupts require different mechanisms
3317
     for clearing.  Level sensitive interrupts should be cleared by
3318
     deasserting the interrupt line, edge sensitive interrupts by
3319
     clearing the corresponding bit in the PICSR SPR.
3320
 
3321
     Internally this amounts to the same thing (clearing the PICSPR
3322
     bit), so a single function is provided, `clear_interrupt'.  Note
3323
     however that when level sensitive interrupts are configured, PICSR
3324
     is read only, and can only be cleared by calling
3325
     `clear_interrupt'.  Using the two functions provided will ensure
3326
     the peripheral works correctly whichever type of interrupt is used.
3327
 
3328
          Note: Until an interrupt is cleared, all subsequent
3329
          interrupts are ignored with a warning.
3330
 
3331
 
3332 19 jeremybenn

3333 104 jeremybenn
File: or1ksim.info,  Node: Internal Debugging,  Next: Regression Testing,  Prev: Concepts,  Up: Code Internals
3334 19 jeremybenn
 
3335
6.4 Internal Debugging
3336
======================
3337
 
3338
The function `debug' is like `printf', but with an extra first
3339 82 jeremybenn
argument, which is the debug level.  If the debug level specified in
3340
the simulator configuration (*note Simulator Behavior: Simulator
3341
Behavior.) is greater than or equal to this value, the remaining
3342
arguments are printed to the current output stream (*note Output
3343
Redirection: Output Redirection.).
3344 19 jeremybenn
 
3345

3346 104 jeremybenn
File: or1ksim.info,  Node: Regression Testing,  Prev: Internal Debugging,  Up: Code Internals
3347
 
3348
6.5 Regression Testing
3349
======================
3350
 
3351
Or1ksim now includes a regression test suite for both standalone and
3352
library usage as described earlier (*note Building and Installing:
3353
Build and Install.).  Running the tests requires that the OpenRISC
3354
toolchain and DejaGNU are both installed.
3355
 
3356
Tests are written using `expect', a derivative of TCL.  Documentation
3357
of DejaGnu, `expect' and TCL are freely available on the Web.  The
3358
Embecosm Application Note 8, `Howto: Using DejaGnu for Testing: A
3359
Simple Introduction' (`http://www.embecosm.com/download/ean8.html')
3360
provides a concise introduction.
3361
 
3362
All test code is found in the `testsuite' directory.  The key files and
3363
directories used are as follows.
3364
 
3365
`global-conf.exp'
3366
     This is the global DejaGNU configuration file used to set up
3367
     parameters common to all tests.  If the user has the environment
3368
     varialbe `DEJAGNU' defined, it will be used instead, but this is
3369
     not recommended.
3370
 
3371
`Makefile.am'
3372
     This is the top level `automake' file for the testsuite.  The only
3373
     changes likely to be needed here is additional local cleanup of
3374
     files created by new tests.
3375
 
3376
`README'
3377
     This contains details of all the tests
3378
 
3379
`config'
3380
     This contains DejaGnu board configurations.  Since the tests are
3381
     generally run on a Unix host, this should just contain `Unix.exp'.
3382
 
3383
`lib'
3384
     This contains DejaGnu tool specific configurations.  "Tool" has a
3385
     specific meaning in DejaGNU, referring just to a grouping of
3386
     tests.  In this case there are two such "tools", "or1ksim" and
3387
     "libsim" for tests of the standalone tool and tests of the library.
3388
 
3389
     Corresponding to this, there are two tool specific configuration
3390
     files, `or1ksim.exp' and `libsim.exp'.  These contain `expect'/TCL
3391
     procedures for common use among the tests.
3392
 
3393
`libsim.tests'
3394
`or1ksim.tests'
3395
     These are the directories of tests of the Or1ksim library.  They
3396
     also include Or1ksim configuration files and each has a
3397
     `Makefile.am' file.  `Makefile.am' should be updated whenever
3398
     files are added to this directory, to ensure they are included in
3399
     the distribution.
3400
 
3401
`test-code'
3402
     These are all the test programs to be compiled on the host (each
3403
     in its own directory).  In general these are programs to support
3404
     testing of the library, and build various programs linking in the
3405
     library.
3406
 
3407
`test-code'
3408
     These are all the test programs to be compiled with the OpenRISC
3409
     tool chain to run with either standalone Or1ksim or the library.
3410
     This directory includes its own `configure.ac', since it must set
3411
     up a separate tool chain based on the target, not the host.
3412
 
3413
 
3414
To add a new test needs the following steps.
3415
 
3416 346 jeremybenn
   * Put new host C code in its own directory within `test-code'.  Add
3417 104 jeremybenn
     the directory to the existing `Makefile.am' in the `test-code'
3418
     directory and create a `Makefile.am' in the new directory to drive
3419 346 jeremybenn
     building the test program(s).  Don't forget to add the new
3420 104 jeremybenn
     `Makefile' to the top level `configure.ac' so it gets generated.
3421
     Not all tests require code here.
3422
 
3423 346 jeremybenn
   * Put new target C code in its own directory within `test-code-or1k'.
3424
     Once again modify & create `Makefile.am'.  This time modify the
3425
     `configure.ac' in the `test-code-or1k' so the `Makefile' gets
3426
     generated.  The existing programs provide examples to start from,
3427
     including custom linker scripts where needed.
3428 104 jeremybenn
 
3429
   * Add one or more tests and configuration files to the relevant
3430 346 jeremybenn
     "tool" test directory.  Use the existing tests as templates.  They
3431 104 jeremybenn
     make heavy use of the `expect'/TCL procedures in the `config'
3432
     directory to facilitate driving the tests.
3433
 
3434
 
3435

3436 19 jeremybenn
File: or1ksim.info,  Node: GNU Free Documentation License,  Next: Index,  Prev: Code Internals,  Up: Top
3437
 
3438
7 GNU Free Documentation License
3439
********************************
3440
 
3441
                      Version 1.2, November 2002
3442
 
3443
     Copyright (C) 2000,2001,2002 Free Software Foundation, Inc.
3444
     51 Franklin St, Fifth Floor, Boston, MA  02110-1301, USA
3445
 
3446
     Everyone is permitted to copy and distribute verbatim copies
3447
     of this license document, but changing it is not allowed.
3448
 
3449
  0. PREAMBLE
3450
 
3451
     The purpose of this License is to make a manual, textbook, or other
3452
     functional and useful document "free" in the sense of freedom: to
3453
     assure everyone the effective freedom to copy and redistribute it,
3454
     with or without modifying it, either commercially or
3455
     noncommercially.  Secondarily, this License preserves for the
3456
     author and publisher a way to get credit for their work, while not
3457
     being considered responsible for modifications made by others.
3458
 
3459
     This License is a kind of "copyleft", which means that derivative
3460
     works of the document must themselves be free in the same sense.
3461
     It complements the GNU General Public License, which is a copyleft
3462
     license designed for free software.
3463
 
3464
     We have designed this License in order to use it for manuals for
3465
     free software, because free software needs free documentation: a
3466
     free program should come with manuals providing the same freedoms
3467
     that the software does.  But this License is not limited to
3468
     software manuals; it can be used for any textual work, regardless
3469
     of subject matter or whether it is published as a printed book.
3470
     We recommend this License principally for works whose purpose is
3471
     instruction or reference.
3472
 
3473
  1. APPLICABILITY AND DEFINITIONS
3474
 
3475
     This License applies to any manual or other work, in any medium,
3476
     that contains a notice placed by the copyright holder saying it
3477
     can be distributed under the terms of this License.  Such a notice
3478
     grants a world-wide, royalty-free license, unlimited in duration,
3479
     to use that work under the conditions stated herein.  The
3480
     "Document", below, refers to any such manual or work.  Any member
3481
     of the public is a licensee, and is addressed as "you".  You
3482
     accept the license if you copy, modify or distribute the work in a
3483
     way requiring permission under copyright law.
3484
 
3485
     A "Modified Version" of the Document means any work containing the
3486
     Document or a portion of it, either copied verbatim, or with
3487
     modifications and/or translated into another language.
3488
 
3489
     A "Secondary Section" is a named appendix or a front-matter section
3490
     of the Document that deals exclusively with the relationship of the
3491
     publishers or authors of the Document to the Document's overall
3492
     subject (or to related matters) and contains nothing that could
3493
     fall directly within that overall subject.  (Thus, if the Document
3494
     is in part a textbook of mathematics, a Secondary Section may not
3495
     explain any mathematics.)  The relationship could be a matter of
3496
     historical connection with the subject or with related matters, or
3497
     of legal, commercial, philosophical, ethical or political position
3498
     regarding them.
3499
 
3500
     The "Invariant Sections" are certain Secondary Sections whose
3501
     titles are designated, as being those of Invariant Sections, in
3502
     the notice that says that the Document is released under this
3503
     License.  If a section does not fit the above definition of
3504
     Secondary then it is not allowed to be designated as Invariant.
3505
     The Document may contain zero Invariant Sections.  If the Document
3506
     does not identify any Invariant Sections then there are none.
3507
 
3508
     The "Cover Texts" are certain short passages of text that are
3509
     listed, as Front-Cover Texts or Back-Cover Texts, in the notice
3510
     that says that the Document is released under this License.  A
3511
     Front-Cover Text may be at most 5 words, and a Back-Cover Text may
3512
     be at most 25 words.
3513
 
3514
     A "Transparent" copy of the Document means a machine-readable copy,
3515
     represented in a format whose specification is available to the
3516
     general public, that is suitable for revising the document
3517
     straightforwardly with generic text editors or (for images
3518
     composed of pixels) generic paint programs or (for drawings) some
3519
     widely available drawing editor, and that is suitable for input to
3520
     text formatters or for automatic translation to a variety of
3521
     formats suitable for input to text formatters.  A copy made in an
3522
     otherwise Transparent file format whose markup, or absence of
3523
     markup, has been arranged to thwart or discourage subsequent
3524
     modification by readers is not Transparent.  An image format is
3525
     not Transparent if used for any substantial amount of text.  A
3526
     copy that is not "Transparent" is called "Opaque".
3527
 
3528
     Examples of suitable formats for Transparent copies include plain
3529
     ASCII without markup, Texinfo input format, LaTeX input format,
3530
     SGML or XML using a publicly available DTD, and
3531
     standard-conforming simple HTML, PostScript or PDF designed for
3532
     human modification.  Examples of transparent image formats include
3533
     PNG, XCF and JPG.  Opaque formats include proprietary formats that
3534
     can be read and edited only by proprietary word processors, SGML or
3535
     XML for which the DTD and/or processing tools are not generally
3536
     available, and the machine-generated HTML, PostScript or PDF
3537
     produced by some word processors for output purposes only.
3538
 
3539
     The "Title Page" means, for a printed book, the title page itself,
3540
     plus such following pages as are needed to hold, legibly, the
3541
     material this License requires to appear in the title page.  For
3542
     works in formats which do not have any title page as such, "Title
3543
     Page" means the text near the most prominent appearance of the
3544
     work's title, preceding the beginning of the body of the text.
3545
 
3546
     A section "Entitled XYZ" means a named subunit of the Document
3547
     whose title either is precisely XYZ or contains XYZ in parentheses
3548
     following text that translates XYZ in another language.  (Here XYZ
3549
     stands for a specific section name mentioned below, such as
3550
     "Acknowledgements", "Dedications", "Endorsements", or "History".)
3551
     To "Preserve the Title" of such a section when you modify the
3552
     Document means that it remains a section "Entitled XYZ" according
3553
     to this definition.
3554
 
3555
     The Document may include Warranty Disclaimers next to the notice
3556
     which states that this License applies to the Document.  These
3557
     Warranty Disclaimers are considered to be included by reference in
3558
     this License, but only as regards disclaiming warranties: any other
3559
     implication that these Warranty Disclaimers may have is void and
3560
     has no effect on the meaning of this License.
3561
 
3562
  2. VERBATIM COPYING
3563
 
3564
     You may copy and distribute the Document in any medium, either
3565
     commercially or noncommercially, provided that this License, the
3566
     copyright notices, and the license notice saying this License
3567
     applies to the Document are reproduced in all copies, and that you
3568
     add no other conditions whatsoever to those of this License.  You
3569
     may not use technical measures to obstruct or control the reading
3570
     or further copying of the copies you make or distribute.  However,
3571
     you may accept compensation in exchange for copies.  If you
3572
     distribute a large enough number of copies you must also follow
3573
     the conditions in section 3.
3574
 
3575
     You may also lend copies, under the same conditions stated above,
3576
     and you may publicly display copies.
3577
 
3578
  3. COPYING IN QUANTITY
3579
 
3580
     If you publish printed copies (or copies in media that commonly
3581
     have printed covers) of the Document, numbering more than 100, and
3582
     the Document's license notice requires Cover Texts, you must
3583
     enclose the copies in covers that carry, clearly and legibly, all
3584
     these Cover Texts: Front-Cover Texts on the front cover, and
3585
     Back-Cover Texts on the back cover.  Both covers must also clearly
3586
     and legibly identify you as the publisher of these copies.  The
3587
     front cover must present the full title with all words of the
3588
     title equally prominent and visible.  You may add other material
3589
     on the covers in addition.  Copying with changes limited to the
3590
     covers, as long as they preserve the title of the Document and
3591
     satisfy these conditions, can be treated as verbatim copying in
3592
     other respects.
3593
 
3594
     If the required texts for either cover are too voluminous to fit
3595
     legibly, you should put the first ones listed (as many as fit
3596
     reasonably) on the actual cover, and continue the rest onto
3597
     adjacent pages.
3598
 
3599
     If you publish or distribute Opaque copies of the Document
3600
     numbering more than 100, you must either include a
3601
     machine-readable Transparent copy along with each Opaque copy, or
3602
     state in or with each Opaque copy a computer-network location from
3603
     which the general network-using public has access to download
3604
     using public-standard network protocols a complete Transparent
3605
     copy of the Document, free of added material.  If you use the
3606
     latter option, you must take reasonably prudent steps, when you
3607
     begin distribution of Opaque copies in quantity, to ensure that
3608
     this Transparent copy will remain thus accessible at the stated
3609
     location until at least one year after the last time you
3610
     distribute an Opaque copy (directly or through your agents or
3611
     retailers) of that edition to the public.
3612
 
3613
     It is requested, but not required, that you contact the authors of
3614
     the Document well before redistributing any large number of
3615
     copies, to give them a chance to provide you with an updated
3616
     version of the Document.
3617
 
3618
  4. MODIFICATIONS
3619
 
3620
     You may copy and distribute a Modified Version of the Document
3621
     under the conditions of sections 2 and 3 above, provided that you
3622
     release the Modified Version under precisely this License, with
3623
     the Modified Version filling the role of the Document, thus
3624
     licensing distribution and modification of the Modified Version to
3625
     whoever possesses a copy of it.  In addition, you must do these
3626
     things in the Modified Version:
3627
 
3628
       A. Use in the Title Page (and on the covers, if any) a title
3629
          distinct from that of the Document, and from those of
3630
          previous versions (which should, if there were any, be listed
3631
          in the History section of the Document).  You may use the
3632
          same title as a previous version if the original publisher of
3633
          that version gives permission.
3634
 
3635
       B. List on the Title Page, as authors, one or more persons or
3636
          entities responsible for authorship of the modifications in
3637
          the Modified Version, together with at least five of the
3638
          principal authors of the Document (all of its principal
3639
          authors, if it has fewer than five), unless they release you
3640
          from this requirement.
3641
 
3642
       C. State on the Title page the name of the publisher of the
3643
          Modified Version, as the publisher.
3644
 
3645
       D. Preserve all the copyright notices of the Document.
3646
 
3647
       E. Add an appropriate copyright notice for your modifications
3648
          adjacent to the other copyright notices.
3649
 
3650
       F. Include, immediately after the copyright notices, a license
3651
          notice giving the public permission to use the Modified
3652
          Version under the terms of this License, in the form shown in
3653
          the Addendum below.
3654
 
3655
       G. Preserve in that license notice the full lists of Invariant
3656
          Sections and required Cover Texts given in the Document's
3657
          license notice.
3658
 
3659
       H. Include an unaltered copy of this License.
3660
 
3661
       I. Preserve the section Entitled "History", Preserve its Title,
3662
          and add to it an item stating at least the title, year, new
3663
          authors, and publisher of the Modified Version as given on
3664
          the Title Page.  If there is no section Entitled "History" in
3665
          the Document, create one stating the title, year, authors,
3666
          and publisher of the Document as given on its Title Page,
3667
          then add an item describing the Modified Version as stated in
3668
          the previous sentence.
3669
 
3670
       J. Preserve the network location, if any, given in the Document
3671
          for public access to a Transparent copy of the Document, and
3672
          likewise the network locations given in the Document for
3673
          previous versions it was based on.  These may be placed in
3674
          the "History" section.  You may omit a network location for a
3675
          work that was published at least four years before the
3676
          Document itself, or if the original publisher of the version
3677
          it refers to gives permission.
3678
 
3679
       K. For any section Entitled "Acknowledgements" or "Dedications",
3680
          Preserve the Title of the section, and preserve in the
3681
          section all the substance and tone of each of the contributor
3682
          acknowledgements and/or dedications given therein.
3683
 
3684
       L. Preserve all the Invariant Sections of the Document,
3685
          unaltered in their text and in their titles.  Section numbers
3686
          or the equivalent are not considered part of the section
3687
          titles.
3688
 
3689
       M. Delete any section Entitled "Endorsements".  Such a section
3690
          may not be included in the Modified Version.
3691
 
3692
       N. Do not retitle any existing section to be Entitled
3693
          "Endorsements" or to conflict in title with any Invariant
3694
          Section.
3695
 
3696
       O. Preserve any Warranty Disclaimers.
3697
 
3698
     If the Modified Version includes new front-matter sections or
3699
     appendices that qualify as Secondary Sections and contain no
3700
     material copied from the Document, you may at your option
3701
     designate some or all of these sections as invariant.  To do this,
3702
     add their titles to the list of Invariant Sections in the Modified
3703
     Version's license notice.  These titles must be distinct from any
3704
     other section titles.
3705
 
3706
     You may add a section Entitled "Endorsements", provided it contains
3707
     nothing but endorsements of your Modified Version by various
3708
     parties--for example, statements of peer review or that the text
3709
     has been approved by an organization as the authoritative
3710
     definition of a standard.
3711
 
3712
     You may add a passage of up to five words as a Front-Cover Text,
3713
     and a passage of up to 25 words as a Back-Cover Text, to the end
3714
     of the list of Cover Texts in the Modified Version.  Only one
3715
     passage of Front-Cover Text and one of Back-Cover Text may be
3716
     added by (or through arrangements made by) any one entity.  If the
3717
     Document already includes a cover text for the same cover,
3718
     previously added by you or by arrangement made by the same entity
3719
     you are acting on behalf of, you may not add another; but you may
3720
     replace the old one, on explicit permission from the previous
3721
     publisher that added the old one.
3722
 
3723
     The author(s) and publisher(s) of the Document do not by this
3724
     License give permission to use their names for publicity for or to
3725
     assert or imply endorsement of any Modified Version.
3726
 
3727
  5. COMBINING DOCUMENTS
3728
 
3729
     You may combine the Document with other documents released under
3730
     this License, under the terms defined in section 4 above for
3731
     modified versions, provided that you include in the combination
3732
     all of the Invariant Sections of all of the original documents,
3733
     unmodified, and list them all as Invariant Sections of your
3734
     combined work in its license notice, and that you preserve all
3735
     their Warranty Disclaimers.
3736
 
3737
     The combined work need only contain one copy of this License, and
3738
     multiple identical Invariant Sections may be replaced with a single
3739
     copy.  If there are multiple Invariant Sections with the same name
3740
     but different contents, make the title of each such section unique
3741
     by adding at the end of it, in parentheses, the name of the
3742
     original author or publisher of that section if known, or else a
3743
     unique number.  Make the same adjustment to the section titles in
3744
     the list of Invariant Sections in the license notice of the
3745
     combined work.
3746
 
3747
     In the combination, you must combine any sections Entitled
3748
     "History" in the various original documents, forming one section
3749
     Entitled "History"; likewise combine any sections Entitled
3750
     "Acknowledgements", and any sections Entitled "Dedications".  You
3751
     must delete all sections Entitled "Endorsements."
3752
 
3753
  6. COLLECTIONS OF DOCUMENTS
3754
 
3755
     You may make a collection consisting of the Document and other
3756
     documents released under this License, and replace the individual
3757
     copies of this License in the various documents with a single copy
3758
     that is included in the collection, provided that you follow the
3759
     rules of this License for verbatim copying of each of the
3760
     documents in all other respects.
3761
 
3762
     You may extract a single document from such a collection, and
3763
     distribute it individually under this License, provided you insert
3764
     a copy of this License into the extracted document, and follow
3765
     this License in all other respects regarding verbatim copying of
3766
     that document.
3767
 
3768
  7. AGGREGATION WITH INDEPENDENT WORKS
3769
 
3770
     A compilation of the Document or its derivatives with other
3771
     separate and independent documents or works, in or on a volume of
3772
     a storage or distribution medium, is called an "aggregate" if the
3773
     copyright resulting from the compilation is not used to limit the
3774
     legal rights of the compilation's users beyond what the individual
3775
     works permit.  When the Document is included in an aggregate, this
3776
     License does not apply to the other works in the aggregate which
3777
     are not themselves derivative works of the Document.
3778
 
3779
     If the Cover Text requirement of section 3 is applicable to these
3780
     copies of the Document, then if the Document is less than one half
3781
     of the entire aggregate, the Document's Cover Texts may be placed
3782
     on covers that bracket the Document within the aggregate, or the
3783
     electronic equivalent of covers if the Document is in electronic
3784
     form.  Otherwise they must appear on printed covers that bracket
3785
     the whole aggregate.
3786
 
3787
  8. TRANSLATION
3788
 
3789
     Translation is considered a kind of modification, so you may
3790
     distribute translations of the Document under the terms of section
3791
     4.  Replacing Invariant Sections with translations requires special
3792
     permission from their copyright holders, but you may include
3793
     translations of some or all Invariant Sections in addition to the
3794
     original versions of these Invariant Sections.  You may include a
3795
     translation of this License, and all the license notices in the
3796
     Document, and any Warranty Disclaimers, provided that you also
3797
     include the original English version of this License and the
3798
     original versions of those notices and disclaimers.  In case of a
3799
     disagreement between the translation and the original version of
3800
     this License or a notice or disclaimer, the original version will
3801
     prevail.
3802
 
3803
     If a section in the Document is Entitled "Acknowledgements",
3804
     "Dedications", or "History", the requirement (section 4) to
3805
     Preserve its Title (section 1) will typically require changing the
3806
     actual title.
3807
 
3808
  9. TERMINATION
3809
 
3810
     You may not copy, modify, sublicense, or distribute the Document
3811
     except as expressly provided for under this License.  Any other
3812
     attempt to copy, modify, sublicense or distribute the Document is
3813
     void, and will automatically terminate your rights under this
3814
     License.  However, parties who have received copies, or rights,
3815
     from you under this License will not have their licenses
3816
     terminated so long as such parties remain in full compliance.
3817
 
3818
 10. FUTURE REVISIONS OF THIS LICENSE
3819
 
3820
     The Free Software Foundation may publish new, revised versions of
3821
     the GNU Free Documentation License from time to time.  Such new
3822
     versions will be similar in spirit to the present version, but may
3823
     differ in detail to address new problems or concerns.  See
3824
     `http://www.gnu.org/copyleft/'.
3825
 
3826
     Each version of the License is given a distinguishing version
3827
     number.  If the Document specifies that a particular numbered
3828
     version of this License "or any later version" applies to it, you
3829
     have the option of following the terms and conditions either of
3830
     that specified version or of any later version that has been
3831
     published (not as a draft) by the Free Software Foundation.  If
3832
     the Document does not specify a version number of this License,
3833
     you may choose any version ever published (not as a draft) by the
3834
     Free Software Foundation.
3835
 
3836
ADDENDUM: How to use this License for your documents
3837
====================================================
3838
 
3839
To use this License in a document you have written, include a copy of
3840
the License in the document and put the following copyright and license
3841
notices just after the title page:
3842
 
3843
       Copyright (C)  YEAR  YOUR NAME.
3844
       Permission is granted to copy, distribute and/or modify this document
3845
       under the terms of the GNU Free Documentation License, Version 1.2
3846
       or any later version published by the Free Software Foundation;
3847
       with no Invariant Sections, no Front-Cover Texts, and no Back-Cover
3848
       Texts.  A copy of the license is included in the section entitled ``GNU
3849
       Free Documentation License''.
3850
 
3851
If you have Invariant Sections, Front-Cover Texts and Back-Cover Texts,
3852
replace the "with...Texts." line with this:
3853
 
3854
         with the Invariant Sections being LIST THEIR TITLES, with
3855
         the Front-Cover Texts being LIST, and with the Back-Cover Texts
3856
         being LIST.
3857
 
3858
If you have Invariant Sections without Cover Texts, or some other
3859
combination of the three, merge those two alternatives to suit the
3860
situation.
3861
 
3862
If your document contains nontrivial examples of program code, we
3863
recommend releasing these examples in parallel under your choice of
3864
free software license, such as the GNU General Public License, to
3865
permit their use in free software.
3866
 
3867

3868
File: or1ksim.info,  Node: Index,  Prev: GNU Free Documentation License,  Up: Top
3869
 
3870
Index
3871
*****
3872
 
3873
 
3874
* Menu:
3875
3876
* --cumulative:                          Profiling Utility.   (line  26)
3877
* --debug-config:                        Standalone Simulator.
3878 472 jeremybenn
                                                              (line  99)
3879 82 jeremybenn
* --disable-all-tests:                   Configuring the Build.
3880 127 jeremybenn
                                                              (line 105)
3881 19 jeremybenn
* --disable-arith-flag:                  Configuring the Build.
3882 127 jeremybenn
                                                              (line 118)
3883 124 jeremybenn
* --disable-debug:                       Configuring the Build.
3884 127 jeremybenn
                                                              (line  98)
3885 19 jeremybenn
* --disable-ethphy:                      Configuring the Build.
3886 104 jeremybenn
                                                              (line  59)
3887 19 jeremybenn
* --disable-ov-flag:                     Configuring the Build.
3888 127 jeremybenn
                                                              (line 133)
3889 19 jeremybenn
* --disable-profiling:                   Configuring the Build.
3890 104 jeremybenn
                                                              (line  30)
3891 19 jeremybenn
* --disable-range-stats:                 Configuring the Build.
3892 127 jeremybenn
                                                              (line  92)
3893
* --disable-unsigned-xori:               Configuring the Build.
3894 104 jeremybenn
                                                              (line  69)
3895 82 jeremybenn
* --enable-all-tests:                    Configuring the Build.
3896 127 jeremybenn
                                                              (line 104)
3897 19 jeremybenn
* --enable-arith-flag:                   Configuring the Build.
3898 127 jeremybenn
                                                              (line 117)
3899 124 jeremybenn
* --enable-debug:                        Configuring the Build.
3900 127 jeremybenn
                                                              (line  97)
3901 19 jeremybenn
* --enable-ethphy:                       Configuring the Build.
3902 104 jeremybenn
                                                              (line  58)
3903 19 jeremybenn
* --enable-execution:                    Configuring the Build.
3904 104 jeremybenn
                                                              (line  37)
3905 19 jeremybenn
* --enable-mprofile:                     Standalone Simulator.
3906 472 jeremybenn
                                                              (line 133)
3907 19 jeremybenn
* --enable-ov-flag:                      Configuring the Build.
3908 127 jeremybenn
                                                              (line 132)
3909 19 jeremybenn
* --enable-profile:                      Standalone Simulator.
3910 472 jeremybenn
                                                              (line 130)
3911 19 jeremybenn
* --enable-profiling:                    Configuring the Build.
3912 104 jeremybenn
                                                              (line  29)
3913 19 jeremybenn
* --enable-range-stats:                  Configuring the Build.
3914 127 jeremybenn
                                                              (line  91)
3915
* --enable-unsigned-xori:                Configuring the Build.
3916 104 jeremybenn
                                                              (line  68)
3917 19 jeremybenn
* --file:                                Standalone Simulator.
3918 472 jeremybenn
                                                              (line  57)
3919 19 jeremybenn
* --filename:                            Memory Profiling Utility.
3920
                                                              (line  51)
3921
* --generate:                            Profiling Utility.   (line  34)
3922
* --group:                               Memory Profiling Utility.
3923
                                                              (line  47)
3924
* --help:                                Standalone Simulator.
3925 346 jeremybenn
                                                              (line  21)
3926 19 jeremybenn
* --help (memory profiling utility):     Memory Profiling Utility.
3927
                                                              (line  22)
3928
* --help (profiling utility):            Profiling Utility.   (line  22)
3929
* --interactive:                         Standalone Simulator.
3930 346 jeremybenn
                                                              (line  25)
3931
* --memory:                              Standalone Simulator.
3932 472 jeremybenn
                                                              (line  83)
3933 19 jeremybenn
* --mode:                                Memory Profiling Utility.
3934
                                                              (line  26)
3935
* --nosrv:                               Standalone Simulator.
3936 472 jeremybenn
                                                              (line  65)
3937 346 jeremybenn
* --quiet <1>:                           Profiling Utility.   (line  30)
3938
* --quiet:                               Standalone Simulator.
3939
                                                              (line  29)
3940
* --report-memory-errors:                Standalone Simulator.
3941 472 jeremybenn
                                                              (line 104)
3942 19 jeremybenn
* --srv:                                 Standalone Simulator.
3943 472 jeremybenn
                                                              (line  73)
3944 19 jeremybenn
* --strict-npc:                          Standalone Simulator.
3945 472 jeremybenn
                                                              (line 113)
3946
* --trace <1>:                           Trace Generation.    (line  14)
3947 420 jeremybenn
* --trace:                               Standalone Simulator.
3948
                                                              (line  39)
3949 472 jeremybenn
* --trace-physical <1>:                  Trace Generation.    (line  44)
3950
* --trace-physical:                      Standalone Simulator.
3951
                                                              (line  44)
3952
* --trace-virtual <1>:                   Trace Generation.    (line  44)
3953
* --trace-virtual:                       Standalone Simulator.
3954
                                                              (line  44)
3955 346 jeremybenn
* --verbose:                             Standalone Simulator.
3956
                                                              (line  33)
3957 19 jeremybenn
* --version:                             Standalone Simulator.
3958 346 jeremybenn
                                                              (line  17)
3959 19 jeremybenn
* --version (memory profiling utility):  Memory Profiling Utility.
3960
                                                              (line  17)
3961
* --version (profiling utility):         Profiling Utility.   (line  17)
3962
* -c:                                    Profiling Utility.   (line  26)
3963
* -d:                                    Standalone Simulator.
3964 472 jeremybenn
                                                              (line  99)
3965 19 jeremybenn
* -f <1>:                                Memory Profiling Utility.
3966
                                                              (line  51)
3967
* -f:                                    Standalone Simulator.
3968 472 jeremybenn
                                                              (line  57)
3969 346 jeremybenn
* -g <1>:                                Memory Profiling Utility.
3970 19 jeremybenn
                                                              (line  47)
3971 346 jeremybenn
* -g:                                    Profiling Utility.   (line  34)
3972 19 jeremybenn
* -h:                                    Standalone Simulator.
3973 346 jeremybenn
                                                              (line  21)
3974 19 jeremybenn
* -h (memory profiling utility):         Memory Profiling Utility.
3975
                                                              (line  22)
3976
* -h (profiling utility):                Profiling Utility.   (line  22)
3977
* -i:                                    Standalone Simulator.
3978 346 jeremybenn
                                                              (line  25)
3979
* -m <1>:                                Memory Profiling Utility.
3980 19 jeremybenn
                                                              (line  26)
3981 346 jeremybenn
* -m:                                    Standalone Simulator.
3982 472 jeremybenn
                                                              (line  83)
3983 346 jeremybenn
* -q <1>:                                Profiling Utility.   (line  30)
3984
* -q:                                    Standalone Simulator.
3985
                                                              (line  29)
3986 472 jeremybenn
* -t <1>:                                Trace Generation.    (line  14)
3987 420 jeremybenn
* -t:                                    Standalone Simulator.
3988
                                                              (line  39)
3989 346 jeremybenn
* -V:                                    Standalone Simulator.
3990
                                                              (line  33)
3991 19 jeremybenn
* -v:                                    Standalone Simulator.
3992 346 jeremybenn
                                                              (line  17)
3993 19 jeremybenn
* -v (memory profiling utility):         Memory Profiling Utility.
3994
                                                              (line  17)
3995
* -v (profiling utility):                Profiling Utility.   (line  17)
3996
* 0x00 UART VAPI sub-command (UART verification): Verification API.
3997
                                                              (line  49)
3998
* 0x01 UART VAPI sub-command (UART verification): Verification API.
3999
                                                              (line  55)
4000
* 0x02 UART VAPI sub-command (UART verification): Verification API.
4001
                                                              (line  59)
4002
* 0x03 UART VAPI sub-command (UART verification): Verification API.
4003
                                                              (line  62)
4004
* 0x04 UART VAPI sub-command (UART verification): Verification API.
4005
                                                              (line  66)
4006
* 16550 (UART configuration):            UART Configuration.  (line  73)
4007 82 jeremybenn
* all tests enabled:                     Configuring the Build.
4008 127 jeremybenn
                                                              (line 105)
4009 19 jeremybenn
* Argtable2 debugging:                   Configuring the Build.
4010 127 jeremybenn
                                                              (line  98)
4011 19 jeremybenn
* ATA/ATAPI configuration:               Disc Interface Configuration.
4012
                                                              (line   6)
4013
* ATA/ATAPI device configuration:        Disc Interface Configuration.
4014 385 jeremybenn
                                                              (line  92)
4015 19 jeremybenn
* base_vapi_id (GPIO configuration - deprecated): GPIO Configuration.
4016
                                                              (line  32)
4017
* baseaddr (ATA/ATAPI configuration):    Disc Interface Configuration.
4018 385 jeremybenn
                                                              (line  26)
4019 19 jeremybenn
* baseaddr (DMA configuration):          DMA Configuration.   (line  24)
4020
* baseaddr (Ethernet configuration):     Ethernet Configuration.
4021 440 jeremybenn
                                                              (line  23)
4022 19 jeremybenn
* baseaddr (frame buffer configuration): Frame Buffer Configuration.
4023
                                                              (line  20)
4024
* baseaddr (generic peripheral configuration): Generic Peripheral Configuration.
4025
                                                              (line  22)
4026
* baseaddr (GPIO configuration):         GPIO Configuration.  (line  21)
4027
* baseaddr (keyboard configuration):     Keyboard Configuration.
4028
                                                              (line  36)
4029
* baseaddr (memory configuration):       Memory Configuration.
4030 418 julius
                                                              (line  94)
4031 19 jeremybenn
* baseaddr (memory controller configuration): Memory Controller Configuration.
4032 385 jeremybenn
                                                              (line  55)
4033 19 jeremybenn
* baseaddr (UART configuration):         UART Configuration.  (line  22)
4034
* baseaddr (VGA configuration):          Display Interface Configuration.
4035
                                                              (line  26)
4036
* blocksize (cache configuration):       Cache Configuration. (line  29)
4037
* BPB configuration:                     Branch Prediction Configuration.
4038
                                                              (line   6)
4039
* branch prediction configuration:       Branch Prediction Configuration.
4040
                                                              (line   6)
4041
* break (Interactive CLI):               Interactive Command Line.
4042
                                                              (line  57)
4043
* breakpoint list (Interactive CLI):     Interactive Command Line.
4044
                                                              (line  60)
4045
* breakpoint set/clear (Interactive CLI): Interactive Command Line.
4046
                                                              (line  57)
4047
* breaks (Interactive CLI):              Interactive Command Line.
4048
                                                              (line  60)
4049 440 jeremybenn
* bridge setup:                          Establishing a Bridge.
4050
                                                              (line   6)
4051 19 jeremybenn
* btic (branch prediction configuration): Branch Prediction Configuration.
4052
                                                              (line  19)
4053 440 jeremybenn
* BusyBox and Ethernet:                  Networking from OpenRISC Linux and BusyBox.
4054
                                                              (line   6)
4055 19 jeremybenn
* byte_enabled (generic peripheral configuration): Generic Peripheral Configuration.
4056
                                                              (line  48)
4057
* cache configuration:                   Cache Configuration. (line   6)
4058 346 jeremybenn
* calling_convention (CUC configuration): CUC Configuration.  (line  37)
4059 19 jeremybenn
* ce (memory configuration):             Memory Configuration.
4060 418 julius
                                                              (line 124)
4061 19 jeremybenn
* cfgr (CPU configuration):              CPU Configuration.   (line  47)
4062
* channel (UART configuration):          UART Configuration.  (line  29)
4063
* clear breakpoint (Interactive CLI):    Interactive Command Line.
4064
                                                              (line  57)
4065 432 jeremybenn
* clear_interrupt:                       Concepts.            (line  20)
4066 202 julius
* clkcycle (simulator configuration):    Simulator Behavior.  (line 115)
4067 19 jeremybenn
* cm (Interactive CLI):                  Interactive Command Line.
4068
                                                              (line  54)
4069
* command line for Or1ksim standalone use: Standalone Simulator.
4070
                                                              (line   6)
4071
* complex model:                         Configuring the Build.
4072 104 jeremybenn
                                                              (line  37)
4073 19 jeremybenn
* config:                                Global Data Structures.
4074
                                                              (line   7)
4075
* config.bpb:                            Global Data Structures.
4076
                                                              (line  37)
4077
* config.cpu:                            Global Data Structures.
4078
                                                              (line  22)
4079
* config.cuc:                            Global Data Structures.
4080
                                                              (line  18)
4081
* config.dc:                             Global Data Structures.
4082
                                                              (line  25)
4083
* config.debug:                          Global Data Structures.
4084
                                                              (line  40)
4085
* config.pic:                            Global Data Structures.
4086
                                                              (line  33)
4087
* config.pm:                             Global Data Structures.
4088
                                                              (line  29)
4089
* config.sim:                            Global Data Structures.
4090
                                                              (line  11)
4091
* config.vapi:                           Global Data Structures.
4092
                                                              (line  14)
4093
* configuration dynamic structure:       Global Data Structures.
4094
                                                              (line  49)
4095
* configuration file structure:          Configuration File Format.
4096
                                                              (line   6)
4097
* configuration global structure:        Global Data Structures.
4098
                                                              (line   7)
4099
* configuration info (Interactive CLI):  Interactive Command Line.
4100
                                                              (line 119)
4101
* configuration of generic peripherals:  Generic Peripheral Configuration.
4102
                                                              (line   6)
4103
* configuration parameter setting (Interactive CLI): Interactive Command Line.
4104
                                                              (line 146)
4105
* configuring branch prediction:         Branch Prediction Configuration.
4106
                                                              (line   6)
4107
* configuring data & instruction caches: Cache Configuration. (line   6)
4108
* configuring data & instruction MMUs:   Memory Management Configuration.
4109
                                                              (line   6)
4110
* configuring DMA:                       DMA Configuration.   (line   6)
4111
* configuring memory:                    Memory Configuration.
4112
                                                              (line   6)
4113
* configuring Or1ksim:                   Configuration.       (line   6)
4114
* configuring power management:          Power Management Configuration.
4115
                                                              (line   6)
4116
* configuring the ATA/ATAPI interfaces:  Disc Interface Configuration.
4117
                                                              (line   6)
4118
* configuring the behavior of Or1ksim:   Simulator Behavior.  (line   6)
4119
* configuring the CPU:                   CPU Configuration.   (line   6)
4120
* configuring the Custom Unit Compiler (CUC): CUC Configuration.
4121
                                                              (line   6)
4122
* configuring the debug unit and interface to external debuggers: Debug Interface Configuration.
4123
                                                              (line   6)
4124
* configuring the Ethernet interface:    Ethernet Configuration.
4125
                                                              (line   6)
4126 440 jeremybenn
* configuring the Ethernet TUN/TAP interface: Ethernet TUN/TAP Interface.
4127
                                                              (line   6)
4128 19 jeremybenn
* configuring the frame buffer:          Frame Buffer Configuration.
4129
                                                              (line   6)
4130
* configuring the GPIO:                  GPIO Configuration.  (line   6)
4131
* configuring the interrupt controller:  Interrupt Configuration.
4132
                                                              (line   6)
4133
* configuring the keyboard interface:    Keyboard Configuration.
4134
                                                              (line   6)
4135
* configuring the memory controller:     Memory Controller Configuration.
4136
                                                              (line   6)
4137
* configuring the processor:             CPU Configuration.   (line   6)
4138
* configuring the PS2 interface:         Keyboard Configuration.
4139
                                                              (line   6)
4140
* configuring the UART:                  UART Configuration.  (line   6)
4141
* configuring the Verification API (VAPI): Verification API Configuration.
4142
                                                              (line   6)
4143
* configuring the VGA interface:         Display Interface Configuration.
4144
                                                              (line   6)
4145
* copying memory (Interactive CLI):      Interactive Command Line.
4146
                                                              (line  54)
4147
* CPU configuration:                     CPU Configuration.   (line   6)
4148
* CUC configuration:                     CUC Configuration.   (line   6)
4149
* Custom Unit Compiler (Interactive CLI): Interactive Command Line.
4150
                                                              (line 162)
4151
* Custom Unit Compiler Configuration:    CUC Configuration.   (line   6)
4152
* data cache configuration:              Cache Configuration. (line   6)
4153
* data MMU configuration:                Memory Management Configuration.
4154
                                                              (line   6)
4155
* DCGE (power management register):      Power Management Configuration.
4156
                                                              (line  21)
4157
* debug (Interactive CLI):               Interactive Command Line.
4158 346 jeremybenn
                                                              (line 151)
4159 19 jeremybenn
* debug (simulator configuration):       Simulator Behavior.  (line  13)
4160
* debug channel toggle (Interactive CLI): Interactive Command Line.
4161
                                                              (line 141)
4162
* debug interface configuration:         Debug Interface Configuration.
4163
                                                              (line   6)
4164
* debug mode toggle (Interactive CLI):   Interactive Command Line.
4165
                                                              (line 151)
4166
* debug unit configuration:              Debug Interface Configuration.
4167
                                                              (line   6)
4168
* Debug Unit verification (VAPI):        Verification API.    (line  34)
4169
* debugging enabled (Argtable2):         Configuring the Build.
4170 127 jeremybenn
                                                              (line  98)
4171 104 jeremybenn
* DejaGnu board configurations:          Regression Testing.  (line  35)
4172
* DejaGnu configuration:                 Regression Testing.  (line  21)
4173
* DejaGNU tests directories:             Regression Testing.  (line  50)
4174
* DejaGnu tool specific configuration:   Regression Testing.  (line  39)
4175 19 jeremybenn
* delayr (memory configuration):         Memory Configuration.
4176 418 julius
                                                              (line 144)
4177 19 jeremybenn
* delayw (memory configuration):         Memory Configuration.
4178 418 julius
                                                              (line 150)
4179 98 jeremybenn
* dependstats (CPU configuration):       CPU Configuration.   (line  89)
4180 19 jeremybenn
* dev_id (ATA/ATAPI configuration):      Disc Interface Configuration.
4181 385 jeremybenn
                                                              (line  40)
4182 19 jeremybenn
* disassemble (Interactive CLI):         Interactive Command Line.
4183
                                                              (line  41)
4184
* disc interface configuration:          Disc Interface Configuration.
4185
                                                              (line   6)
4186
* disc interface device configuration:   Disc Interface Configuration.
4187 385 jeremybenn
                                                              (line  92)
4188 19 jeremybenn
* display interface configuration:       Display Interface Configuration.
4189
                                                              (line   6)
4190
* displaying memory (Interactive CLI):   Interactive Command Line.
4191
                                                              (line  31)
4192
* displaying registers (Interactive CLI): Interactive Command Line.
4193
                                                              (line  14)
4194
* dm (Interactive CLI):                  Interactive Command Line.
4195
                                                              (line  31)
4196
* dma (Ethernet configuration):          Ethernet Configuration.
4197 440 jeremybenn
                                                              (line  34)
4198 19 jeremybenn
* DMA configuration:                     DMA Configuration.   (line   6)
4199
* DMA verification (VAPI):               Verification API.    (line  73)
4200
* dma_mode0_td (ATA/ATAPI configuration): Disc Interface Configuration.
4201 385 jeremybenn
                                                              (line  74)
4202 19 jeremybenn
* dma_mode0_teoc (ATA/ATAPI configuration): Disc Interface Configuration.
4203 385 jeremybenn
                                                              (line  75)
4204 19 jeremybenn
* dma_mode0_tm (ATA/ATAPI configuration): Disc Interface Configuration.
4205 385 jeremybenn
                                                              (line  73)
4206 19 jeremybenn
* DME (power management register):       Power Management Configuration.
4207
                                                              (line  15)
4208
* DMMU configuration:                    Memory Management Configuration.
4209
                                                              (line   6)
4210
* doze mode (power management register): Power Management Configuration.
4211
                                                              (line  15)
4212 451 jeremybenn
* dummy_crc (Ethernet configuration):    Ethernet Configuration.
4213
                                                              (line 104)
4214 19 jeremybenn
* dv (Interactive CLI):                  Interactive Command Line.
4215
                                                              (line 124)
4216
* dynamic clock gating (power management register): Power Management Configuration.
4217
                                                              (line  21)
4218
* dynamic model:                         Configuring the Build.
4219 104 jeremybenn
                                                              (line  37)
4220 19 jeremybenn
* dynamic ports, use of:                 Verification API Configuration.
4221
                                                              (line  23)
4222
* edge_trigger (interrupt controller):   Interrupt Configuration.
4223
                                                              (line  16)
4224 346 jeremybenn
* enable_bursts (CUC configuration):     CUC Configuration.   (line  41)
4225 19 jeremybenn
* enabled (ATA/ATAPI configuration):     Disc Interface Configuration.
4226 385 jeremybenn
                                                              (line  22)
4227 19 jeremybenn
* enabled (branch prediction configuration): Branch Prediction Configuration.
4228
                                                              (line  15)
4229
* enabled (cache configuration):         Cache Configuration. (line  11)
4230
* enabled (debug interface configuration): Debug Interface Configuration.
4231
                                                              (line  11)
4232
* enabled (DMA configuration):           DMA Configuration.   (line  20)
4233
* enabled (Ethernet configuration):      Ethernet Configuration.
4234 440 jeremybenn
                                                              (line  19)
4235 19 jeremybenn
* enabled (frame buffer configuration):  Frame Buffer Configuration.
4236
                                                              (line  16)
4237
* enabled (generic peripheral configuration): Generic Peripheral Configuration.
4238
                                                              (line  18)
4239
* enabled (GPIO configuration):          GPIO Configuration.  (line  17)
4240
* enabled (interrupt controller):        Interrupt Configuration.
4241
                                                              (line  12)
4242
* enabled (keyboard configuration):      Keyboard Configuration.
4243
                                                              (line  32)
4244
* enabled (memory controller configuration): Memory Controller Configuration.
4245 385 jeremybenn
                                                              (line  44)
4246 19 jeremybenn
* enabled (MMU configuration):           Memory Management Configuration.
4247
                                                              (line  12)
4248
* enabled (power management configuration): Power Management Configuration.
4249
                                                              (line  35)
4250
* enabled (UART configuration):          UART Configuration.  (line  18)
4251
* enabled (verification API configuration): Verification API Configuration.
4252
                                                              (line  15)
4253
* enabled (VGA configuration):           Display Interface Configuration.
4254
                                                              (line  22)
4255
* enabling Ethernet via socket:          Configuring the Build.
4256 104 jeremybenn
                                                              (line  59)
4257 19 jeremybenn
* entrysize (MMU configuration):         Memory Management Configuration.
4258
                                                              (line  32)
4259
* ETH_VAPI_CTRL (Ethernet verification): Verification API.    (line  86)
4260
* ETH_VAPI_DATA (Ethernet verification): Verification API.    (line  84)
4261 440 jeremybenn
* Ethernet bridge setup:                 Establishing a Bridge.
4262
                                                              (line   6)
4263 19 jeremybenn
* Ethernet configuration:                Ethernet Configuration.
4264
                                                              (line   6)
4265
* Ethernet verification (VAPI):          Verification API.    (line  78)
4266
* Ethernet via socket, enabling:         Configuring the Build.
4267 104 jeremybenn
                                                              (line  59)
4268 127 jeremybenn
* exclusive-OR immediate operand:        Configuring the Build.
4269
                                                              (line  69)
4270 202 julius
* exe_bin_insn_log (simulator configuration): Simulator Behavior.
4271
                                                              (line 103)
4272
* exe_bin_insn_log_file (simulator configuration): Simulator Behavior.
4273
                                                              (line 111)
4274 82 jeremybenn
* exe_log (simulator configuration):     Simulator Behavior.  (line  49)
4275
* exe_log_end (simulator configuration): Simulator Behavior.  (line  89)
4276
* exe_log_file (simulator configuration): Simulator Behavior. (line  97)
4277 19 jeremybenn
* exe_log_fn (simulator configuration - deprecated): Simulator Behavior.
4278 82 jeremybenn
                                                              (line  97)
4279 19 jeremybenn
* exe_log_marker (simulator configuration): Simulator Behavior.
4280 82 jeremybenn
                                                              (line  93)
4281 19 jeremybenn
* exe_log_start (simulator configuration): Simulator Behavior.
4282 82 jeremybenn
                                                              (line  86)
4283
* exe_log_type (simulator configuration): Simulator Behavior. (line  55)
4284 19 jeremybenn
* exe_log_type=default (simulator configuration): Simulator Behavior.
4285 82 jeremybenn
                                                              (line  58)
4286 19 jeremybenn
* exe_log_type=hardware (simulator configuration): Simulator Behavior.
4287 82 jeremybenn
                                                              (line  62)
4288 19 jeremybenn
* exe_log_type=simple (simulator configuration): Simulator Behavior.
4289 82 jeremybenn
                                                              (line  69)
4290 19 jeremybenn
* exe_log_type=software (simulator configuration): Simulator Behavior.
4291 82 jeremybenn
                                                              (line  74)
4292 19 jeremybenn
* executing code (Interactive CLI):      Interactive Command Line.
4293
                                                              (line  23)
4294
* execution history (Interactive CLI):   Interactive Command Line.
4295
                                                              (line  67)
4296
* file (ATA/ATAPI device configuration): Disc Interface Configuration.
4297 385 jeremybenn
                                                              (line 108)
4298 19 jeremybenn
* file (keyboard configuration):         Keyboard Configuration.
4299
                                                              (line  51)
4300
* filename (frame buffer configuration - deprecated): Frame Buffer Configuration.
4301 82 jeremybenn
                                                              (line  36)
4302 19 jeremybenn
* filename (VGA configuration - deprecated): Display Interface Configuration.
4303
                                                              (line  47)
4304 440 jeremybenn
* firewall with Ethernet bridge and TAP/TUN: Opening the Firewall.
4305
                                                              (line   6)
4306 19 jeremybenn
* firmware (ATA/ATAPI device configuration): Disc Interface Configuration.
4307 385 jeremybenn
                                                              (line 121)
4308 19 jeremybenn
* flag setting by instructions:          Configuring the Build.
4309 127 jeremybenn
                                                              (line 118)
4310 19 jeremybenn
* frame buffer configuration:            Frame Buffer Configuration.
4311
                                                              (line   6)
4312
* generic peripheral configuration:      Generic Peripheral Configuration.
4313
                                                              (line   6)
4314
* GPIO configuration:                    GPIO Configuration.  (line   6)
4315
* GPIO verification (VAPI):              Verification API.    (line  88)
4316
* GPIO_VAPI_AUX (GPIO verification):     Verification API.    (line 100)
4317
* GPIO_VAPI_CLOCK (GPIO verification):   Verification API.    (line 103)
4318
* GPIO_VAPI_CTRL (GPIO verification):    Verification API.    (line 119)
4319
* GPIO_VAPI_DATA (GPIO verification):    Verification API.    (line  97)
4320
* GPIO_VAPI_INTE (GPIO verification):    Verification API.    (line 110)
4321
* GPIO_VAPI_PTRIG (GPIO verification):   Verification API.    (line 113)
4322
* GPIO_VAPI_RGPIO (GPIO verification):   Verification API.    (line 107)
4323 100 julius
* hardfloat (CPU configuration):         CPU Configuration.   (line 110)
4324 98 jeremybenn
* hazards (CPU configuration):           CPU Configuration.   (line  74)
4325 19 jeremybenn
* heads (ATA/ATAPI device configuration): Disc Interface Configuration.
4326 385 jeremybenn
                                                              (line 125)
4327 19 jeremybenn
* help (Interactive CLI):                Interactive Command Line.
4328
                                                              (line 170)
4329
* hexadecimal memory dump (Interactive CLI): Interactive Command Line.
4330
                                                              (line 133)
4331
* hide_device_id (verification API configuration): Verification API Configuration.
4332
                                                              (line  36)
4333
* hist (Interactive CLI):                Interactive Command Line.
4334
                                                              (line  67)
4335 82 jeremybenn
* history (simulator configuration):     Simulator Behavior.  (line  40)
4336 19 jeremybenn
* history of execution (Interactive CLI): Interactive Command Line.
4337
                                                              (line  67)
4338
* hitdelay (branch prediction configuration): Branch Prediction Configuration.
4339
                                                              (line  33)
4340
* hitdelay (instruction cache configuration): Cache Configuration.
4341
                                                              (line  38)
4342
* hitdelay (MMU configuration):          Memory Management Configuration.
4343
                                                              (line  51)
4344 104 jeremybenn
* host test code:                        Regression Testing.  (line  57)
4345 19 jeremybenn
* hw_enabled (generic peripheral configuration): Generic Peripheral Configuration.
4346
                                                              (line  49)
4347
* IMMU configuration:                    Memory Management Configuration.
4348
                                                              (line   6)
4349
* index (memory controller configuration): Memory Controller Configuration.
4350 385 jeremybenn
                                                              (line  77)
4351 19 jeremybenn
* info (Interactive CLI):                Interactive Command Line.
4352
                                                              (line 119)
4353
* installing Or1ksim:                    Installation.        (line   6)
4354
* instruction cache configuration:       Cache Configuration. (line   6)
4355
* instruction MMU configuration:         Memory Management Configuration.
4356
                                                              (line   6)
4357
* instruction profiling for Or1ksim:     Profiling Utility.   (line   6)
4358
* instruction profiling utility (Interactive CLI): Interactive Command Line.
4359
                                                              (line 178)
4360
* internal debugging:                    Internal Debugging.  (line   6)
4361
* interrupt controller configuration:    Interrupt Configuration.
4362
                                                              (line   6)
4363 432 jeremybenn
* interrupts:                            Concepts.            (line  20)
4364 19 jeremybenn
* irq (ATA/ATAPI configuration):         Disc Interface Configuration.
4365 385 jeremybenn
                                                              (line  36)
4366 19 jeremybenn
* irq (DMA configuration):               DMA Configuration.   (line  34)
4367
* irq (GPIO configuration):              GPIO Configuration.  (line  29)
4368
* irq (keyboard configuration):          Keyboard Configuration.
4369
                                                              (line  47)
4370
* irq (UART configuration):              UART Configuration.  (line  70)
4371
* irq (VGA configuration):               Display Interface Configuration.
4372
                                                              (line  37)
4373
* jitter (UART configuration):           UART Configuration.  (line  78)
4374
* keyboard configuration:                Keyboard Configuration.
4375
                                                              (line   6)
4376 460 jeremybenn
* l.nop 0:                               l.nop Support.       (line  12)
4377
* l.nop 1 (end simulation):              l.nop Support.       (line  15)
4378
* l.nop 2 (report):                      l.nop Support.       (line  19)
4379
* l.nop 3 (printf, now obsolete):        l.nop Support.       (line  22)
4380
* l.nop 4 (putc):                        l.nop Support.       (line  29)
4381
* l.nop 5 (reset statistics counters):   l.nop Support.       (line  34)
4382
* l.nop 6 (get clock ticks):             l.nop Support.       (line  37)
4383
* l.nop 7 (get picoseconds per cycle):   l.nop Support.       (line  41)
4384 472 jeremybenn
* l.nop 8 (turn off tracing):            Trace Generation.    (line  40)
4385
* l.nop 8 (turn on tracing) <1>:         l.nop Support.       (line  45)
4386
* l.nop 8 (turn on tracing):             Trace Generation.    (line  40)
4387 460 jeremybenn
* l.nop 9 (turn off tracing):            l.nop Support.       (line  48)
4388
* l.nop opcode effects:                  l.nop Support.       (line   6)
4389 19 jeremybenn
* library version of Or1ksim:            Simulator Library.   (line   6)
4390
* license for Or1ksim:                   GNU Free Documentation License.
4391
                                                              (line   6)
4392 440 jeremybenn
* Linux (OpenRISC) and Ethernet:         Networking from OpenRISC Linux and BusyBox.
4393
                                                              (line   6)
4394 19 jeremybenn
* list breakpoints (Interactive CLI):    Interactive Command Line.
4395
                                                              (line  60)
4396
* load_hitdelay (data cache configuration): Cache Configuration.
4397
                                                              (line  46)
4398
* load_missdelay (data cache configuration): Cache Configuration.
4399
                                                              (line  50)
4400
* log (memory configuration):            Memory Configuration.
4401 418 julius
                                                              (line 156)
4402 19 jeremybenn
* log_enabled (verification API configuration): Verification API Configuration.
4403
                                                              (line  28)
4404 432 jeremybenn
* long:                                  Simulator Library.   (line  94)
4405 104 jeremybenn
* make file for tests:                   Regression Testing.  (line  27)
4406 19 jeremybenn
* mc (memory configuration):             Memory Configuration.
4407 418 julius
                                                              (line 133)
4408 19 jeremybenn
* memory configuration:                  Memory Configuration.
4409
                                                              (line   6)
4410
* memory controller configuration:       Memory Controller Configuration.
4411
                                                              (line   6)
4412
* memory copying (Interactive CLI):      Interactive Command Line.
4413
                                                              (line  54)
4414
* memory display (Interactive CLI):      Interactive Command Line.
4415
                                                              (line  31)
4416
* memory dump, hexadecimal (Interactive CLI): Interactive Command Line.
4417
                                                              (line 133)
4418
* memory dump, Verilog (Interactive CLI): Interactive Command Line.
4419
                                                              (line 124)
4420
* memory patching (Interactive CLI):     Interactive Command Line.
4421
                                                              (line  48)
4422
* memory profiling end address:          Memory Profiling Utility.
4423
                                                              (line  56)
4424
* memory profiling start address:        Memory Profiling Utility.
4425
                                                              (line  56)
4426
* memory profiling utility (Interactive CLI): Interactive Command Line.
4427
                                                              (line 173)
4428
* memory profiling version of Or1ksim:   Memory Profiling Utility.
4429
                                                              (line   6)
4430
* memory_order (CUC configuration):      CUC Configuration.   (line  15)
4431 346 jeremybenn
* memory_order=exact (CUC configuration): CUC Configuration.  (line  30)
4432 19 jeremybenn
* memory_order=none (CUC configuration): CUC Configuration.   (line  18)
4433 346 jeremybenn
* memory_order=strong (CUC configuration): CUC Configuration. (line  27)
4434
* memory_order=weak (CUC configuration): CUC Configuration.   (line  22)
4435 19 jeremybenn
* missdelay (branch prediction configuration): Branch Prediction Configuration.
4436
                                                              (line  37)
4437
* missdelay (instruction cache configuration): Cache Configuration.
4438
                                                              (line  42)
4439
* missdelay (MMU configuration):         Memory Management Configuration.
4440
                                                              (line  55)
4441
* MMU configuration:                     Memory Management Configuration.
4442
                                                              (line   6)
4443 82 jeremybenn
* mprof_file (simulator configuration):  Simulator Behavior.  (line  34)
4444 19 jeremybenn
* mprof_fn (simulator configuration - deprecated): Simulator Behavior.
4445 82 jeremybenn
                                                              (line  34)
4446 19 jeremybenn
* mprofile (Interactive CLI):            Interactive Command Line.
4447 346 jeremybenn
                                                              (line 173)
4448 82 jeremybenn
* mprofile (simulator configuration):    Simulator Behavior.  (line  29)
4449 432 jeremybenn
* mtspr:                                 Concepts.            (line  20)
4450 19 jeremybenn
* mwdma (ATA/ATAPI device configuration): Disc Interface Configuration.
4451 385 jeremybenn
                                                              (line 132)
4452 19 jeremybenn
* name (generic peripheral configuration): Generic Peripheral Configuration.
4453
                                                              (line  42)
4454
* name (memory configuration):           Memory Configuration.
4455 418 julius
                                                              (line 115)
4456 346 jeremybenn
* no_multicycle (CUC configuration):     CUC Configuration.   (line  45)
4457 19 jeremybenn
* nsets (cache configuration):           Cache Configuration. (line  15)
4458
* nsets (MMU configuration):             Memory Management Configuration.
4459
                                                              (line  16)
4460
* nways (cache configuration):           Cache Configuration. (line  22)
4461
* nways (MMU configuration):             Memory Management Configuration.
4462
                                                              (line  22)
4463 432 jeremybenn
* or1ksim_get_time_period:               Simulator Library.   (line  84)
4464
* or1ksim_init:                          Simulator Library.   (line  19)
4465
* or1ksim_interrupt:                     Simulator Library.   (line  99)
4466
* or1ksim_interrupt_clear:               Simulator Library.   (line 121)
4467
* or1ksim_interrupt_set:                 Simulator Library.   (line 110)
4468
* or1ksim_is_le:                         Simulator Library.   (line  89)
4469
* or1ksim_jtag_reset:                    Simulator Library.   (line 130)
4470
* or1ksim_jtag_shift_dr:                 Simulator Library.   (line 152)
4471
* or1ksim_jtag_shift_ir:                 Simulator Library.   (line 139)
4472
* or1ksim_read_mem:                      Simulator Library.   (line 165)
4473
* or1ksim_read_reg:                      Simulator Library.   (line 197)
4474 346 jeremybenn
* or1ksim_read_spr:                      Simulator Library.   (line 181)
4475 432 jeremybenn
* or1ksim_reset_duration:                Simulator Library.   (line  69)
4476
* or1ksim_run:                           Simulator Library.   (line  58)
4477
* or1ksim_set_stall_state:               Simulator Library.   (line 212)
4478
* or1ksim_set_time_point:                Simulator Library.   (line  80)
4479
* or1ksim_write_mem:                     Simulator Library.   (line 173)
4480
* or1ksim_write_reg:                     Simulator Library.   (line 205)
4481
* or1ksim_write_spr:                     Simulator Library.   (line 189)
4482 19 jeremybenn
* output rediretion:                     Concepts.            (line   7)
4483
* overflow flag setting by instructions: Configuring the Build.
4484 127 jeremybenn
                                                              (line 133)
4485 19 jeremybenn
* packet (ATA/ATAPI device configuration): Disc Interface Configuration.
4486 385 jeremybenn
                                                              (line 117)
4487 19 jeremybenn
* pagesize (MMU configuration):          Memory Management Configuration.
4488
                                                              (line  27)
4489
* patching memory (Interactive CLI):     Interactive Command Line.
4490
                                                              (line  48)
4491
* patching registers (Interactive CLI):  Interactive Command Line.
4492
                                                              (line  28)
4493
* patching the program counter (Interactive CLI): Interactive Command Line.
4494
                                                              (line  51)
4495
* pattern (memory configuration):        Memory Configuration.
4496 418 julius
                                                              (line  82)
4497 19 jeremybenn
* pc (Interactive CLI):                  Interactive Command Line.
4498
                                                              (line  51)
4499 440 jeremybenn
* persistent TAP device creation:        Setting Up a Persistent TAP device.
4500
                                                              (line   6)
4501 429 julius
* phy_addr:                              Ethernet Configuration.
4502 451 jeremybenn
                                                              (line  99)
4503 19 jeremybenn
* PIC configuration:                     Interrupt Configuration.
4504
                                                              (line   6)
4505
* pio (ATA/ATAPI device configuration):  Disc Interface Configuration.
4506 385 jeremybenn
                                                              (line 136)
4507 19 jeremybenn
* pio_mode0_t1 (ATA/ATAPI configuration): Disc Interface Configuration.
4508 385 jeremybenn
                                                              (line  55)
4509 19 jeremybenn
* pio_mode0_t2 (ATA/ATAPI configuration): Disc Interface Configuration.
4510 385 jeremybenn
                                                              (line  56)
4511 19 jeremybenn
* pio_mode0_t4 (ATA/ATAPI configuration): Disc Interface Configuration.
4512 385 jeremybenn
                                                              (line  57)
4513 19 jeremybenn
* pio_mode0_teoc (ATA/ATAPI configuration): Disc Interface Configuration.
4514 385 jeremybenn
                                                              (line  58)
4515 19 jeremybenn
* pm (Interactive CLI):                  Interactive Command Line.
4516
                                                              (line  48)
4517
* PMR - DGCE:                            Power Management Configuration.
4518
                                                              (line  21)
4519
* PMR - DME:                             Power Management Configuration.
4520
                                                              (line  15)
4521
* PMR - SDF:                             Power Management Configuration.
4522
                                                              (line  12)
4523
* PMR - SME:                             Power Management Configuration.
4524
                                                              (line  16)
4525
* PMR - SUME:                            Power Management Configuration.
4526
                                                              (line  24)
4527
* PMU configuration:                     Power Management Configuration.
4528
                                                              (line   6)
4529
* poc (memory controller configuration): Memory Controller Configuration.
4530 385 jeremybenn
                                                              (line  64)
4531 19 jeremybenn
* port range for TCP/IP:                 Verification API Configuration.
4532
                                                              (line  23)
4533
* power management configuration:        Power Management Configuration.
4534
                                                              (line   6)
4535
* power management register, DGCE:       Power Management Configuration.
4536
                                                              (line  21)
4537
* power management register, DME:        Power Management Configuration.
4538
                                                              (line  15)
4539
* power management register, SDF:        Power Management Configuration.
4540
                                                              (line  12)
4541
* power management register, SME:        Power Management Configuration.
4542
                                                              (line  16)
4543
* power management register, SUME:       Power Management Configuration.
4544
                                                              (line  24)
4545
* pr (Interactive CLI):                  Interactive Command Line.
4546
                                                              (line  28)
4547
* private ports, use of:                 Verification API Configuration.
4548
                                                              (line  23)
4549
* processor configuration:               CPU Configuration.   (line   6)
4550
* processor stall (Interactive CLI):     Interactive Command Line.
4551
                                                              (line  72)
4552
* processor unstall (Interactive CLI):   Interactive Command Line.
4553
                                                              (line  78)
4554
* prof_file (simulator configuration):   Simulator Behavior.  (line  23)
4555
* prof_fn (simulator configuration - deprecated): Simulator Behavior.
4556
                                                              (line  23)
4557
* profile (simulator configuration):     Simulator Behavior.  (line  19)
4558
* profiling for Or1ksim:                 Profiling Utility.   (line   6)
4559
* profiling utility (Interactive CLI):   Interactive Command Line.
4560
                                                              (line 178)
4561
* program counter patching (Interactive CLI): Interactive Command Line.
4562
                                                              (line  51)
4563
* programmable interrupt controller configuration: Interrupt Configuration.
4564
                                                              (line   6)
4565
* PS2 configuration:                     Keyboard Configuration.
4566
                                                              (line   6)
4567
* q (Interactive CLI):                   Interactive Command Line.
4568
                                                              (line  11)
4569
* quitting (Interactive CLI):            Interactive Command Line.
4570
                                                              (line  11)
4571
* r (Interactive CLI):                   Interactive Command Line.
4572
                                                              (line  14)
4573
* random_seed (memory configuration):    Memory Configuration.
4574 418 julius
                                                              (line  72)
4575 19 jeremybenn
* refresh_rate (frame buffer configuration): Frame Buffer Configuration.
4576 82 jeremybenn
                                                              (line  30)
4577 19 jeremybenn
* refresh_rate (VGA configuration):      Display Interface Configuration.
4578
                                                              (line  41)
4579
* reg_sim_reset:                         Concepts.            (line  13)
4580
* register display (Interactive CLI):    Interactive Command Line.
4581
                                                              (line  14)
4582
* register over time statistics:         Configuring the Build.
4583 127 jeremybenn
                                                              (line  92)
4584 19 jeremybenn
* register patching (Interactive CLI):   Interactive Command Line.
4585
                                                              (line  28)
4586 104 jeremybenn
* regression testing:                    Regression Testing.  (line   6)
4587 19 jeremybenn
* Remote Serial Protocol:                Debug Interface Configuration.
4588
                                                              (line  20)
4589 235 jeremybenn
* Remote Serial Protocol, --nosrv:       Standalone Simulator.
4590 472 jeremybenn
                                                              (line  65)
4591 235 jeremybenn
* Remote Serial Protocol, --srv:         Standalone Simulator.
4592 472 jeremybenn
                                                              (line  73)
4593 432 jeremybenn
* report_interrupt:                      Concepts.            (line  20)
4594 19 jeremybenn
* reset (Interactive CLI):               Interactive Command Line.
4595
                                                              (line  63)
4596
* reset hooks:                           Concepts.            (line  13)
4597
* reset the simulator (Interactive CLI): Interactive Command Line.
4598
                                                              (line  63)
4599
* rev (ATA/ATAPI configuration):         Disc Interface Configuration.
4600 385 jeremybenn
                                                              (line  48)
4601 19 jeremybenn
* rev (CPU configuration):               CPU Configuration.   (line  15)
4602
* rsp_enabled (debug interface configuration): Debug Interface Configuration.
4603
                                                              (line  20)
4604
* rsp_port (debug interface configuration): Debug Interface Configuration.
4605 235 jeremybenn
                                                              (line  32)
4606 19 jeremybenn
* rtx_type (Ethernet configuration):     Ethernet Configuration.
4607 440 jeremybenn
                                                              (line  47)
4608 19 jeremybenn
* run (Interactive CLI):                 Interactive Command Line.
4609
                                                              (line  23)
4610
* running code (Interactive CLI):        Interactive Command Line.
4611
                                                              (line  23)
4612
* running Or1ksim:                       Usage.               (line   6)
4613
* runtime:                               Global Data Structures.
4614
                                                              (line  58)
4615
* runtime global structure:              Global Data Structures.
4616
                                                              (line  58)
4617
* runtime.cpu:                           Global Data Structures.
4618
                                                              (line  62)
4619
* runtime.cpu.fout:                      Concepts.            (line   7)
4620
* runtime.cuc:                           Global Data Structures.
4621
                                                              (line  62)
4622
* runtime.vapi:                          Global Data Structures.
4623
                                                              (line  62)
4624
* rx_channel (Ethernet configuration):   Ethernet Configuration.
4625 440 jeremybenn
                                                              (line  67)
4626 19 jeremybenn
* rxfile (Ethernet configuration):       Ethernet Configuration.
4627 440 jeremybenn
                                                              (line  76)
4628 19 jeremybenn
* sbp_bf_fwd (branch prediction configuration): Branch Prediction Configuration.
4629
                                                              (line  23)
4630
* sbp_bnf_fwd (branch prediction configuration): Branch Prediction Configuration.
4631
                                                              (line  28)
4632 98 jeremybenn
* sbuf_len (CPU configuration):          CPU Configuration.   (line 101)
4633 19 jeremybenn
* SDF (power management register):       Power Management Configuration.
4634
                                                              (line  12)
4635
* section ata:                           Disc Interface Configuration.
4636
                                                              (line   6)
4637
* section bpb:                           Branch Prediction Configuration.
4638
                                                              (line   6)
4639
* section cpio:                          GPIO Configuration.  (line   6)
4640
* section cpu:                           CPU Configuration.   (line   6)
4641
* section cuc:                           CUC Configuration.   (line   6)
4642
* section dc:                            Cache Configuration. (line   6)
4643
* section debug:                         Debug Interface Configuration.
4644
                                                              (line   6)
4645
* section dma:                           DMA Configuration.   (line   6)
4646
* section dmmu:                          Memory Management Configuration.
4647
                                                              (line   6)
4648
* section ethernet:                      Ethernet Configuration.
4649
                                                              (line   6)
4650
* section fb:                            Frame Buffer Configuration.
4651
                                                              (line   6)
4652
* section generic:                       Generic Peripheral Configuration.
4653
                                                              (line   6)
4654
* section ic:                            Cache Configuration. (line   6)
4655
* section immu:                          Memory Management Configuration.
4656
                                                              (line   6)
4657
* section kb:                            Keyboard Configuration.
4658
                                                              (line   6)
4659
* section mc:                            Memory Controller Configuration.
4660
                                                              (line   6)
4661
* section memory:                        Memory Configuration.
4662
                                                              (line   6)
4663
* section pic:                           Interrupt Configuration.
4664
                                                              (line   6)
4665
* section pmu:                           Power Management Configuration.
4666
                                                              (line   6)
4667
* section sim:                           Simulator Behavior.  (line   6)
4668
* section uart:                          UART Configuration.  (line   6)
4669
* section vapi:                          Verification API Configuration.
4670
                                                              (line   6)
4671
* section vga:                           Display Interface Configuration.
4672
                                                              (line   6)
4673
* sections:                              Global Data Structures.
4674
                                                              (line  49)
4675
* sectors (ATA/ATAPI device configuration): Disc Interface Configuration.
4676 385 jeremybenn
                                                              (line 129)
4677 19 jeremybenn
* server_port (verification API configuration): Verification API Configuration.
4678
                                                              (line  19)
4679
* set (Interactive CLI):                 Interactive Command Line.
4680
                                                              (line 146)
4681
* set breakpoint (Interactive CLI):      Interactive Command Line.
4682
                                                              (line  57)
4683
* setdbch (Interactive CLI):             Interactive Command Line.
4684
                                                              (line 141)
4685
* simple model:                          Configuring the Build.
4686 104 jeremybenn
                                                              (line  37)
4687 19 jeremybenn
* simulator configuration:               Simulator Behavior.  (line   6)
4688
* simulator configuration info (Interactive CLI): Interactive Command Line.
4689
                                                              (line 119)
4690
* simulator reset (Interactive CLI):     Interactive Command Line.
4691
                                                              (line  63)
4692
* simulator statistics (Interactive CLI): Interactive Command Line.
4693
                                                              (line  83)
4694
* size (ATA/ATAPI device configuration): Disc Interface Configuration.
4695 385 jeremybenn
                                                              (line 113)
4696 19 jeremybenn
* size (generic peripheral configuration): Generic Peripheral Configuration.
4697
                                                              (line  30)
4698
* size (memory configuration):           Memory Configuration.
4699 418 julius
                                                              (line  99)
4700 19 jeremybenn
* sleep mode (power management register): Power Management Configuration.
4701
                                                              (line  16)
4702
* slow down factor (power management register): Power Management Configuration.
4703
                                                              (line  12)
4704
* SME (power management register):       Power Management Configuration.
4705
                                                              (line  16)
4706
* sr (CPU configuration):                CPU Configuration.   (line  53)
4707
* stall (Interactive CLI):               Interactive Command Line.
4708
                                                              (line  72)
4709
* stall the processor (Interactive CLI): Interactive Command Line.
4710
                                                              (line  72)
4711
* statistics, register over time:        Configuring the Build.
4712 127 jeremybenn
                                                              (line  92)
4713 19 jeremybenn
* statistics, simulation (Interactive CLI): Interactive Command Line.
4714
                                                              (line  83)
4715
* stats (Interactive CLI):               Interactive Command Line.
4716
                                                              (line  83)
4717
* stepping code (Interactive CLI):       Interactive Command Line.
4718
                                                              (line  19)
4719
* store_hitdelay (data cache configuration): Cache Configuration.
4720
                                                              (line  54)
4721
* store_missdelay (data cache configuration): Cache Configuration.
4722
                                                              (line  58)
4723
* SUME (power management register):      Power Management Configuration.
4724
                                                              (line  24)
4725 98 jeremybenn
* superscalar (CPU configuration):       CPU Configuration.   (line  63)
4726 19 jeremybenn
* suspend mode (power management register): Power Management Configuration.
4727
                                                              (line  24)
4728
* t (Interactive CLI):                   Interactive Command Line.
4729
                                                              (line  19)
4730 440 jeremybenn
* TAP device creation:                   Setting Up a Persistent TAP device.
4731
                                                              (line   6)
4732
* tap_dev (Ethernet configuration):      Ethernet Configuration.
4733
                                                              (line  93)
4734 104 jeremybenn
* target test code:                      Regression Testing.  (line  63)
4735 19 jeremybenn
* TCP/IP port range:                     Verification API Configuration.
4736
                                                              (line  23)
4737
* TCP/IP port range for or1ksim-rsp service: Debug Interface Configuration.
4738 235 jeremybenn
                                                              (line  37)
4739 104 jeremybenn
* test code for host:                    Regression Testing.  (line  57)
4740
* test code for target:                  Regression Testing.  (line  63)
4741
* test make file:                        Regression Testing.  (line  27)
4742
* test README:                           Regression Testing.  (line  32)
4743
* testing:                               Regression Testing.  (line   6)
4744 82 jeremybenn
* tests, all enabled.:                   Configuring the Build.
4745 127 jeremybenn
                                                              (line 105)
4746 346 jeremybenn
* timings_file (CUC configuration):      CUC Configuration.   (line  49)
4747 19 jeremybenn
* timings_fn (CUC configuration - deprecated): CUC Configuration.
4748 346 jeremybenn
                                                              (line  49)
4749 19 jeremybenn
* toggle breakpoint (Interactive CLI):   Interactive Command Line.
4750
                                                              (line  57)
4751
* toggle debug channels (Interactive CLI): Interactive Command Line.
4752
                                                              (line 141)
4753
* toggle debug mode (Interactive CLI):   Interactive Command Line.
4754
                                                              (line 151)
4755 442 julius
* trace generation of Or1ksim:           Trace Generation.    (line   6)
4756 19 jeremybenn
* tx_channel (Ethernet configuration):   Ethernet Configuration.
4757 440 jeremybenn
                                                              (line  68)
4758 19 jeremybenn
* txfile (Ethernet configuration):       Ethernet Configuration.
4759 440 jeremybenn
                                                              (line  77)
4760 19 jeremybenn
* txfile (frame buffer configuration):   Frame Buffer Configuration.
4761 82 jeremybenn
                                                              (line  36)
4762 19 jeremybenn
* txfile (VGA configuration):            Display Interface Configuration.
4763
                                                              (line  47)
4764
* type (ATA/ATAPI device configuration): Disc Interface Configuration.
4765 385 jeremybenn
                                                              (line 103)
4766 19 jeremybenn
* type (memory configuration):           Memory Configuration.
4767 385 jeremybenn
                                                              (line  37)
4768 418 julius
* type=exitnops (memory configuration):  Memory Configuration.
4769 420 jeremybenn
                                                              (line  66)
4770 19 jeremybenn
* type=pattern (memory configuration):   Memory Configuration.
4771 385 jeremybenn
                                                              (line  47)
4772 19 jeremybenn
* type=random (memory configuration):    Memory Configuration.
4773 385 jeremybenn
                                                              (line  41)
4774 19 jeremybenn
* type=unknown (memory configuration):   Memory Configuration.
4775 385 jeremybenn
                                                              (line  51)
4776 19 jeremybenn
* type=zero (memory configuration):      Memory Configuration.
4777 385 jeremybenn
                                                              (line  56)
4778 19 jeremybenn
* UART configuration:                    UART Configuration.  (line   6)
4779
* UART I/O from/to a physical serial port: UART Configuration.
4780
                                                              (line  62)
4781
* UART I/O from/to an xterm:             UART Configuration.  (line  38)
4782
* UART I/O from/to files:                UART Configuration.  (line  33)
4783
* UART I/O from/to open file descriptors: UART Configuration. (line  58)
4784
* UART I/O from/to TCP/IP:               UART Configuration.  (line  45)
4785
* UART verification (VAPI):              Verification API.    (line  41)
4786
* unstall (Interactive CLI):             Interactive Command Line.
4787
                                                              (line  78)
4788
* unstall the processor (Interactive CLI): Interactive Command Line.
4789
                                                              (line  78)
4790
* upr (CPU configuration):               CPU Configuration.   (line  21)
4791 432 jeremybenn
* use_nmi (interrupt controller):        Interrupt Configuration.
4792
                                                              (line  30)
4793 19 jeremybenn
* ustates (cache configuration):         Cache Configuration. (line  33)
4794
* ustates (MMU configuration):           Memory Management Configuration.
4795
                                                              (line  41)
4796
* VAPI configuration:                    Verification API Configuration.
4797
                                                              (line   6)
4798
* VAPI for Debug Unit:                   Verification API.    (line  34)
4799
* VAPI for DMA:                          Verification API.    (line  73)
4800
* VAPI for Ethernet:                     Verification API.    (line  78)
4801
* VAPI for GPIO:                         Verification API.    (line  88)
4802
* VAPI for UART:                         Verification API.    (line  41)
4803
* vapi_id (debug interface configuration): Debug Interface Configuration.
4804 235 jeremybenn
                                                              (line  43)
4805 346 jeremybenn
* vapi_id (DMA configuration) <1>:       Ethernet Configuration.
4806 451 jeremybenn
                                                              (line 119)
4807 346 jeremybenn
* vapi_id (DMA configuration):           DMA Configuration.   (line  38)
4808 19 jeremybenn
* vapi_id (GPIO configuration):          GPIO Configuration.  (line  32)
4809
* vapi_id (UART configuration):          UART Configuration.  (line  85)
4810
* vapi_log_file (verification API configuration): Verification API Configuration.
4811
                                                              (line  41)
4812
* vapi_log_fn (verification API configuration - deprecated): Verification API Configuration.
4813
                                                              (line  41)
4814
* ver (CPU configuration):               CPU Configuration.   (line  15)
4815
* verbose (simulator configuration):     Simulator Behavior.  (line  10)
4816
* Verification API configuration:        Verification API Configuration.
4817
                                                              (line   6)
4818
* Verilog memory dump (Interactive CLI): Interactive Command Line.
4819
                                                              (line 124)
4820
* VGA configuration:                     Display Interface Configuration.
4821
 
4822
 
4823
                                                              (line  50)
4824
4825
4826

4827
Tag Table:
4828 450 jeremybenn
Node: Top810
4829
Node: Installation1220
4830
Node: Preparation1467
4831
Node: Configuring the Build1762
4832
Node: Build and Install7902
4833
Node: Known Issues8668
4834
Node: Usage9723
4835 460 jeremybenn
Node: Standalone Simulator10007
4836 472 jeremybenn
Node: Profiling Utility15151
4837
Node: Memory Profiling Utility16057
4838
Node: Trace Generation17417
4839
Node: Simulator Library19602
4840
Node: Ethernet TUN/TAP Interface30034
4841
Node: Setting Up a Persistent TAP device31139
4842
Node: Establishing a Bridge31814
4843
Node: Opening the Firewall33497
4844
Node: Disabling Ethernet Filtering33988
4845
Node: Networking from OpenRISC Linux and BusyBox34613
4846
Node: Tearing Down a Bridge36275
4847
Node: l.nop Support37018
4848
Node: Configuration38528
4849
Node: Configuration File Format39140
4850
Node: Configuration File Preprocessing39525
4851
Node: Configuration File Syntax39822
4852
Node: Simulator Configuration42607
4853
Node: Simulator Behavior42898
4854
Node: Verification API Configuration47479
4855
Node: CUC Configuration49419
4856
Node: Core OpenRISC Configuration51411
4857
Node: CPU Configuration51913
4858
Node: Memory Configuration56032
4859
Node: Memory Management Configuration62754
4860
Node: Cache Configuration65131
4861
Node: Interrupt Configuration67517
4862
Node: Power Management Configuration69350
4863
Node: Branch Prediction Configuration70627
4864
Node: Debug Interface Configuration71987
4865
Node: Peripheral Configuration74330
4866
Node: Memory Controller Configuration74956
4867
Node: UART Configuration78736
4868
Node: DMA Configuration82255
4869
Node: Ethernet Configuration84122
4870
Node: GPIO Configuration89401
4871
Node: Display Interface Configuration91034
4872
Node: Frame Buffer Configuration93343
4873
Node: Keyboard Configuration95207
4874
Node: Disc Interface Configuration97445
4875
Node: Generic Peripheral Configuration102549
4876
Node: Interactive Command Line104844
4877
Node: Verification API111818
4878
Node: Code Internals116248
4879
Node: Coding Conventions116831
4880
Node: Global Data Structures121258
4881
Node: Concepts123915
4882
Ref: Output Redirection124060
4883
Ref: Interrupts Internal124598
4884
Node: Internal Debugging125751
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Node: GNU Free Documentation License130064

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