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[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [support/] [spr-defs.h] - Blame information for rev 432

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1 233 julius
/* ipc.h.  Microkernel IPC header for Or1ksim
2
 
3
   Copyright (C) 2000 Damjan Lampret
4
   Copyright (C) 2008, 2010 Embecosm Limited
5
 
6
   Contributor Damjan Lampret <lampret@opencores.org>
7
   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
8 90 jeremybenn
 
9 233 julius
   This file is part of OpenRISC 1000 Architectural Simulator.
10
 
11
   This program is free software; you can redistribute it and/or modify it
12
   under the terms of the GNU General Public License as published by the Free
13
   Software Foundation; either version 3 of the License, or (at your option)
14
   any later version.
15
 
16
   This program is distributed in the hope that it will be useful, but WITHOUT
17
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19
   more details.
20
 
21
   You should have received a copy of the GNU General Public License along
22
   with this program.  If not, see <http:  www.gnu.org/licenses/>.  */
23
 
24
/* ----------------------------------------------------------------------------
25
   This code is commented throughout for use with Doxygen.
26
   --------------------------------------------------------------------------*/
27
 
28
/* This file is part of test microkernel for OpenRISC 1000. */
29
/* spr-defs.h -- Defines OR1K architecture specific special-purpose registers
30
 
31 90 jeremybenn
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
32
   Copyright (C) 2008 Embecosm Limited
33
 
34
   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
35
 
36
   This file is part of OpenRISC 1000 Architectural Simulator.
37
 
38
   This program is free software; you can redistribute it and/or modify it
39
   under the terms of the GNU General Public License as published by the Free
40
   Software Foundation; either version 3 of the License, or (at your option)
41
   any later version.
42
 
43
   This program is distributed in the hope that it will be useful, but WITHOUT
44
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
45
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
46
   more details.
47
 
48
   You should have received a copy of the GNU General Public License along
49
   with this program.  If not, see <http://www.gnu.org/licenses/>. */
50
 
51 233 julius
/* This program is commented throughout in a fashion suitable for processing
52
   with Doxygen. */
53 90 jeremybenn
 
54
 
55 233 julius
#ifndef SPR_DEFS__H
56
#define SPR_DEFS__H
57
 
58
/* Definition of special-purpose registers (SPRs). */
59
 
60 90 jeremybenn
#define MAX_GRPS (32)
61
#define MAX_SPRS_PER_GRP_BITS (11)
62
#define MAX_SPRS_PER_GRP (1 << MAX_SPRS_PER_GRP_BITS)
63
#define MAX_SPRS (0x10000)
64
 
65
/* Base addresses for the groups */
66
#define SPRGROUP_SYS    (0<< MAX_SPRS_PER_GRP_BITS)
67
#define SPRGROUP_DMMU   (1<< MAX_SPRS_PER_GRP_BITS)
68
#define SPRGROUP_IMMU   (2<< MAX_SPRS_PER_GRP_BITS)
69
#define SPRGROUP_DC     (3<< MAX_SPRS_PER_GRP_BITS)
70
#define SPRGROUP_IC     (4<< MAX_SPRS_PER_GRP_BITS)
71
#define SPRGROUP_MAC    (5<< MAX_SPRS_PER_GRP_BITS)
72
#define SPRGROUP_D      (6<< MAX_SPRS_PER_GRP_BITS)
73
#define SPRGROUP_PC     (7<< MAX_SPRS_PER_GRP_BITS)
74
#define SPRGROUP_PM     (8<< MAX_SPRS_PER_GRP_BITS)
75
#define SPRGROUP_PIC    (9<< MAX_SPRS_PER_GRP_BITS)
76
#define SPRGROUP_TT     (10<< MAX_SPRS_PER_GRP_BITS)
77 233 julius
#define SPRGROUP_FP     (11<< MAX_SPRS_PER_GRP_BITS)
78 90 jeremybenn
 
79
/* System control and status group */
80
#define SPR_VR          (SPRGROUP_SYS + 0)
81
#define SPR_UPR         (SPRGROUP_SYS + 1)
82
#define SPR_CPUCFGR     (SPRGROUP_SYS + 2)
83
#define SPR_DMMUCFGR    (SPRGROUP_SYS + 3)
84
#define SPR_IMMUCFGR    (SPRGROUP_SYS + 4)
85
#define SPR_DCCFGR      (SPRGROUP_SYS + 5)
86
#define SPR_ICCFGR      (SPRGROUP_SYS + 6)
87
#define SPR_DCFGR       (SPRGROUP_SYS + 7)
88
#define SPR_PCCFGR      (SPRGROUP_SYS + 8)
89
#define SPR_NPC         (SPRGROUP_SYS + 16)  /* CZ 21/06/01 */
90
#define SPR_SR          (SPRGROUP_SYS + 17)  /* CZ 21/06/01 */
91
#define SPR_PPC         (SPRGROUP_SYS + 18)  /* CZ 21/06/01 */
92 233 julius
#define SPR_FPCSR       (SPRGROUP_SYS + 20)  /* CZ 21/06/01 */
93 90 jeremybenn
#define SPR_EPCR_BASE   (SPRGROUP_SYS + 32)  /* CZ 21/06/01 */
94
#define SPR_EPCR_LAST   (SPRGROUP_SYS + 47)  /* CZ 21/06/01 */
95
#define SPR_EEAR_BASE   (SPRGROUP_SYS + 48)
96
#define SPR_EEAR_LAST   (SPRGROUP_SYS + 63)
97
#define SPR_ESR_BASE    (SPRGROUP_SYS + 64)
98
#define SPR_ESR_LAST    (SPRGROUP_SYS + 79)
99 233 julius
#define SPR_GPR_BASE    (SPRGROUP_SYS + 1024)
100 90 jeremybenn
 
101
/* Data MMU group */
102
#define SPR_DMMUCR      (SPRGROUP_DMMU + 0)
103
#define SPR_DTLBMR_BASE(WAY)    (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)
104
#define SPR_DTLBMR_LAST(WAY)    (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)
105
#define SPR_DTLBTR_BASE(WAY)    (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100)
106
#define SPR_DTLBTR_LAST(WAY)    (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100)
107
 
108
/* Instruction MMU group */
109
#define SPR_IMMUCR      (SPRGROUP_IMMU + 0)
110
#define SPR_ITLBMR_BASE(WAY)    (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100)
111
#define SPR_ITLBMR_LAST(WAY)    (SPRGROUP_IMMU + 0x27f + (WAY) * 0x100)
112
#define SPR_ITLBTR_BASE(WAY)    (SPRGROUP_IMMU + 0x280 + (WAY) * 0x100)
113
#define SPR_ITLBTR_LAST(WAY)    (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100)
114
 
115
/* Data cache group */
116
#define SPR_DCCR        (SPRGROUP_DC + 0)
117
#define SPR_DCBPR       (SPRGROUP_DC + 1)
118
#define SPR_DCBFR       (SPRGROUP_DC + 2)
119
#define SPR_DCBIR       (SPRGROUP_DC + 3)
120
#define SPR_DCBWR       (SPRGROUP_DC + 4)
121
#define SPR_DCBLR       (SPRGROUP_DC + 5)
122
#define SPR_DCR_BASE(WAY)       (SPRGROUP_DC + 0x200 + (WAY) * 0x200)
123
#define SPR_DCR_LAST(WAY)       (SPRGROUP_DC + 0x3ff + (WAY) * 0x200)
124
 
125
/* Instruction cache group */
126
#define SPR_ICCR        (SPRGROUP_IC + 0)
127
#define SPR_ICBPR       (SPRGROUP_IC + 1)
128
#define SPR_ICBIR       (SPRGROUP_IC + 2)
129
#define SPR_ICBLR       (SPRGROUP_IC + 3)
130
#define SPR_ICR_BASE(WAY)       (SPRGROUP_IC + 0x200 + (WAY) * 0x200)
131
#define SPR_ICR_LAST(WAY)       (SPRGROUP_IC + 0x3ff + (WAY) * 0x200)
132
 
133
/* MAC group */
134
#define SPR_MACLO       (SPRGROUP_MAC + 1)
135
#define SPR_MACHI       (SPRGROUP_MAC + 2)
136
 
137
/* Debug group */
138
#define SPR_DVR(N)      (SPRGROUP_D + (N))
139
#define SPR_DCR(N)      (SPRGROUP_D + 8 + (N))
140
#define SPR_DMR1        (SPRGROUP_D + 16)
141
#define SPR_DMR2        (SPRGROUP_D + 17)
142
#define SPR_DWCR0       (SPRGROUP_D + 18)
143
#define SPR_DWCR1       (SPRGROUP_D + 19)
144
#define SPR_DSR         (SPRGROUP_D + 20)
145
#define SPR_DRR         (SPRGROUP_D + 21)
146
 
147
/* Performance counters group */
148
#define SPR_PCCR(N)     (SPRGROUP_PC + (N))
149
#define SPR_PCMR(N)     (SPRGROUP_PC + 8 + (N))
150
 
151
/* Power management group */
152
#define SPR_PMR (SPRGROUP_PM + 0)
153
 
154
/* PIC group */
155
#define SPR_PICMR (SPRGROUP_PIC + 0)
156
#define SPR_PICSR (SPRGROUP_PIC + 2)
157
 
158
/* Tick Timer group */
159
#define SPR_TTMR (SPRGROUP_TT + 0)
160
#define SPR_TTCR (SPRGROUP_TT + 1)
161
 
162
/*
163
 * Bit definitions for the Version Register
164
 *
165
 */
166 233 julius
#define SPR_VR_VER      0xff000000  /* Processor version */
167
#define SPR_VR_CFG      0x00ff0000  /* Processor configuration */
168 385 jeremybenn
#define SPR_VR_RES      0x0000ffc0  /* Reserved */
169 90 jeremybenn
#define SPR_VR_REV      0x0000003f  /* Processor revision */
170
 
171 233 julius
#define SPR_VR_VER_OFF  24
172
#define SPR_VR_CFG_OFF  16
173
#define SPR_VR_REV_OFF  0
174
 
175 90 jeremybenn
/*
176
 * Bit definitions for the Unit Present Register
177
 *
178
 */
179
#define SPR_UPR_UP         0x00000001  /* UPR present */
180
#define SPR_UPR_DCP        0x00000002  /* Data cache present */
181
#define SPR_UPR_ICP        0x00000004  /* Instruction cache present */
182
#define SPR_UPR_DMP        0x00000008  /* Data MMU present */
183
#define SPR_UPR_IMP        0x00000010  /* Instruction MMU present */
184
#define SPR_UPR_MP         0x00000020  /* MAC present */
185
#define SPR_UPR_DUP        0x00000040  /* Debug unit present */
186
#define SPR_UPR_PCUP       0x00000080  /* Performance counters unit present */
187
#define SPR_UPR_PMP        0x00000100  /* Power management present */
188
#define SPR_UPR_PICP       0x00000200  /* PIC present */
189
#define SPR_UPR_TTP        0x00000400  /* Tick timer present */
190
#define SPR_UPR_RES        0x00fe0000  /* Reserved */
191
#define SPR_UPR_CUP        0xff000000  /* Context units present */
192
 
193
/*
194
 * JPB: Bit definitions for the CPU configuration register
195
 *
196
 */
197
#define SPR_CPUCFGR_NSGF   0x0000000f  /* Number of shadow GPR files */
198
#define SPR_CPUCFGR_CGF    0x00000010  /* Custom GPR file */
199
#define SPR_CPUCFGR_OB32S  0x00000020  /* ORBIS32 supported */
200
#define SPR_CPUCFGR_OB64S  0x00000040  /* ORBIS64 supported */
201
#define SPR_CPUCFGR_OF32S  0x00000080  /* ORFPX32 supported */
202
#define SPR_CPUCFGR_OF64S  0x00000100  /* ORFPX64 supported */
203
#define SPR_CPUCFGR_OV64S  0x00000200  /* ORVDX64 supported */
204
#define SPR_CPUCFGR_RES    0xfffffc00  /* Reserved */
205
 
206
/*
207
 * JPB: Bit definitions for the Debug configuration register and other
208
 * constants.
209
 *
210
 */
211
 
212
#define SPR_DCFGR_NDP      0x00000007  /* Number of matchpoints mask */
213
#define SPR_DCFGR_NDP1     0x00000000  /* One matchpoint supported */
214
#define SPR_DCFGR_NDP2     0x00000001  /* Two matchpoints supported */
215
#define SPR_DCFGR_NDP3     0x00000002  /* Three matchpoints supported */
216
#define SPR_DCFGR_NDP4     0x00000003  /* Four matchpoints supported */
217
#define SPR_DCFGR_NDP5     0x00000004  /* Five matchpoints supported */
218
#define SPR_DCFGR_NDP6     0x00000005  /* Six matchpoints supported */
219
#define SPR_DCFGR_NDP7     0x00000006  /* Seven matchpoints supported */
220
#define SPR_DCFGR_NDP8     0x00000007  /* Eight matchpoints supported */
221 233 julius
#define SPR_DCFGR_WPCI     0x00000008  /* Watchpoint counters implemented */
222 90 jeremybenn
 
223
#define MATCHPOINTS_TO_NDP(n) (1 == n ? SPR_DCFGR_NDP1 : \
224
                               2 == n ? SPR_DCFGR_NDP2 : \
225
                               3 == n ? SPR_DCFGR_NDP3 : \
226
                               4 == n ? SPR_DCFGR_NDP4 : \
227
                               5 == n ? SPR_DCFGR_NDP5 : \
228
                               6 == n ? SPR_DCFGR_NDP6 : \
229
                               7 == n ? SPR_DCFGR_NDP7 : SPR_DCFGR_NDP8)
230
#define MAX_MATCHPOINTS  8
231
#define MAX_WATCHPOINTS  (MAX_MATCHPOINTS + 2)
232
 
233
/*
234
 * Bit definitions for the Supervision Register
235
 *
236
 */
237
#define SPR_SR_SM          0x00000001  /* Supervisor Mode */
238
#define SPR_SR_TEE         0x00000002  /* Tick timer Exception Enable */
239
#define SPR_SR_IEE         0x00000004  /* Interrupt Exception Enable */
240
#define SPR_SR_DCE         0x00000008  /* Data Cache Enable */
241
#define SPR_SR_ICE         0x00000010  /* Instruction Cache Enable */
242
#define SPR_SR_DME         0x00000020  /* Data MMU Enable */
243
#define SPR_SR_IME         0x00000040  /* Instruction MMU Enable */
244
#define SPR_SR_LEE         0x00000080  /* Little Endian Enable */
245
#define SPR_SR_CE          0x00000100  /* CID Enable */
246
#define SPR_SR_F           0x00000200  /* Condition Flag */
247
#define SPR_SR_CY          0x00000400  /* Carry flag */
248
#define SPR_SR_OV          0x00000800  /* Overflow flag */
249
#define SPR_SR_OVE         0x00001000  /* Overflow flag Exception */
250
#define SPR_SR_DSX         0x00002000  /* Delay Slot Exception */
251
#define SPR_SR_EPH         0x00004000  /* Exception Prefix High */
252
#define SPR_SR_FO          0x00008000  /* Fixed one */
253
#define SPR_SR_SUMRA       0x00010000  /* Supervisor SPR read access */
254
#define SPR_SR_RES         0x0ffe0000  /* Reserved */
255
#define SPR_SR_CID         0xf0000000  /* Context ID */
256
 
257
/*
258
 * Bit definitions for the Data MMU Control Register
259
 *
260
 */
261
#define SPR_DMMUCR_P2S     0x0000003e  /* Level 2 Page Size */
262
#define SPR_DMMUCR_P1S     0x000007c0  /* Level 1 Page Size */
263
#define SPR_DMMUCR_VADDR_WIDTH  0x0000f800  /* Virtual ADDR Width */
264
#define SPR_DMMUCR_PADDR_WIDTH  0x000f0000  /* Physical ADDR Width */
265
 
266
/*
267
 * Bit definitions for the Instruction MMU Control Register
268
 *
269
 */
270
#define SPR_IMMUCR_P2S     0x0000003e  /* Level 2 Page Size */
271
#define SPR_IMMUCR_P1S     0x000007c0  /* Level 1 Page Size */
272
#define SPR_IMMUCR_VADDR_WIDTH  0x0000f800  /* Virtual ADDR Width */
273
#define SPR_IMMUCR_PADDR_WIDTH  0x000f0000  /* Physical ADDR Width */
274
 
275
/*
276
 * Bit definitions for the Data TLB Match Register
277
 *
278
 */
279
#define SPR_DTLBMR_V       0x00000001  /* Valid */
280
#define SPR_DTLBMR_PL1     0x00000002  /* Page Level 1 (if 0 then PL2) */
281
#define SPR_DTLBMR_CID     0x0000003c  /* Context ID */
282
#define SPR_DTLBMR_LRU     0x000000c0  /* Least Recently Used */
283
#define SPR_DTLBMR_VPN     0xfffff000  /* Virtual Page Number */
284
 
285
/*
286
 * Bit definitions for the Data TLB Translate Register
287
 *
288
 */
289
#define SPR_DTLBTR_CC      0x00000001  /* Cache Coherency */
290
#define SPR_DTLBTR_CI      0x00000002  /* Cache Inhibit */
291
#define SPR_DTLBTR_WBC     0x00000004  /* Write-Back Cache */
292
#define SPR_DTLBTR_WOM     0x00000008  /* Weakly-Ordered Memory */
293
#define SPR_DTLBTR_A       0x00000010  /* Accessed */
294
#define SPR_DTLBTR_D       0x00000020  /* Dirty */
295
#define SPR_DTLBTR_URE     0x00000040  /* User Read Enable */
296
#define SPR_DTLBTR_UWE     0x00000080  /* User Write Enable */
297
#define SPR_DTLBTR_SRE     0x00000100  /* Supervisor Read Enable */
298
#define SPR_DTLBTR_SWE     0x00000200  /* Supervisor Write Enable */
299
#define SPR_DTLBTR_PPN     0xfffff000  /* Physical Page Number */
300
 
301
/*
302
 * Bit definitions for the Instruction TLB Match Register
303
 *
304
 */
305
#define SPR_ITLBMR_V       0x00000001  /* Valid */
306
#define SPR_ITLBMR_PL1     0x00000002  /* Page Level 1 (if 0 then PL2) */
307
#define SPR_ITLBMR_CID     0x0000003c  /* Context ID */
308
#define SPR_ITLBMR_LRU     0x000000c0  /* Least Recently Used */
309
#define SPR_ITLBMR_VPN     0xfffff000  /* Virtual Page Number */
310
 
311
/*
312
 * Bit definitions for the Instruction TLB Translate Register
313
 *
314
 */
315
#define SPR_ITLBTR_CC      0x00000001  /* Cache Coherency */
316
#define SPR_ITLBTR_CI      0x00000002  /* Cache Inhibit */
317
#define SPR_ITLBTR_WBC     0x00000004  /* Write-Back Cache */
318
#define SPR_ITLBTR_WOM     0x00000008  /* Weakly-Ordered Memory */
319
#define SPR_ITLBTR_A       0x00000010  /* Accessed */
320
#define SPR_ITLBTR_D       0x00000020  /* Dirty */
321
#define SPR_ITLBTR_SXE     0x00000040  /* User Read Enable */
322
#define SPR_ITLBTR_UXE     0x00000080  /* User Write Enable */
323
#define SPR_ITLBTR_PPN     0xfffff000  /* Physical Page Number */
324
 
325
/*
326
 * Bit definitions for Data Cache Control register
327
 *
328
 */
329
#define SPR_DCCR_EW        0x000000ff  /* Enable ways */
330
 
331
/*
332
 * Bit definitions for Insn Cache Control register
333
 *
334
 */
335
#define SPR_ICCR_EW        0x000000ff  /* Enable ways */
336
 
337
/*
338
 * Bit definitions for Data Cache Configuration Register
339
 *
340
 */
341
 
342
#define SPR_DCCFGR_NCW          0x00000007
343
#define SPR_DCCFGR_NCS          0x00000078
344
#define SPR_DCCFGR_CBS          0x00000080
345
#define SPR_DCCFGR_CWS          0x00000100
346
#define SPR_DCCFGR_CCRI         0x00000200
347
#define SPR_DCCFGR_CBIRI        0x00000400
348
#define SPR_DCCFGR_CBPRI        0x00000800
349
#define SPR_DCCFGR_CBLRI        0x00001000
350
#define SPR_DCCFGR_CBFRI        0x00002000
351
#define SPR_DCCFGR_CBWBRI       0x00004000
352
 
353 233 julius
#define SPR_DCCFGR_NCW_OFF      0
354
#define SPR_DCCFGR_NCS_OFF      3
355
#define SPR_DCCFGR_CBS_OFF      7
356
 
357 90 jeremybenn
/*
358
 * Bit definitions for Instruction Cache Configuration Register
359
 *
360
 */
361
#define SPR_ICCFGR_NCW          0x00000007
362
#define SPR_ICCFGR_NCS          0x00000078
363
#define SPR_ICCFGR_CBS          0x00000080
364
#define SPR_ICCFGR_CCRI         0x00000200
365
#define SPR_ICCFGR_CBIRI        0x00000400
366
#define SPR_ICCFGR_CBPRI        0x00000800
367
#define SPR_ICCFGR_CBLRI        0x00001000
368
 
369 233 julius
#define SPR_ICCFGR_NCW_OFF      0
370
#define SPR_ICCFGR_NCS_OFF      3
371
#define SPR_ICCFGR_CBS_OFF      7
372
 
373 90 jeremybenn
/*
374
 * Bit definitions for Data MMU Configuration Register
375
 *
376
 */
377
 
378
#define SPR_DMMUCFGR_NTW        0x00000003
379
#define SPR_DMMUCFGR_NTS        0x0000001C
380
#define SPR_DMMUCFGR_NAE        0x000000E0
381
#define SPR_DMMUCFGR_CRI        0x00000100
382
#define SPR_DMMUCFGR_PRI        0x00000200
383
#define SPR_DMMUCFGR_TEIRI      0x00000400
384
#define SPR_DMMUCFGR_HTR        0x00000800
385
 
386 233 julius
#define SPR_DMMUCFGR_NTW_OFF    0
387
#define SPR_DMMUCFGR_NTS_OFF    2
388
 
389 90 jeremybenn
/*
390
 * Bit definitions for Instruction MMU Configuration Register
391
 *
392
 */
393
 
394
#define SPR_IMMUCFGR_NTW        0x00000003
395
#define SPR_IMMUCFGR_NTS        0x0000001C
396
#define SPR_IMMUCFGR_NAE        0x000000E0
397
#define SPR_IMMUCFGR_CRI        0x00000100
398
#define SPR_IMMUCFGR_PRI        0x00000200
399
#define SPR_IMMUCFGR_TEIRI      0x00000400
400
#define SPR_IMMUCFGR_HTR        0x00000800
401
 
402 233 julius
#define SPR_IMMUCFGR_NTW_OFF    0
403
#define SPR_IMMUCFGR_NTS_OFF    2
404
 
405 90 jeremybenn
/*
406
 * Bit definitions for Debug Control registers
407
 *
408
 */
409
#define SPR_DCR_DP      0x00000001  /* DVR/DCR present */
410
#define SPR_DCR_CC      0x0000000e  /* Compare condition */
411
#define SPR_DCR_SC      0x00000010  /* Signed compare */
412
#define SPR_DCR_CT      0x000000e0  /* Compare to */
413
 
414
/* Bit results with SPR_DCR_CC mask */
415
#define SPR_DCR_CC_MASKED 0x00000000
416
#define SPR_DCR_CC_EQUAL  0x00000002
417
#define SPR_DCR_CC_LESS   0x00000004
418
#define SPR_DCR_CC_LESSE  0x00000006
419
#define SPR_DCR_CC_GREAT  0x00000008
420
#define SPR_DCR_CC_GREATE 0x0000000a
421
#define SPR_DCR_CC_NEQUAL 0x0000000c
422
 
423
/* Bit results with SPR_DCR_CT mask */
424
#define SPR_DCR_CT_DISABLED 0x00000000
425
#define SPR_DCR_CT_IFEA     0x00000020
426
#define SPR_DCR_CT_LEA      0x00000040
427
#define SPR_DCR_CT_SEA      0x00000060
428
#define SPR_DCR_CT_LD       0x00000080
429
#define SPR_DCR_CT_SD       0x000000a0
430
#define SPR_DCR_CT_LSEA     0x000000c0
431
#define SPR_DCR_CT_LSD      0x000000e0
432
/* SPR_DCR_CT_LSD doesn't seem to be implemented anywhere in or1ksim. 2004-1-30 HP */
433
 
434
/*
435
 * Bit definitions for Debug Mode 1 register
436
 *
437
 */
438
#define SPR_DMR1_CW       0x000fffff  /* Chain register pair data */
439
#define SPR_DMR1_CW0_AND  0x00000001
440
#define SPR_DMR1_CW0_OR   0x00000002
441
#define SPR_DMR1_CW0      (SPR_DMR1_CW0_AND | SPR_DMR1_CW0_OR)
442
#define SPR_DMR1_CW1_AND  0x00000004
443
#define SPR_DMR1_CW1_OR   0x00000008
444
#define SPR_DMR1_CW1      (SPR_DMR1_CW1_AND | SPR_DMR1_CW1_OR)
445
#define SPR_DMR1_CW2_AND  0x00000010
446
#define SPR_DMR1_CW2_OR   0x00000020
447
#define SPR_DMR1_CW2      (SPR_DMR1_CW2_AND | SPR_DMR1_CW2_OR)
448
#define SPR_DMR1_CW3_AND  0x00000040
449
#define SPR_DMR1_CW3_OR   0x00000080
450
#define SPR_DMR1_CW3      (SPR_DMR1_CW3_AND | SPR_DMR1_CW3_OR)
451
#define SPR_DMR1_CW4_AND  0x00000100
452
#define SPR_DMR1_CW4_OR   0x00000200
453
#define SPR_DMR1_CW4      (SPR_DMR1_CW4_AND | SPR_DMR1_CW4_OR)
454
#define SPR_DMR1_CW5_AND  0x00000400
455
#define SPR_DMR1_CW5_OR   0x00000800
456
#define SPR_DMR1_CW5      (SPR_DMR1_CW5_AND | SPR_DMR1_CW5_OR)
457
#define SPR_DMR1_CW6_AND  0x00001000
458
#define SPR_DMR1_CW6_OR   0x00002000
459
#define SPR_DMR1_CW6      (SPR_DMR1_CW6_AND | SPR_DMR1_CW6_OR)
460
#define SPR_DMR1_CW7_AND  0x00004000
461
#define SPR_DMR1_CW7_OR   0x00008000
462
#define SPR_DMR1_CW7      (SPR_DMR1_CW7_AND | SPR_DMR1_CW7_OR)
463
#define SPR_DMR1_CW8_AND  0x00010000
464
#define SPR_DMR1_CW8_OR   0x00020000
465
#define SPR_DMR1_CW8      (SPR_DMR1_CW8_AND | SPR_DMR1_CW8_OR)
466
#define SPR_DMR1_CW9_AND  0x00040000
467
#define SPR_DMR1_CW9_OR   0x00080000
468
#define SPR_DMR1_CW9      (SPR_DMR1_CW9_AND | SPR_DMR1_CW9_OR)
469
#define SPR_DMR1_RES1      0x00300000  /* Reserved */
470
#define SPR_DMR1_ST       0x00400000  /* Single-step trace*/
471
#define SPR_DMR1_BT       0x00800000  /* Branch trace */
472
#define SPR_DMR1_RES2     0xff000000  /* Reserved */
473
 
474
/*
475
 * Bit definitions for Debug Mode 2 register. AWTC and WGB corrected by JPB
476
 *
477
 */
478
#define SPR_DMR2_WCE0      0x00000001  /* Watchpoint counter 0 enable */
479
#define SPR_DMR2_WCE1      0x00000002  /* Watchpoint counter 0 enable */
480
#define SPR_DMR2_AWTC      0x00000ffc  /* Assign watchpoints to counters */
481
#define SPR_DMR2_AWTC_OFF           2  /* Bit offset to AWTC field */
482
#define SPR_DMR2_WGB       0x003ff000  /* Watchpoints generating breakpoint */
483
#define SPR_DMR2_WGB_OFF           12  /* Bit offset to WGB field */
484
#define SPR_DMR2_WBS       0xffc00000  /* JPB: Watchpoint status */
485
#define SPR_DMR2_WBS_OFF           22  /* Bit offset to WBS field */
486
 
487
/*
488
 * Bit definitions for Debug watchpoint counter registers
489
 *
490
 */
491
#define SPR_DWCR_COUNT      0x0000ffff  /* Count */
492
#define SPR_DWCR_MATCH      0xffff0000  /* Match */
493
#define SPR_DWCR_MATCH_OFF          16  /* Match bit offset */
494
 
495
/*
496
 * Bit definitions for Debug stop register
497
 *
498
 */
499
#define SPR_DSR_RSTE    0x00000001  /* Reset exception */
500
#define SPR_DSR_BUSEE   0x00000002  /* Bus error exception */
501
#define SPR_DSR_DPFE    0x00000004  /* Data Page Fault exception */
502
#define SPR_DSR_IPFE    0x00000008  /* Insn Page Fault exception */
503
#define SPR_DSR_TTE     0x00000010  /* Tick Timer exception */
504
#define SPR_DSR_AE      0x00000020  /* Alignment exception */
505
#define SPR_DSR_IIE     0x00000040  /* Illegal Instruction exception */
506
#define SPR_DSR_IE      0x00000080  /* Interrupt exception */
507
#define SPR_DSR_DME     0x00000100  /* DTLB miss exception */
508
#define SPR_DSR_IME     0x00000200  /* ITLB miss exception */
509
#define SPR_DSR_RE      0x00000400  /* Range exception */
510
#define SPR_DSR_SCE     0x00000800  /* System call exception */
511 233 julius
#define SPR_DSR_FPE     0x00001000  /* Floating Point Exception */
512 90 jeremybenn
#define SPR_DSR_TE      0x00002000  /* Trap exception */
513
 
514
/*
515
 * Bit definitions for Debug reason register
516
 *
517
 */
518
#define SPR_DRR_RSTE    0x00000001  /* Reset exception */
519
#define SPR_DRR_BUSEE   0x00000002  /* Bus error exception */
520
#define SPR_DRR_DPFE    0x00000004  /* Data Page Fault exception */
521
#define SPR_DRR_IPFE    0x00000008  /* Insn Page Fault exception */
522
#define SPR_DRR_TTE     0x00000010  /* Tick Timer exception */
523
#define SPR_DRR_AE      0x00000020  /* Alignment exception */
524
#define SPR_DRR_IIE     0x00000040  /* Illegal Instruction exception */
525
#define SPR_DRR_IE      0x00000080  /* Interrupt exception */
526
#define SPR_DRR_DME     0x00000100  /* DTLB miss exception */
527
#define SPR_DRR_IME     0x00000200  /* ITLB miss exception */
528
#define SPR_DRR_RE      0x00000400  /* Range exception */
529
#define SPR_DRR_SCE     0x00000800  /* System call exception */
530 233 julius
#define SPR_DRR_FPE     0x00001000  /* Floating Point Exception */
531
#define SPR_DRR_TE      0x00002000  /* Trap exception */
532 90 jeremybenn
 
533
/*
534
 * Bit definitions for Performance counters mode registers
535
 *
536
 */
537
#define SPR_PCMR_CP     0x00000001  /* Counter present */
538
#define SPR_PCMR_UMRA   0x00000002  /* User mode read access */
539
#define SPR_PCMR_CISM   0x00000004  /* Count in supervisor mode */
540
#define SPR_PCMR_CIUM   0x00000008  /* Count in user mode */
541
#define SPR_PCMR_LA     0x00000010  /* Load access event */
542
#define SPR_PCMR_SA     0x00000020  /* Store access event */
543
#define SPR_PCMR_IF     0x00000040  /* Instruction fetch event*/
544
#define SPR_PCMR_DCM    0x00000080  /* Data cache miss event */
545
#define SPR_PCMR_ICM    0x00000100  /* Insn cache miss event */
546
#define SPR_PCMR_IFS    0x00000200  /* Insn fetch stall event */
547
#define SPR_PCMR_LSUS   0x00000400  /* LSU stall event */
548
#define SPR_PCMR_BS     0x00000800  /* Branch stall event */
549
#define SPR_PCMR_DTLBM  0x00001000  /* DTLB miss event */
550
#define SPR_PCMR_ITLBM  0x00002000  /* ITLB miss event */
551
#define SPR_PCMR_DDS    0x00004000  /* Data dependency stall event */
552
#define SPR_PCMR_WPE    0x03ff8000  /* Watchpoint events */
553
 
554
/*
555
 * Bit definitions for the Power management register
556
 *
557
 */
558
#define SPR_PMR_SDF     0x0000000f  /* Slow down factor */
559
#define SPR_PMR_DME     0x00000010  /* Doze mode enable */
560
#define SPR_PMR_SME     0x00000020  /* Sleep mode enable */
561
#define SPR_PMR_DCGE    0x00000040  /* Dynamic clock gating enable */
562
#define SPR_PMR_SUME    0x00000080  /* Suspend mode enable */
563
 
564
/*
565
 * Bit definitions for PICMR
566
 *
567
 */
568
#define SPR_PICMR_IUM   0xfffffffc  /* Interrupt unmask */
569
 
570
/*
571
 * Bit definitions for PICSR
572
 *
573
 */
574
#define SPR_PICSR_IS    0xffffffff  /* Interrupt status */
575
 
576
/*
577
 * Bit definitions for Tick Timer Control Register
578
 *
579
 */
580
#define SPR_TTCR_PERIOD 0x0fffffff  /* Time Period */
581
#define SPR_TTMR_PERIOD SPR_TTCR_PERIOD
582
#define SPR_TTMR_IP     0x10000000  /* Interrupt Pending */
583
#define SPR_TTMR_IE     0x20000000  /* Interrupt Enable */
584
#define SPR_TTMR_DI     0x00000000  /* Disabled */
585
#define SPR_TTMR_RT     0x40000000  /* Restart tick */
586
#define SPR_TTMR_SR     0x80000000  /* Single run */
587
#define SPR_TTMR_CR     0xc0000000  /* Continuous run */
588
#define SPR_TTMR_M      0xc0000000  /* Tick mode */
589
 
590
/*
591 233 julius
 * Bit definitions for the FP Control Status Register
592
 *
593
 */
594
#define SPR_FPCSR_FPEE  0x00000001  /* Floating Point Exception Enable */
595
#define SPR_FPCSR_RM    0x00000006  /* Rounding Mode */
596
#define SPR_FPCSR_OVF   0x00000008  /* Overflow Flag */
597
#define SPR_FPCSR_UNF   0x00000010  /* Underflow Flag */
598
#define SPR_FPCSR_SNF   0x00000020  /* SNAN Flag */
599
#define SPR_FPCSR_QNF   0x00000040  /* QNAN Flag */
600
#define SPR_FPCSR_ZF    0x00000080  /* Zero Flag */
601
#define SPR_FPCSR_IXF   0x00000100  /* Inexact Flag */
602
#define SPR_FPCSR_IVF   0x00000200  /* Invalid Flag */
603
#define SPR_FPCSR_INF   0x00000400  /* Infinity Flag */
604
#define SPR_FPCSR_DZF   0x00000800  /* Divide By Zero Flag */
605
#define SPR_FPCSR_ALLF (SPR_FPCSR_OVF | SPR_FPCSR_UNF | SPR_FPCSR_SNF | \
606
                        SPR_FPCSR_QNF | SPR_FPCSR_ZF | SPR_FPCSR_IXF |  \
607
                        SPR_FPCSR_IVF | SPR_FPCSR_INF | SPR_FPCSR_DZF)
608
 
609
#define FPCSR_RM_RN (0<<1)
610
#define FPCSR_RM_RZ (1<<1)
611
#define FPCSR_RM_RIP (2<<1)
612
#define FPCSR_RM_RIN (3<<1)
613
 
614
/*
615 90 jeremybenn
 * l.nop constants
616
 *
617
 */
618
#define NOP_NOP          0x0000      /* Normal nop instruction */
619
#define NOP_EXIT         0x0001      /* End of simulation */
620
#define NOP_REPORT       0x0002      /* Simple report */
621 233 julius
/*#define NOP_PRINTF       0x0003       Simprintf instruction (obsolete)*/
622 90 jeremybenn
#define NOP_PUTC         0x0004      /* JPB: Simputc instruction */
623
#define NOP_CNT_RESET    0x0005      /* Reset statistics counters */
624
#define NOP_GET_TICKS    0x0006      /* JPB: Get # ticks running */
625
#define NOP_GET_PS       0x0007      /* JPB: Get picosecs/cycle */
626
#define NOP_REPORT_FIRST 0x0400      /* Report with number */
627
#define NOP_REPORT_LAST  0x03ff      /* Report with number */
628 233 julius
 
629
#endif  /* SPR_DEFS__H */

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