OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [bench/] [verilog/] [include/] [eth_stim.v] - Blame information for rev 439

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 44 julius
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3 412 julius
////  Ethernet MAC Stimulus                                       ////
4 44 julius
////                                                              ////
5
////  Description                                                 ////
6
////  Ethernet MAC stimulus tasks. Taken from the project         ////
7
////  testbench in the ethmac core.                               ////
8
////                                                              ////
9
////  To Do:                                                      ////
10
////                                                              ////
11
////                                                              ////
12
////  Author(s):                                                  ////
13
////      - Tadej Markovic, tadej@opencores.org                   ////
14
////      - Igor Mohor,     igorM@opencores.org                   ////
15 412 julius
////      - Julius Baxter   julius.baxter@orsoc.se                ////
16 44 julius
////                                                              ////
17
////                                                              ////
18
//////////////////////////////////////////////////////////////////////
19
////                                                              ////
20
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
21
////                                                              ////
22
//// This source file may be used and distributed without         ////
23
//// restriction provided that this copyright statement is not    ////
24
//// removed from the file and that any derivative work contains  ////
25
//// the original copyright notice and the associated disclaimer. ////
26
////                                                              ////
27
//// This source file is free software; you can redistribute it   ////
28
//// and/or modify it under the terms of the GNU Lesser General   ////
29
//// Public License as published by the Free Software Foundation; ////
30
//// either version 2.1 of the License, or (at your option) any   ////
31
//// later version.                                               ////
32
////                                                              ////
33
//// This source is distributed in the hope that it will be       ////
34
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
35
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
36
//// PURPOSE.  See the GNU Lesser General Public License for more ////
37
//// details.                                                     ////
38
////                                                              ////
39
//// You should have received a copy of the GNU Lesser General    ////
40
//// Public License along with this source; if not, download it   ////
41
//// from http://www.opencores.org/lgpl.shtml                     ////
42
////                                                              ////
43
//////////////////////////////////////////////////////////////////////
44 412 julius
`define TIME $display("Time: %0t", $time)
45 44 julius
 
46 412 julius
// Defines for ethernet test to trigger sending/receiving
47
// Is straight forward when using RTL design, but if using netlist then paths to
48
// the RX/TX enabled bits depend on synthesis tool, etc, but ones here appear to
49
// work with design put through Synplify, with hierarchy maintained.
50
`define ETH_TOP dut.ethmac0
51
`define ETH_BD_RAM_PATH `ETH_TOP.wishbone.bd_ram
52
`define ETH_MODER_PATH `ETH_TOP.ethreg1.MODER_0
53 44 julius
 
54 412 julius
`ifdef RTL_SIM
55
 `ifdef ethmac_IS_GATELEVEL
56
  `define ETH_MODER_TXEN_BIT `ETH_MODER_PATH.r_TxEn;
57
  `define ETH_MODER_RXEN_BIT `ETH_MODER_PATH.r_RxEn;
58
 `else
59
  `define ETH_MODER_TXEN_BIT `ETH_MODER_PATH.DataOut[1];
60
  `define ETH_MODER_RXEN_BIT `ETH_MODER_PATH.DataOut[0];
61
 `endif
62
`endif
63
 
64
`ifdef GATE_SIM
65
 `define ETH_MODER_TXEN_BIT `ETH_MODER_PATH.r_TxEn;
66
 `define ETH_MODER_RXEN_BIT `ETH_MODER_PATH.r_RxEn;
67
`endif
68
 
69
reg [15:0] eth_stim_rx_packet_length;
70 44 julius
reg [7:0] st_data;
71 412 julius
reg [31:0] lfsr;
72
integer lfsr_last_byte;
73
 
74
// Is number of ethernet packets to send if doing the eth-rx test.
75
parameter eth_stim_num_rx_only_num_packets = 500; // Set to 0 for continuous RX
76
parameter eth_stim_num_rx_only_packet_size = 512;
77
parameter eth_stim_num_rx_only_packet_size_change = 2'b01;  // 2'b01: Increment
78
parameter eth_stim_num_rx_only_packet_size_change_amount = 1;
79 439 julius
parameter eth_stim_num_rx_only_IPG = 800000000; // ns
80 412 julius
 
81
// Do call/response test
82
reg eth_stim_do_rx_reponse_to_tx;
83
 
84
 
85
parameter num_tx_bds = 16;
86
parameter num_tx_bds_mask = 4'hf;
87
parameter num_rx_bds = 16;
88
parameter num_rx_bds_mask = 4'hf;
89
parameter max_eth_packet_size = 16'h0600;
90
 
91
// If running eth-rxtxbig test (sending and receiving maximum packets), then
92
// set this parameter to the max packet size, otherwise min packet size
93
//parameter rx_while_tx_min_packet_size = max_eth_packet_size;
94
parameter rx_while_tx_min_packet_size = 32;
95
 
96
// Use the smallest possible IPG
97
parameter eth_stim_use_min_IPG = 0;
98
parameter eth_stim_IPG_delay_max = 500_000; // Maximum 500uS ga
99
//parameter eth_stim_IPG_delay_max = 100_000_000; // Maximum 100mS between packets
100
parameter eth_stim_IPG_min_10mb = 9600; // 9.6 uS
101
parameter eth_stim_IPG_min_100mb = 800; // 860+~100 = 960 nS 100MBit min IPG
102
parameter eth_stim_check_rx_packet_contents = 1;
103
parameter eth_stim_check_tx_packet_contents = 1;
104
 
105
parameter eth_inject_errors = 0;
106
 
107
// When running simulations where you don't want to feed packets to the design
108
// like this...
109
parameter eth_stim_disable_rx_stim = 0;
110
 
111
// Delay between seeing that the buffer descriptor for an RX packet says it's
112
// been received and ending up in the memory.
113
// For 25MHz sdram controller, use following:
114
//parameter  Td_rx_packet_check = (`BOARD_CLOCK_PERIOD * 2000);
115
// For 64MHz sdram controller, use following:
116
parameter  Td_rx_packet_check = (`BOARD_CLOCK_PERIOD * 500);
117
 
118
 
119
 
120
integer expected_rxbd;// init to 0
121
integer expected_txbd;
122
 
123
wire ethmac_rxen;
124
wire ethmac_txen;
125
assign ethmac_rxen = eth_stim_disable_rx_stim ? 0 : `ETH_MODER_RXEN_BIT;
126
assign ethmac_txen = `ETH_MODER_TXEN_BIT;
127
 
128
integer eth_rx_num_packets_sent = 0;
129
integer eth_rx_num_packets_checked = 0;
130
integer num_tx_packets = 1;
131
 
132
integer rx_packet_lengths [0:1023]; // Array of packet lengths
133
 
134
 
135
integer speed_loop;
136
 
137
// When txen is (re)enabled, the tx bd pointer goes back to 0
138
always @(posedge ethmac_txen)
139
  expected_txbd = 0;
140
 
141
   reg  eth_stim_waiting;
142
 
143 44 julius
initial
144
  begin
145 412 julius
     #1;
146
     //lfsr = 32'h84218421; // Init pseudo lfsr
147
     lfsr = 32'h00700001; // Init pseudo lfsr
148
     lfsr_last_byte = 0;
149
 
150
     eth_stim_waiting = 1;
151
     expected_rxbd = num_tx_bds; // init this here
152 44 julius
 
153 412 julius
     eth_stim_do_rx_reponse_to_tx = 0;
154 44 julius
 
155
 
156 412 julius
     while (eth_stim_waiting) // Loop, waiting for enabling of MAC by software
157
       begin
158
          #100;
159
          // If RX enable and not TX enable...
160
          if(ethmac_rxen === 1'b1 & !(ethmac_txen===1'b1))
161
            begin
162
               if (eth_inject_errors)
163
                 begin
164
                    do_rx_only_stim(16, 64, 0, 0);
165
                    do_rx_only_stim(128, 64, 1'b1, 8);
166
                    do_rx_only_stim(256, 64, 1'b1, 4);
167
                    eth_stim_waiting = 0;
168
                 end
169
               else
170
                 begin
171
                    //do_rx_only_stim(eth_stim_num_rx_only_num_packets, 
172
                    //eth_stim_num_rx_only_packet_size, 0, 0);
173 44 julius
 
174 412 julius
                    // Call packet send loop directly. No error injection.
175
                    send_packet_loop(eth_stim_num_rx_only_num_packets,
176
                                     eth_stim_num_rx_only_packet_size,
177
                                     eth_stim_num_rx_only_packet_size_change,
178
                                     eth_stim_num_rx_only_packet_size_change_amount,
179
                                     eth_phy0.eth_speed,     // Speed
180
                                     eth_stim_num_rx_only_IPG, // IPG
181
                               48'h0012_3456_789a, 48'h0708_090A_0B0C, 1,
182
                               0, 0);
183
 
184
                    eth_stim_waiting = 0;
185
                 end
186
            end // if (ethmac_rxen === 1'b1 & !(ethmac_txen===1'b1))
187
          // If both RX and TX enabled
188
          else if (ethmac_rxen === 1'b1 & ethmac_txen===1'b1)
189
            begin
190
               // Both enabled - let's wait for the first packet transmitted
191
               // to see what stimulus we should provide
192
               while (num_tx_packets==1)
193
                 #1000;
194
 
195
               $display("* ethmac RX/TX test request: %x", eth_phy0.tx_mem[0]);
196
 
197
               // Check the first received byte's value
198
                 case (eth_phy0.tx_mem[0])
199
                   0:
200
                     begin
201
                        // kickoff call/response here
202
                        eth_stim_do_rx_reponse_to_tx = 1;
203
                     end
204
                   default:
205
                     begin
206
                        do_rx_while_tx_stim(1400);
207
                     end
208
                 endcase // case (eth_phy0.tx_mem[0])
209
 
210
               eth_stim_waiting = 0;
211
            end
212
       end // while (eth_stim_waiting)     
213 49 julius
 
214 412 julius
  end // initial begin
215 49 julius
 
216 412 julius
   // Main Ethernet RX testing stimulus task.
217
   // Sends a set of packets at both speeds
218
   task do_rx_only_stim;
219
      input [31:0] num_packets;
220
      input [31:0] start_packet_size;
221
      input        inject_errors;
222
      input [31:0] inject_errors_mod;
223
 
224
      begin
225
 
226
         for(speed_loop=1;speed_loop<3;speed_loop=speed_loop+1)
227
           begin
228
 
229
              send_packet_loop(num_packets, start_packet_size, 2'b01, 1,
230
                               speed_loop[0], 10000,
231
                               48'h0012_3456_789a, 48'h0708_090A_0B0C, 1,
232
                               inject_errors, inject_errors_mod);
233
 
234
           end
235
 
236
      end
237
   endtask // do_rx_stim
238 44 julius
 
239 412 julius
   // Generate RX packets while there's TX going on
240
   // Sends a set of packets at both speeds
241
   task do_rx_while_tx_stim;
242
      input [31:0] num_packets;
243
      reg [31:0] IPG; // Inter-packet gap
244
      reg [31:0] packet_size;
245 44 julius
 
246 412 julius
      integer    j;
247
      begin
248
 
249
         for(j=0;j<num_packets;j=j+1)
250
           begin
251
              // Determine delay between RX packets:
252
 
253
              if (eth_stim_use_min_IPG)
254
                begin
255
                   // Assign based on whether we're in 100mbit or 10mbit mode
256
                   IPG = eth_phy0.eth_speed ? eth_stim_IPG_min_100mb :
257
                         eth_stim_IPG_min_10mb;
258
                   // Add a little bit of variability
259
                   // Add up to 15
260
                   IPG = IPG + ($random & 32'h000000f);
261
                end
262
              else
263
                begin
264
                   IPG = $random;
265
 
266
                   while (IPG > eth_stim_IPG_delay_max)
267
                     IPG = IPG / 2;
268
 
269
 
270
                end
271
              $display("do_rx_while_tx IPG = %0d", IPG);
272
              // Determine size of next packet:
273
              if (rx_while_tx_min_packet_size == max_eth_packet_size)
274
                // We want to transmit biggest packets possible, easy case
275
                packet_size = max_eth_packet_size - 4;
276
              else
277
                begin
278
                   // Constrained random sized packets
279
                   packet_size = $random;
280
 
281
                   while (packet_size > (max_eth_packet_size-4))
282
                     packet_size = packet_size / 2;
283
 
284
                   // Now divide by least significant bits of j
285
                   packet_size = packet_size / {29'd0,j[1:0],1'b1};
286
                   if (packet_size < 60)
287
                     packet_size = packet_size + 60;
288
                end
289
 
290
              $display("do_rx_while_tx packet_size = %0d", packet_size);
291
              send_packet_loop(1, packet_size, 2'b01, 1, eth_phy0.eth_speed,
292
                               IPG, 48'h0012_3456_789a,
293
                               48'h0708_090A_0B0C, 1, 1'b0, 0);
294 44 julius
 
295 412 julius
              // If RX enable went low, wait for it go high again
296
              if (ethmac_rxen===1'b0)
297
                begin
298
 
299
                   while (ethmac_rxen===1'b0)
300
                     begin
301
                        @(posedge ethmac_rxen);
302
                        #10000;
303
                     end
304
 
305
                   // RX disabled and when re-enabled we reset the buffer descriptor number
306
                   expected_rxbd = num_tx_bds;
307 44 julius
 
308 412 julius
                end
309
 
310
           end // for (j=0;j<num_packets;j=j+1)
311
      end
312
   endtask // do_rx_stim
313 44 julius
 
314 412 julius
   // Registers used in detecting transmitted packets
315
   reg eth_stim_tx_loop_keep_polling;
316
   reg [31:0] ethmac_txbd_lenstat, ethmac_last_txbd_lenstat;
317
   reg        eth_stim_detected_packet_tx;
318 44 julius
 
319 412 julius
   // If in call-response mode, whenever we receive a TX packet, we generate
320
   // one and send it back
321
   always @(negedge eth_stim_detected_packet_tx)
322
     begin
323
        if (eth_stim_do_rx_reponse_to_tx & ethmac_rxen)
324
          // Continue if we are enabled
325
          do_rx_response_to_tx();
326
     end
327
 
328
   // Generate RX packet in rsponse to TX packet
329
   task do_rx_response_to_tx;
330
      //input unused;
331
 
332
     reg [31:0] IPG; // Inter-packet gap
333
      reg [31:0] packet_size;
334
 
335
      integer    j;
336
      begin
337 44 julius
 
338 412 julius
         // Get packet size test wants us to send
339
         packet_size = {eth_phy0.tx_mem[0],eth_phy0.tx_mem[1],
340
                        eth_phy0.tx_mem[2],eth_phy0.tx_mem[3]};
341
 
342 44 julius
 
343 412 julius
         IPG = {eth_phy0.tx_mem[4],eth_phy0.tx_mem[5],
344
                eth_phy0.tx_mem[6],eth_phy0.tx_mem[7]};
345
 
346
 
347
         $display("do_rx_response_to_tx IPG = %0d", IPG);
348
         if (packet_size == 0)
349
           begin
350
              // Constrained random sized packets
351
              packet_size = $random;
352
 
353
              while (packet_size > (max_eth_packet_size-4))
354
                packet_size = packet_size / 2;
355
 
356
              if (packet_size < 60)
357
                packet_size = packet_size + 60;
358
           end
359
 
360
         $display("do_rx_response_to_tx packet_size = %0d", packet_size);
361
         send_packet_loop(1, packet_size, 2'b01, 1, eth_phy0.eth_speed,
362
                          IPG, 48'h0012_3456_789a,
363
                          48'h0708_090A_0B0C, 1, 1'b0, 0);
364
 
365
         // If RX enable went low, wait for it go high again
366
         if (ethmac_rxen===1'b0)
367
           begin
368
 
369
              while (ethmac_rxen===1'b0)
370
                begin
371
                   @(posedge ethmac_rxen);
372
                   #10000;
373
                end
374
 
375
              // RX disabled and when re-enabled we reset the buffer 
376
              // descriptor number
377
              expected_rxbd = num_tx_bds;
378 44 julius
 
379 412 julius
           end
380 44 julius
 
381 412 julius
      end
382
   endtask // do_rx_response_to_tx
383
 
384
 
385
 
386
 
387
 
388
   //
389
   // always@() to check the TX buffer descriptors
390
   //
391
   always @(posedge ethmac_txen)
392
     begin
393
         ethmac_last_txbd_lenstat = 0;
394
         eth_stim_tx_loop_keep_polling=1;
395
         // Wait on the TxBD Ready bit
396
         while(eth_stim_tx_loop_keep_polling)
397
           begin
398
              #10;
399
              get_bd_lenstat(expected_txbd, ethmac_txbd_lenstat);
400
              // Check if we've finished transmitting this BD
401
              if (!ethmac_txbd_lenstat[15] & ethmac_last_txbd_lenstat[15])
402
                // Falling edge of TX BD Ready
403
                eth_stim_detected_packet_tx = 1;
404
 
405
              ethmac_last_txbd_lenstat = ethmac_txbd_lenstat;
406
 
407
              // If TX en goes low then exit
408
              if (!ethmac_txen)
409
                eth_stim_tx_loop_keep_polling = 0;
410
              else if (eth_stim_detected_packet_tx)
411
                begin
412
                   // Wait until the eth_phy has finished receiving it
413
                   while (eth_phy0.mtxen_i === 1'b1)
414
                     #10;
415
 
416
                   $display("(%t) Check TX packet: bd %d: 0x%h",$time,
417
                            expected_txbd, ethmac_txbd_lenstat);
418
 
419
                   // Check the TXBD, see if the packet transmitted OK
420
                   if (ethmac_txbd_lenstat[8] | ethmac_txbd_lenstat[3])
421
                     begin
422
                        // Error occured
423
                        `TIME;
424
                        $display("*E TX Error of packet %0d detected.",
425
                                 num_tx_packets);
426
                        $display(" TX BD %0d = 0x%h", expected_txbd,
427
                                 ethmac_txbd_lenstat);
428
                        if (ethmac_txbd_lenstat[8])
429
                          $display(" Underrun in MAC during TX");
430
                        if (ethmac_txbd_lenstat[3])
431
                          $display(" Retransmission limit hit");
432
 
433
                        $finish;
434
                     end
435
                   else
436
                     begin
437
                        // Packet was OK, let's compare the contents we 
438
                        // received with those that were meant to be transmitted
439
                        if (eth_stim_check_tx_packet_contents)
440
                          begin
441
                             check_tx_packet(expected_txbd);
442
                             expected_txbd = (expected_txbd + 1) &
443
                                             num_tx_bds_mask;
444
                             num_tx_packets = num_tx_packets + 1;
445
                             eth_stim_detected_packet_tx = 0;
446
                          end
447
                     end
448
                end
449
           end // while (eth_stim_tx_loop_keep_polling)
450
     end // always @ (posedge ethmac_txen)
451
 
452
 
453
 
454 415 julius
 
455
`ifdef XILINX_DDR2
456
   // Gets word from correct bank
457
   task get_32bitword_from_xilinx_ddr2;
458
      input [31:0] addr;
459
      output [31:0] insn;
460
      reg [16*8-1:0] ddr2_array_line0,ddr2_array_line1,ddr2_array_line2,
461
                     ddr2_array_line3;
462
      integer        word_in_line_num;
463
      begin
464
        // Get our 4 128-bit chunks (8 half-words in each!! Confused yet?), 
465
        // 16 words total
466
         gen_cs[0].gen[0].u_mem0.memory_read(addr[28:27],addr[26:13],
467
                                             {addr[12:6],3'd0},
468
                                             ddr2_array_line0);
469
         gen_cs[0].gen[1].u_mem0.memory_read(addr[28:27],addr[26:13],
470
                                             {addr[12:6],3'd0},
471
                                             ddr2_array_line1);
472
         gen_cs[0].gen[2].u_mem0.memory_read(addr[28:27],addr[26:13],
473
                                             {addr[12:6],3'd0},
474
                                             ddr2_array_line2);
475
         gen_cs[0].gen[3].u_mem0.memory_read(addr[28:27],addr[26:13],
476
                                             {addr[12:6],3'd0},
477
                                             ddr2_array_line3);
478
         case (addr[5:2])
479
           4'h0:
480
             begin
481
                insn[15:0] = ddr2_array_line0[15:0];
482
                insn[31:16] = ddr2_array_line1[15:0];
483
             end
484
           4'h1:
485
             begin
486
                insn[15:0] = ddr2_array_line2[15:0];
487
                insn[31:16] = ddr2_array_line3[15:0];
488
             end
489
           4'h2:
490
             begin
491
                insn[15:0] = ddr2_array_line0[31:16];
492
                insn[31:16] = ddr2_array_line1[31:16];
493
             end
494
           4'h3:
495
             begin
496
                insn[15:0] = ddr2_array_line2[31:16];
497
                insn[31:16] = ddr2_array_line3[31:16];
498
             end
499
           4'h4:
500
             begin
501
                insn[15:0] = ddr2_array_line0[47:32];
502
                insn[31:16] = ddr2_array_line1[47:32];
503
             end
504
           4'h5:
505
             begin
506
                insn[15:0] = ddr2_array_line2[47:32];
507
                insn[31:16] = ddr2_array_line3[47:32];
508
             end
509
           4'h6:
510
             begin
511
                insn[15:0] = ddr2_array_line0[63:48];
512
                insn[31:16] = ddr2_array_line1[63:48];
513
             end
514
           4'h7:
515
             begin
516
                insn[15:0] = ddr2_array_line2[63:48];
517
                insn[31:16] = ddr2_array_line3[63:48];
518
             end
519
           4'h8:
520
             begin
521
                insn[15:0] = ddr2_array_line0[79:64];
522
                insn[31:16] = ddr2_array_line1[79:64];
523
             end
524
           4'h9:
525
             begin
526
                insn[15:0] = ddr2_array_line2[79:64];
527
                insn[31:16] = ddr2_array_line3[79:64];
528
             end
529
           4'ha:
530
             begin
531
                insn[15:0] = ddr2_array_line0[95:80];
532
                insn[31:16] = ddr2_array_line1[95:80];
533
             end
534
           4'hb:
535
             begin
536
                insn[15:0] = ddr2_array_line2[95:80];
537
                insn[31:16] = ddr2_array_line3[95:80];
538
             end
539
           4'hc:
540
             begin
541
                insn[15:0] = ddr2_array_line0[111:96];
542
                insn[31:16] = ddr2_array_line1[111:96];
543
             end
544
           4'hd:
545
             begin
546
                insn[15:0] = ddr2_array_line2[111:96];
547
                insn[31:16] = ddr2_array_line3[111:96];
548
             end
549
           4'he:
550
             begin
551
                insn[15:0] = ddr2_array_line0[127:112];
552
                insn[31:16] = ddr2_array_line1[127:112];
553
             end
554
           4'hf:
555
             begin
556
                insn[15:0] = ddr2_array_line2[127:112];
557
                insn[31:16] = ddr2_array_line3[127:112];
558
             end
559
         endcase // case (addr[5:2])
560
      end
561
   endtask
562
 
563
   task get_byte_from_xilinx_ddr2;
564
      input [31:0] addr;
565
      output [7:0] data_byte;
566
      reg [31:0]   word;
567
      begin
568
         get_32bitword_from_xilinx_ddr2(addr, word);
569
         case (addr[1:0])
570
           2'b00:
571
             data_byte = word[31:24];
572
           2'b01:
573
             data_byte = word[23:16];
574
           2'b10:
575
             data_byte = word[15:8];
576
           2'b11:
577
             data_byte = word[7:0];
578
         endcase // case (addr[1:0])
579
      end
580
   endtask // get_byte_from_xilinx_ddr2
581
 
582
`endif
583
 
584
 
585 412 julius
   //
586
   // Check packet TX'd by MAC was good
587
   // 
588
   task check_tx_packet;
589
      input [31:0] tx_bd_num;
590
 
591
      reg [31:0]   tx_bd_addr;
592
      reg [7:0]    phy_byte;
593
 
594
      reg [31:0]   txpnt_wb; // Pointer in array to where data should be
595
      reg [24:0]   txpnt_sdram; // Index in array of shorts for data in SDRAM 
596
                                // part
597
      reg [21:0]   buffer;
598
      reg [7:0]    sdram_byte;
599
      reg [31:0]   tx_len_bd;
600
 
601
      integer      i;
602
      integer      failure;
603 44 julius
      begin
604 412 julius
         failure = 0;
605
 
606
         get_bd_lenstat(tx_bd_num, tx_len_bd);
607
 
608
         tx_len_bd = {15'd0,tx_len_bd[31:16]};
609
 
610
         // Check, if length didn't have to be padded, that
611
         // amount transmitted was correct
612
         if ((tx_len_bd > 60)&(tx_len_bd != (eth_phy0.tx_len-4)))
613
           begin
614
              $display("*E TX packet sent length, %0d != length in TX BD, %0d",
615
                       eth_phy0.tx_len-4, tx_len_bd);
616
              #100;
617
              $finish;
618
           end
619
 
620
         get_bd_addr(tx_bd_num, tx_bd_addr);
621
 
622
         // We're never going to be using more than about 256K of receive buffer
623
         // so let's lop off the top bit of the address pointer - we only want
624
         // the offset from the base of the memory bank
625
         txpnt_wb = {14'd0,tx_bd_addr[17:0]};
626
         txpnt_sdram = tx_bd_addr[24:0];
627
 
628
         // Variable we'll use for index in the PHY's TX buffer
629
         buffer = 0; // Start of TX data
630 415 julius
 
631 412 julius
         for (i=0;i<tx_len_bd;i=i+1)
632
           begin
633
              //$display("Checking address in tx bd 0x%0h",txpnt_sdram);
634 415 julius
              sdram_byte = 8'hx;
635 439 julius
`ifdef RAM_WB
636
              sdram_byte = dut.ram_wb0.ram_wb_b3_0.get_byte(txpnt_sdram);
637
`endif
638 415 julius
`ifdef VERSATILE_SDRAM
639
              sdram0.get_byte(txpnt_sdram,sdram_byte);
640
`endif
641
`ifdef XILINX_DDR2
642
              get_byte_from_xilinx_ddr2(txpnt_sdram, sdram_byte);
643
`endif
644
              if (sdram_byte === 8'hx)
645
                begin
646
                   $display(" * Error: sdram_byte was %x", sdram_byte);
647
 
648
                   $display(" * eth_stim needs to be able to access the main memory to check packet rx/tx");
649
                   $display(" * RAM pointer for BD is 0x%h, bank offset we'll use is 0x%h",
650
                            tx_bd_addr, txpnt_wb);
651
                   $finish;
652
                end
653 412 julius
 
654 415 julius
 
655 412 julius
              phy_byte = eth_phy0.tx_mem[buffer];
656
              // Debugging output
657
              //$display("txpnt_sdram = 0x%h, sdram_byte = 0x%h, buffer = 0x%h, phy_byte = 0x%h", txpnt_sdram,  sdram_byte, buffer, phy_byte);
658
              if (phy_byte !== sdram_byte)
659
                begin
660
                   `TIME;
661
                   $display("*E Wrong byte (%d) of TX packet! ram = %h, phy = %h",buffer, sdram_byte, phy_byte);
662
                   failure = 1;
663
                end
664
 
665
              buffer = buffer + 1;
666
 
667
              txpnt_sdram = txpnt_sdram+1;
668
 
669
           end // for (i=0;i<tx_len_bd;i=i+1)
670
 
671
         if (failure)
672
           begin
673
              #100
674
                `TIME;
675
              $display("*E Error transmitting packet %0d (%0d bytes). Finishing simulation", num_tx_packets, tx_len_bd);
676
              get_bd_lenstat(tx_bd_num, tx_len_bd);
677
              $display("   TXBD lenstat: 0x%0h",tx_len_bd);
678
              $display("   TXBD address: 0x%0h",tx_bd_addr);
679
              $finish;
680
           end
681
         else
682
           begin
683
              #1 $display( "(%0t)(%m) TX packet %0d: %0d bytes in memory OK!",$time,num_tx_packets, tx_len_bd);
684
 
685
           end
686
 
687
 
688 44 julius
      end
689 412 julius
   endtask // check_tx_packet
690
 
691
   //
692
   // Task to send a set of packets
693
   //
694
   task send_packet_loop;
695
      input [31:0] num_packets;
696
      input [31:0] length;
697
      input [1:0]  length_change; // 0 = none, 1 = incr, 2 = decrement
698
      input [31:0] length_change_size; // Size to change by
699
      input        speed;
700
      input [31:0] back_to_back_delay; // #delay setting between packets
701
      input [47:0] dst_mac;
702
      input [47:0] src_mac;
703
      input        random_fill;
704
      input        random_errors;
705
      input [31:0] random_error_mod;
706
      integer      j;
707
      reg          error_this_time;
708
      integer      error_type; // 0 = rxerr, 1=bad preamble 2=bad crc 3=TODO
709
      reg [31:0]   rx_bd_lenstat;
710 44 julius
      begin
711 412 julius
         error_type = 0;
712
         error_this_time = 0;
713
 
714
         if (num_packets == 0)
715
           // Loop forever when num_packets is 0
716
           num_packets = 32'h7fffffff;
717
 
718
 
719
         if (speed & !(eth_phy0.control_bit14_10[13] === 1'b1))
720
           begin
721
              // write to phy's control register for 100Mbps
722
              eth_phy0.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
723
              // Swapping speeds, give some delay
724
              #10000;
725
           end
726
         else if (!speed & !(eth_phy0.control_bit14_10[13] === 1'b0))
727
           begin
728
              eth_phy0.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
729
              // Swapping speeds, give some delay
730
              #10000;
731
           end
732
 
733
         eth_phy0.control_bit8_0   = 9'h1_00;
734
 
735
         for(j=0;j<num_packets | length <32;j=j+1)
736
           begin
737
              eth_stim_rx_packet_length = length[15:0]; // Bytes
738
              st_data = 8'h0F;
739
 
740
              // setup RX packet in buffer - length is without CRC
741
              set_rx_packet(0, eth_stim_rx_packet_length, 1'b0, dst_mac,
742
                            src_mac, 16'h0D0E, st_data, random_fill);
743
 
744
              set_rx_addr_type(0, dst_mac, src_mac, 16'h0D0E);
745
 
746
              // Error type 2 is cause CRC error
747
              append_rx_crc(0, eth_stim_rx_packet_length, 1'b0,
748
                            (error_type==2));
749
 
750
              if (error_this_time)
751
                begin
752
                   if (error_type == 0)
753
                     // RX ERR assert during transmit
754
                     eth_phy0.send_rx_packet(64'h0055_5555_5555_5555, 4'h7,
755
                                             8'hD5, 0,
756
                                             eth_stim_rx_packet_length+4,
757
                                             1'b0, 1'b1);
758
                   else if (error_type == 1)
759
                     // Incorrect preamble
760
                     eth_phy0.send_rx_packet(64'h0055_5f55_5555_5555, 4'h7,
761
                                             8'hD5, 0,
762
                                             eth_stim_rx_packet_length+4,
763
                                             1'b0, 1'b0);
764
                   else
765
                     // Normal datapacket
766
                     eth_phy0.send_rx_packet(64'h0055_5555_5555_5555, 4'h7,
767
                                             8'hD5, 0,
768
                                             eth_stim_rx_packet_length+4,
769
                                             1'b0, 1'b0);
770
                end
771
              else
772
                eth_phy0.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5,
773
                                        0, eth_stim_rx_packet_length+4, 1'b0,
774
                                        1'b0);
775
 
776
 
777
              // if RX enable still set (might have gone low during this packet
778
              if (ethmac_rxen)
779
                begin
780
                   if (error_this_time)
781
                     // Put in dummy length, checking function will skip...
782
                     rx_packet_lengths[(eth_rx_num_packets_sent& 12'h3ff)]=32'heeeeeeee;
783
                   else
784
                     rx_packet_lengths[(eth_rx_num_packets_sent & 12'h3ff)] = length;
785
 
786
                   eth_rx_num_packets_sent = eth_rx_num_packets_sent + 1;
787
 
788
                end // if (ethmac_rxen)
789
              else
790
                begin
791
                   // Force the loop to finish up                  
792
                   j = num_packets;
793
                end
794
 
795
 
796
              // Inter-packet gap
797
              #back_to_back_delay;
798
 
799
              // Update length
800
              if (length_change == 2'b01)
801
                length = length + length_change_size;
802
 
803
              if ((length_change == 2'b10) &&
804
                  ((length - length_change_size) > 32))
805
                length = length - length_change_size;
806
 
807
              // Increment error type
808
              if (error_this_time)
809
                error_type = error_type + 1;
810
              if (error_type > 3)
811
                error_type = 0;
812
 
813
 
814
              // Check if we should put in an error this time
815
              if (j%random_error_mod == 0)
816
                error_this_time = 1;
817
              else
818
                error_this_time = 0;
819
 
820
              eth_phy0.rx_err(0);
821
 
822
              // Now wait to check if we have filled up all the RX BDs and
823
              // the this packet would start writing over them. Only really an
824
              // issue when doing minimum IPG tests.
825
              while(((eth_rx_num_packets_sent+1) - eth_rx_num_packets_checked)
826
                    == num_rx_bds)
827
                #100;
828
 
829
 
830
           end // for (j=0;j<num_packets | length <32;j=j+1)
831 44 julius
      end
832 412 julius
   endtask // send_packet_loop
833
 
834
   // Local buffer of "sent" data to the ethernet MAC, we will check against
835
   // Size of our local buffer in bytes
836
   parameter eth_rx_sent_circbuf_size = (16*1024);
837
   parameter eth_rx_sent_circbuf_size_mask = eth_rx_sent_circbuf_size - 1;
838
   integer eth_rx_sent_circbuf_fill_ptr = 0;
839
   integer eth_rx_sent_circbuf_read_ptr = 0;
840
   // The actual buffer
841
   reg [7:0] eth_rx_sent_circbuf [0:eth_rx_sent_circbuf_size-1];
842
 
843
   /*
844
    TASKS for set and check RX packets:
845
    -----------------------------------
846
    set_rx_packet
847
    (rxpnt[31:0], len[15:0], plus_nibble, d_addr[47:0], s_addr[47:0], type_len[15:0], start_data[7:0]);
848
    check_rx_packet
849
    (rxpnt_phy[31:0], rxpnt_wb[31:0], len[15:0], plus_nibble, successful_nibble, failure[31:0]);
850
    */
851
   task set_rx_packet;
852
      input  [31:0] rxpnt; // pointer to place in in the phy rx buffer we'll start at
853
      input [15:0]  len;
854
      input         plus_dribble_nibble; // if length is longer for one nibble
855
      input [47:0]  eth_dest_addr;
856
      input [47:0]  eth_source_addr;
857
      input [15:0]  eth_type_len;
858
      input [7:0]   eth_start_data;
859
      input         random_fill;
860
      integer       i, sd;
861
      reg [47:0]    dest_addr;
862
      reg [47:0]    source_addr;
863
      reg [15:0]    type_len;
864
      reg [21:0]    buffer;
865
      reg           delta_t;
866
 
867 44 julius
      begin
868 412 julius
         buffer = rxpnt[21:0];
869
         dest_addr = eth_dest_addr;
870
         source_addr = eth_source_addr;
871
         type_len = eth_type_len;
872
         sd = eth_start_data;
873
         delta_t = 0;
874
         for(i = 0; i < len; i = i + 1)
875
           begin
876
              if (i < 6)
877
                begin
878
                   eth_phy0.rx_mem[buffer] = dest_addr[47:40];
879
                   dest_addr = dest_addr << 8;
880
                end
881
              else if (i < 12)
882
                begin
883
                   eth_phy0.rx_mem[buffer] = source_addr[47:40];
884
                   source_addr = source_addr << 8;
885
                end
886
              else if (i < 14)
887
                begin
888
                   eth_phy0.rx_mem[buffer] = type_len[15:8];
889
                   type_len = type_len << 8;
890
                end
891
              else
892
                begin
893
                   if (random_fill)
894
                     begin
895
                        if (lfsr_last_byte == 0)
896
                          eth_phy0.rx_mem[buffer] = lfsr[15:8];
897
                        if (lfsr_last_byte == 1)
898
                          eth_phy0.rx_mem[buffer] = lfsr[23:16];
899
                        if (lfsr_last_byte == 2)
900
                          eth_phy0.rx_mem[buffer] = lfsr[31:24];
901
                        if (lfsr_last_byte == 3)
902
                          begin
903
                             eth_phy0.rx_mem[buffer] = lfsr[7:0];
904
                             lfsr = {lfsr[30:0],(((lfsr[31] ^ lfsr[6]) ^
905
                                                  lfsr[5]) ^ lfsr[1])};
906
                             lfsr_last_byte =  0;
907
                          end
908
                        else
909
                          lfsr_last_byte = lfsr_last_byte + 1;
910
 
911
                     end // if (random_fill)               
912
                   else
913
                     eth_phy0.rx_mem[buffer] = sd[7:0];
914
                   sd = sd + 1;
915
                end // else: !if(i < 14)
916
 
917
              // Update our local buffer
918
              eth_rx_sent_circbuf[eth_rx_sent_circbuf_fill_ptr]
919
                = eth_phy0.rx_mem[buffer];
920
              eth_rx_sent_circbuf_fill_ptr = (eth_rx_sent_circbuf_fill_ptr+1)&
921
                                             eth_rx_sent_circbuf_size_mask;
922
 
923
              buffer = buffer + 1;
924
           end // for (i = 0; i < len; i = i + 1)
925
 
926
         delta_t = !delta_t;
927
         if (plus_dribble_nibble)
928
           eth_phy0.rx_mem[buffer] = {4'h0, 4'hD /*sd[3:0]*/};
929
         delta_t = !delta_t;
930 44 julius
      end
931 412 julius
   endtask // set_rx_packet
932
 
933
 
934
 
935
 
936
   task set_rx_addr_type;
937
      input  [31:0] rxpnt;
938
      input [47:0]  eth_dest_addr;
939
      input [47:0]  eth_source_addr;
940
      input [15:0]  eth_type_len;
941
      integer       i;
942
      reg [47:0]    dest_addr;
943
      reg [47:0]    source_addr;
944
      reg [15:0]    type_len;
945
      reg [21:0]    buffer;
946
      reg           delta_t;
947 44 julius
      begin
948 412 julius
         buffer = rxpnt[21:0];
949
         dest_addr = eth_dest_addr;
950
         source_addr = eth_source_addr;
951
         type_len = eth_type_len;
952
         delta_t = 0;
953
         for(i = 0; i < 14; i = i + 1)
954
           begin
955
              if (i < 6)
956
                begin
957
                   eth_phy0.rx_mem[buffer] = dest_addr[47:40];
958
                   dest_addr = dest_addr << 8;
959
                end
960
              else if (i < 12)
961
                begin
962
                   eth_phy0.rx_mem[buffer] = source_addr[47:40];
963
                   source_addr = source_addr << 8;
964
                end
965
              else // if (i < 14)
966
                begin
967
                   eth_phy0.rx_mem[buffer] = type_len[15:8];
968
                   type_len = type_len << 8;
969
                end
970
              buffer = buffer + 1;
971
           end
972
         delta_t = !delta_t;
973 44 julius
      end
974 412 julius
   endtask // set_rx_addr_type
975
 
976
 
977
   // Check if we're using a synthesized version of eth module
978
`ifdef ethmac_IS_GATELEVEL
979
 
980
   // Get the length/status register of the ethernet buffer descriptor
981
   task get_bd_lenstat;
982
      input [31:0] bd_num;// Number of ethernet BD to check
983
      output [31:0] bd_lenstat;
984
 `ifdef ACTEL
985
      reg [8:0]    tmp;
986
      integer      raddr;
987
 `endif
988 44 julius
      begin
989 412 julius
 `ifdef ACTEL
990
 
991
         // Pull from the Actel memory model
992
         raddr = `ETH_BD_RAM_PATH.\mem_tile.I_1 .get_address((bd_num*2));
993
 
994
         tmp = `ETH_BD_RAM_PATH.\mem_tile.I_1 .MEM_512_9[(raddr*2)];
995
         bd_lenstat[8:0] = tmp[8:0];
996
 
997
         tmp = `ETH_BD_RAM_PATH.\mem_tile.I_1 .MEM_512_9[(raddr*2)+1];
998
         bd_lenstat[17:9] = tmp[8:0];
999
 
1000
         raddr = `ETH_BD_RAM_PATH.\mem_tile_0.I_1 .get_address((bd_num*2));
1001
 
1002
         tmp = `ETH_BD_RAM_PATH.\mem_tile_0.I_1 .MEM_512_9[(raddr*2)];
1003
         bd_lenstat[26:18] = tmp[8:0];
1004
 
1005
         tmp = `ETH_BD_RAM_PATH.\mem_tile_0.I_1 .MEM_512_9[(raddr*2)+1];
1006
         bd_lenstat[31:27] = tmp[4:0];
1007
 
1008
         //$display("(%t) read eth bd lenstat %h",$time, bd_lenstat);
1009
 `endif
1010 44 julius
      end
1011 412 julius
   endtask // get_bd_lenstat
1012
 
1013
   // Get the length/status register of the ethernet buffer descriptor
1014
   task get_bd_addr;
1015
      input [31:0] bd_num;// Number of the ethernet BD to check
1016
      output [31:0] bd_addr;
1017
 `ifdef ACTEL
1018
      reg [8:0]    tmp;
1019
      integer       raddr;
1020
 `endif
1021 44 julius
      begin
1022 412 julius
 `ifdef ACTEL
1023
         // Pull from the Actel memory model
1024
         raddr = `ETH_BD_RAM_PATH.\mem_tile.I_1 .get_address((bd_num*2)+1);
1025
 
1026
         tmp = `ETH_BD_RAM_PATH.\mem_tile.I_1 .MEM_512_9[(raddr*2)];
1027
         bd_addr[8:0] = tmp[8:0];
1028
 
1029
         tmp = `ETH_BD_RAM_PATH.\mem_tile.I_1 .MEM_512_9[(raddr*2)+1];
1030
         bd_addr[17:9] = tmp[8:0];
1031
 
1032
         raddr = `ETH_BD_RAM_PATH.\mem_tile_0.I_1 .get_address((bd_num*2)+1);
1033
 
1034
         tmp = `ETH_BD_RAM_PATH.\mem_tile_0.I_1 .MEM_512_9[(raddr*2)];
1035
         bd_addr[26:18] = tmp[8:0];
1036
 
1037
         tmp = `ETH_BD_RAM_PATH.\mem_tile_0.I_1 .MEM_512_9[(raddr*2)+1];
1038
         bd_addr[31:27] = tmp[4:0];
1039
 
1040
         //$display("(%t) read eth bd%d addr %h",$time,bd_num, bd_addr);
1041
 `endif
1042 44 julius
      end
1043 412 julius
   endtask // get_bd_addr
1044
 
1045
`else // !`ifdef ethmac_IS_GATELEVEL
1046
 
1047
   // Get the length/status register of the ethernet buffer descriptor
1048
   task get_bd_lenstat;
1049
      input [31:0] bd_num;// Number of ethernet BD to check
1050
      output [31:0] bd_lenstat;
1051 44 julius
      begin
1052 412 julius
         bd_lenstat = `ETH_BD_RAM_PATH.mem[(bd_num*2)];
1053 44 julius
      end
1054 412 julius
   endtask // get_bd_lenstat
1055
 
1056
   // Get the length/status register of the ethernet buffer descriptor
1057
   task get_bd_addr;
1058
      input [31:0] bd_num;// Number of the ethernet BD to check
1059
      output [31:0] bd_addr;
1060 44 julius
      begin
1061 412 julius
         bd_addr = `ETH_BD_RAM_PATH.mem[((bd_num*2)+1)];
1062
         //$display("(%t) read eth bd%d addr %h",$time,bd_num, bd_addr);
1063 44 julius
      end
1064 412 julius
   endtask // get_bd_addr
1065
`endif
1066
 
1067
   // Always block triggered by finishing of transmission of new packet from 
1068
   // send_packet_loop
1069
   integer eth_rx_packet_length_to_check;
1070 44 julius
 
1071 412 julius
   always @*
1072
     begin
1073
        // Loop here until:
1074
        // 1 - packets sent is not equal to packets checked (ie. some to check)
1075
        // 2 - we're explicitly disabled for some reason
1076
        // 3 - Receive has been disabled in the MAC
1077
        while((eth_rx_num_packets_sent == eth_rx_num_packets_checked) ||
1078
              !eth_stim_check_rx_packet_contents || !(ethmac_rxen===1'b1))
1079
          #1000;
1080 44 julius
 
1081 412 julius
        eth_rx_packet_length_to_check
1082
          = rx_packet_lengths[(eth_rx_num_packets_checked & 12'h3ff)];
1083
 
1084
        if ( eth_rx_packet_length_to_check !==  32'heeeeeeee)
1085
          check_rx_packet(expected_rxbd, 0, eth_rx_packet_length_to_check);
1086
 
1087
        eth_rx_num_packets_checked = eth_rx_num_packets_checked + 1;
1088
 
1089
        expected_rxbd = expected_rxbd + 1;
1090
 
1091
        // Wrap
1092
        if (expected_rxbd == (num_tx_bds + num_rx_bds))
1093
          expected_rxbd = num_tx_bds;
1094
     end
1095
 
1096
   task check_rx_packet;
1097
 
1098
      input [31:0] rx_bd_num;
1099
      input [31:0] rxpnt_phy; // Pointer in array of data in PHY
1100
      input [31:0] len;
1101
 
1102
      reg [31:0]   rx_bd_lenstat;
1103
      reg [31:0]   rx_bd_addr;
1104
      reg [7:0]    phy_byte;
1105
 
1106
      reg [31:0]   rxpnt_wb; // Pointer in array to where data should be
1107
      reg [24:0]   rxpnt_sdram; // byte address from CPU in RAM
1108
      reg [15:0]   sdram_short;
1109
      reg [7:0]    sdram_byte;
1110
      //reg [7:0]    phy_rx_mem [0:2000];
1111
 
1112
      integer      i;
1113
      integer      failure;
1114
 
1115
      begin
1116 44 julius
 
1117 412 julius
         failure = 0;
1118
 
1119
         // Wait until the buffer descriptor indicates the packet has been 
1120
         // received...
1121
         get_bd_lenstat(rx_bd_num, rx_bd_lenstat);
1122
         while (rx_bd_lenstat & 32'h00008000)// Check Empty bit
1123
           begin
1124
              #10;
1125
              get_bd_lenstat(rx_bd_num, rx_bd_lenstat);
1126
              //$display("(%t) check_rx_packet: poll bd %d: 0x%h",$time,
1127
                //        rx_bd_num, rx_bd_lenstat);
1128
           end
1129
 
1130 44 julius
 
1131 412 julius
         // Delay some time - takes a bit for the Wishbone FSM to pipe out the
1132
         // packet over Wishbone and into whatever memory it's going into
1133
         #Td_rx_packet_check;
1134
 
1135
         // Ok, buffer filled, let's get its offset in memory
1136
         get_bd_addr(rx_bd_num, rx_bd_addr);
1137 44 julius
 
1138 412 julius
         $display("(%t) Check RX packet: bd %d: 0x%h, addr 0x%h",$time,
1139
                  rx_bd_num, rx_bd_lenstat, rx_bd_addr);
1140 44 julius
 
1141 412 julius
 
1142
         // We're never going to be using more than about 256KB of receive buffer
1143
         // so let's lop off the top bit of the address pointer - we only want
1144
         // the offset from the base of the memory bank
1145
 
1146
         rxpnt_wb = {14'd0,rx_bd_addr[17:0]};
1147
         rxpnt_sdram = rx_bd_addr[24:0];
1148 415 julius
 
1149
 
1150 412 julius
         //$display("RAM pointer for BD is 0x%h, SDRAM addr is 0x%h", rx_bd_addr, rxpnt_sdram);
1151 44 julius
 
1152
 
1153 412 julius
         for (i=0;i<len;i=i+1)
1154
           begin
1155 44 julius
 
1156 415 julius
              sdram_byte = 8'hx;
1157 439 julius
`ifdef RAM_WB
1158
              sdram_byte = dut.ram_wb0.ram_wb_b3_0.get_byte(rxpnt_sdram);
1159
`endif
1160 415 julius
`ifdef VERSATILE_SDRAM
1161
              sdram0.get_byte(rxpnt_sdram,sdram_byte);
1162 439 julius
`endif
1163 415 julius
`ifdef XILINX_DDR2
1164
              get_byte_from_xilinx_ddr2(rxpnt_sdram, sdram_byte);
1165
`endif
1166
              if (sdram_byte === 8'hx)
1167
                begin
1168
                   $display(" * Error:");
1169
 
1170
                   $display(" * eth_stim needs to be able to access the main memory to check packet rx/tx");
1171
                   $display("RAM pointer for BD is 0x%h, bank offset we'll use is 0x%h",
1172
                            rx_bd_addr, rxpnt_wb);
1173
                   $finish;
1174
                end
1175 44 julius
 
1176 412 julius
              phy_byte = eth_rx_sent_circbuf[eth_rx_sent_circbuf_read_ptr];//phy_rx_mem[buffer]; //eth_phy0.rx_mem[buffer];
1177
 
1178
              if (phy_byte !== sdram_byte)
1179
                begin
1180
//                 `TIME;                 
1181
                   $display("*E Wrong byte (%5d) of RX packet %5d! phy = %h, ram = %h",
1182
                            i, eth_rx_num_packets_checked, phy_byte, sdram_byte);
1183
                   failure = 1;
1184
                end
1185
 
1186
              eth_rx_sent_circbuf_read_ptr = (eth_rx_sent_circbuf_read_ptr+1)&
1187
                                             eth_rx_sent_circbuf_size_mask;
1188
 
1189
              rxpnt_sdram = rxpnt_sdram+1;
1190
 
1191
           end // for (i=0;i<len;i=i+2)
1192
 
1193
         if (failure)
1194
           begin
1195
              #100
1196
                `TIME;
1197
              $display("*E Recieved packet %0d, length %0d bytes, had an error. Finishing simulation.", eth_rx_num_packets_checked, len);
1198
              $finish;
1199
           end
1200
         else
1201
           begin
1202
              #1 $display( "(%0t)(%m) RX packet %0d: %0d bytes in memory OK!",$time,eth_rx_num_packets_checked, len);
1203
 
1204
           end
1205
      end
1206
   endtask // check_rx_packet
1207
 
1208
 
1209
   //////////////////////////////////////////////////////////////
1210
   // Ethernet CRC Basic tasks
1211
   //////////////////////////////////////////////////////////////
1212
 
1213
   task append_rx_crc;
1214
      input  [31:0] rxpnt_phy; // source
1215
      input [15:0]  len; // length in bytes without CRC
1216
      input         plus_dribble_nibble; // if length is longer for one nibble
1217
      input         negated_crc; // if appended CRC is correct or not
1218
      reg [31:0]    crc;
1219
      reg [7:0]     tmp;
1220
      reg [31:0]    addr_phy;
1221
      reg           delta_t;
1222
      begin
1223
         addr_phy = rxpnt_phy + len;
1224
         delta_t = 0;
1225
         // calculate CRC from prepared packet
1226
         paralel_crc_phy_rx(rxpnt_phy, {16'h0, len}, plus_dribble_nibble, crc);
1227
         if (negated_crc)
1228
           crc = ~crc;
1229
         delta_t = !delta_t;
1230
 
1231
         if (plus_dribble_nibble)
1232
           begin
1233
              tmp = eth_phy0.rx_mem[addr_phy];
1234
              eth_phy0.rx_mem[addr_phy]     = {crc[27:24], tmp[3:0]};
1235
              eth_phy0.rx_mem[addr_phy + 1] = {crc[19:16], crc[31:28]};
1236
              eth_phy0.rx_mem[addr_phy + 2] = {crc[11:8], crc[23:20]};
1237
              eth_phy0.rx_mem[addr_phy + 3] = {crc[3:0], crc[15:12]};
1238
              eth_phy0.rx_mem[addr_phy + 4] = {4'h0, crc[7:4]};
1239
           end
1240
         else
1241
           begin
1242
              eth_phy0.rx_mem[addr_phy]     = crc[31:24];
1243
              eth_phy0.rx_mem[addr_phy + 1] = crc[23:16];
1244
              eth_phy0.rx_mem[addr_phy + 2] = crc[15:8];
1245
              eth_phy0.rx_mem[addr_phy + 3] = crc[7:0];
1246
           end
1247
      end
1248
   endtask // append_rx_crc
1249
 
1250
   task append_rx_crc_delayed;
1251
      input  [31:0] rxpnt_phy; // source
1252
      input [15:0]  len; // length in bytes without CRC
1253
      input         plus_dribble_nibble; // if length is longer for one nibble
1254
      input         negated_crc; // if appended CRC is correct or not
1255
      reg [31:0]    crc;
1256
      reg [7:0]     tmp;
1257
      reg [31:0]    addr_phy;
1258
      reg           delta_t;
1259
      begin
1260
         addr_phy = rxpnt_phy + len;
1261
         delta_t = 0;
1262
         // calculate CRC from prepared packet
1263
         paralel_crc_phy_rx(rxpnt_phy+4, {16'h0, len}-4, plus_dribble_nibble, crc);
1264
         if (negated_crc)
1265
           crc = ~crc;
1266
         delta_t = !delta_t;
1267
 
1268
         if (plus_dribble_nibble)
1269
           begin
1270
              tmp = eth_phy0.rx_mem[addr_phy];
1271
              eth_phy0.rx_mem[addr_phy]     = {crc[27:24], tmp[3:0]};
1272
              eth_phy0.rx_mem[addr_phy + 1] = {crc[19:16], crc[31:28]};
1273
              eth_phy0.rx_mem[addr_phy + 2] = {crc[11:8], crc[23:20]};
1274
              eth_phy0.rx_mem[addr_phy + 3] = {crc[3:0], crc[15:12]};
1275
              eth_phy0.rx_mem[addr_phy + 4] = {4'h0, crc[7:4]};
1276
           end
1277
         else
1278
           begin
1279
              eth_phy0.rx_mem[addr_phy]     = crc[31:24];
1280
              eth_phy0.rx_mem[addr_phy + 1] = crc[23:16];
1281
              eth_phy0.rx_mem[addr_phy + 2] = crc[15:8];
1282
              eth_phy0.rx_mem[addr_phy + 3] = crc[7:0];
1283
           end
1284
      end
1285
   endtask // append_rx_crc_delayed
1286
 
1287
 
1288
   // paralel CRC calculating for PHY RX
1289
   task paralel_crc_phy_rx;
1290
      input  [31:0] start_addr; // start address
1291
      input [31:0]  len; // length of frame in Bytes without CRC length
1292
      input         plus_dribble_nibble; // if length is longer for one nibble
1293
      output [31:0] crc_out;
1294
      reg [21:0]    addr_cnt; // only 22 address lines
1295
      integer       word_cnt;
1296
      integer       nibble_cnt;
1297
      reg [31:0]    load_reg;
1298
      reg           delta_t;
1299
      reg [31:0]    crc_next;
1300
      reg [31:0]    crc;
1301
      reg           crc_error;
1302
      reg [3:0]     data_in;
1303
      integer       i;
1304
      begin
1305
         #1 addr_cnt = start_addr[21:0];
1306
         word_cnt = 24; // 27; // start of the frame - nibble granularity (MSbit first)
1307
         crc = 32'hFFFF_FFFF; // INITIAL value
1308
         delta_t = 0;
1309
         // length must include 4 bytes of ZEROs, to generate CRC
1310
         // get number of nibbles from Byte length (2^1 = 2)
1311
         if (plus_dribble_nibble)
1312
           nibble_cnt = ((len + 4) << 1) + 1'b1; // one nibble longer
1313
         else
1314
           nibble_cnt = ((len + 4) << 1);
1315
         // because of MAGIC NUMBER nibbles are swapped [3:0] -> [0:3]
1316
         load_reg[31:24] = eth_phy0.rx_mem[addr_cnt];
1317
         addr_cnt = addr_cnt + 1;
1318
         load_reg[23:16] = eth_phy0.rx_mem[addr_cnt];
1319
         addr_cnt = addr_cnt + 1;
1320
         load_reg[15: 8] = eth_phy0.rx_mem[addr_cnt];
1321
         addr_cnt = addr_cnt + 1;
1322
         load_reg[ 7: 0] = eth_phy0.rx_mem[addr_cnt];
1323
         addr_cnt = addr_cnt + 1;
1324
         while (nibble_cnt > 0)
1325
           begin
1326
              // wait for delta time
1327
              delta_t = !delta_t;
1328
              // shift data in
1329
 
1330
              if(nibble_cnt <= 8) // for additional 8 nibbles shift ZEROs in!
1331
                data_in[3:0] = 4'h0;
1332
              else
1333
 
1334
                data_in[3:0] = {load_reg[word_cnt], load_reg[word_cnt+1], load_reg[word_cnt+2], load_reg[word_cnt+3]};
1335
              crc_next[0]  = (data_in[0] ^ crc[28]);
1336
              crc_next[1]  = (data_in[1] ^ data_in[0] ^ crc[28]    ^ crc[29]);
1337
              crc_next[2]  = (data_in[2] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[30]);
1338
              crc_next[3]  = (data_in[3] ^ data_in[2] ^ data_in[1] ^ crc[29]  ^ crc[30] ^ crc[31]);
1339
              crc_next[4]  = (data_in[3] ^ data_in[2] ^ data_in[0] ^ crc[28]  ^ crc[30] ^ crc[31]) ^ crc[0];
1340
              crc_next[5]  = (data_in[3] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[31]) ^ crc[1];
1341
              crc_next[6]  = (data_in[2] ^ data_in[1] ^ crc[29]    ^ crc[30]) ^ crc[ 2];
1342
              crc_next[7]  = (data_in[3] ^ data_in[2] ^ data_in[0] ^ crc[28]  ^ crc[30] ^ crc[31]) ^ crc[3];
1343
              crc_next[8]  = (data_in[3] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[31]) ^ crc[4];
1344
              crc_next[9]  = (data_in[2] ^ data_in[1] ^ crc[29]    ^ crc[30]) ^ crc[5];
1345
              crc_next[10] = (data_in[3] ^ data_in[2] ^ data_in[0] ^ crc[28]  ^ crc[30] ^ crc[31]) ^ crc[6];
1346
              crc_next[11] = (data_in[3] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[31]) ^ crc[7];
1347
              crc_next[12] = (data_in[2] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[30]) ^ crc[8];
1348
              crc_next[13] = (data_in[3] ^ data_in[2] ^ data_in[1] ^ crc[29]  ^ crc[30] ^ crc[31]) ^ crc[9];
1349
              crc_next[14] = (data_in[3] ^ data_in[2] ^ crc[30]    ^ crc[31]) ^ crc[10];
1350
              crc_next[15] = (data_in[3] ^ crc[31])   ^ crc[11];
1351
              crc_next[16] = (data_in[0] ^ crc[28])   ^ crc[12];
1352
              crc_next[17] = (data_in[1] ^ crc[29])   ^ crc[13];
1353
              crc_next[18] = (data_in[2] ^ crc[30])   ^ crc[14];
1354
              crc_next[19] = (data_in[3] ^ crc[31])   ^ crc[15];
1355
              crc_next[20] =  crc[16];
1356
              crc_next[21] =  crc[17];
1357
              crc_next[22] = (data_in[0] ^ crc[28])   ^ crc[18];
1358
              crc_next[23] = (data_in[1] ^ data_in[0] ^ crc[29]    ^ crc[28]) ^ crc[19];
1359
              crc_next[24] = (data_in[2] ^ data_in[1] ^ crc[30]    ^ crc[29]) ^ crc[20];
1360
              crc_next[25] = (data_in[3] ^ data_in[2] ^ crc[31]    ^ crc[30]) ^ crc[21];
1361
              crc_next[26] = (data_in[3] ^ data_in[0] ^ crc[31]    ^ crc[28]) ^ crc[22];
1362
              crc_next[27] = (data_in[1] ^ crc[29])   ^ crc[23];
1363
              crc_next[28] = (data_in[2] ^ crc[30])   ^ crc[24];
1364
              crc_next[29] = (data_in[3] ^ crc[31])   ^ crc[25];
1365
              crc_next[30] =  crc[26];
1366
              crc_next[31] =  crc[27];
1367
 
1368
              crc = crc_next;
1369
              crc_error = crc[31:0] != 32'hc704dd7b;  // CRC not equal to magic number
1370
              case (nibble_cnt)
1371
                9: crc_out = {!crc[24], !crc[25], !crc[26], !crc[27], !crc[28], !crc[29], !crc[30], !crc[31],
1372
                              !crc[16], !crc[17], !crc[18], !crc[19], !crc[20], !crc[21], !crc[22], !crc[23],
1373
                              !crc[ 8], !crc[ 9], !crc[10], !crc[11], !crc[12], !crc[13], !crc[14], !crc[15],
1374
                              !crc[ 0], !crc[ 1], !crc[ 2], !crc[ 3], !crc[ 4], !crc[ 5], !crc[ 6], !crc[ 7]};
1375
                default: crc_out = crc_out;
1376
              endcase
1377
              // wait for delta time
1378
              delta_t = !delta_t;
1379
              // increment address and load new data
1380
              if ((word_cnt+3) == 7)//4)
1381
                begin
1382
                   // because of MAGIC NUMBER nibbles are swapped [3:0] -> [0:3]
1383
                   load_reg[31:24] = eth_phy0.rx_mem[addr_cnt];
1384
                   addr_cnt = addr_cnt + 1;
1385
                   load_reg[23:16] = eth_phy0.rx_mem[addr_cnt];
1386
                   addr_cnt = addr_cnt + 1;
1387
                   load_reg[15: 8] = eth_phy0.rx_mem[addr_cnt];
1388
                   addr_cnt = addr_cnt + 1;
1389
                   load_reg[ 7: 0] = eth_phy0.rx_mem[addr_cnt];
1390
                   addr_cnt = addr_cnt + 1;
1391
                end
1392
              // set new load bit position
1393
              if((word_cnt+3) == 31)
1394
                word_cnt = 16;
1395
              else if ((word_cnt+3) == 23)
1396
                word_cnt = 8;
1397
              else if ((word_cnt+3) == 15)
1398
                word_cnt = 0;
1399
              else if ((word_cnt+3) == 7)
1400
                word_cnt = 24;
1401
              else
1402
                word_cnt = word_cnt + 4;// - 4;
1403
              // decrement nibble counter
1404
              nibble_cnt = nibble_cnt - 1;
1405
              // wait for delta time
1406
              delta_t = !delta_t;
1407
           end // while
1408
         #1;
1409
      end
1410
   endtask // paralel_crc_phy_rx
1411
 
1412
 
1413
 
1414 44 julius
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.