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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [rtl/] [verilog/] [orpsoc_top/] [orpsoc_top.v] - Blame information for rev 530

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1 412 julius
//////////////////////////////////////////////////////////////////////
2
///                                                               //// 
3
/// ORPSoC top for ML501 board                                    ////
4
///                                                               ////
5
/// Instantiates modules, depending on ORPSoC defines file        ////
6
///                                                               ////
7
/// Julius Baxter, julius@opencores.org                           ////
8
///                                                               ////
9
//////////////////////////////////////////////////////////////////////
10
////                                                              ////
11
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG           ////
12
////                                                              ////
13
//// This source file may be used and distributed without         ////
14
//// restriction provided that this copyright statement is not    ////
15
//// removed from the file and that any derivative work contains  ////
16
//// the original copyright notice and the associated disclaimer. ////
17
////                                                              ////
18
//// This source file is free software; you can redistribute it   ////
19
//// and/or modify it under the terms of the GNU Lesser General   ////
20
//// Public License as published by the Free Software Foundation; ////
21
//// either version 2.1 of the License, or (at your option) any   ////
22
//// later version.                                               ////
23
////                                                              ////
24
//// This source is distributed in the hope that it will be       ////
25
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
26
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
27
//// PURPOSE.  See the GNU Lesser General Public License for more ////
28
//// details.                                                     ////
29
////                                                              ////
30
//// You should have received a copy of the GNU Lesser General    ////
31
//// Public License along with this source; if not, download it   ////
32
//// from http://www.opencores.org/lgpl.shtml                     ////
33
////                                                              ////
34
//////////////////////////////////////////////////////////////////////
35
 
36
`include "orpsoc-defines.v"
37
`include "synthesis-defines.v"
38
module orpsoc_top
39
  (
40
`ifdef JTAG_DEBUG
41
    tdo_pad_o, tms_pad_i, tck_pad_i, tdi_pad_i,
42
`endif
43
`ifdef XILINX_DDR2
44
    ddr2_a, ddr2_ba, ddr2_ras_n, ddr2_cas_n, ddr2_we_n,
45
    ddr2_cs_n, ddr2_odt, ddr2_cke, ddr2_dm,
46
    ddr2_dq, ddr2_dqs, ddr2_dqs_n, ddr2_ck, ddr2_ck_n,
47
`endif
48
`ifdef XILINX_SSRAM
49
    sram_clk, sram_clk_fb, sram_flash_addr, sram_flash_data,
50
    sram_cen, sram_flash_oe_n, sram_flash_we_n, sram_bw,
51
    sram_adv_ld_n, sram_mode,
52
`endif
53
`ifdef UART0
54
    uart0_srx_pad_i, uart0_stx_pad_o,
55
    uart0_srx_expheader_pad_i, uart0_stx_expheader_pad_o,
56
`endif
57
`ifdef SPI0
58 415 julius
    spi0_mosi_o, spi0_ss_o,/* spi0_sck_o, spi0_miso_i,via STARTUP_VIRTEX5*/
59 412 julius
`endif
60
`ifdef I2C0
61
    i2c0_sda_io, i2c0_scl_io,
62
`endif
63
`ifdef I2C1
64
    i2c1_sda_io, i2c1_scl_io,
65
`endif
66
`ifdef GPIO0
67
    gpio0_io,
68
`endif
69
 
70
`ifdef ETH0
71
    eth0_tx_clk, eth0_tx_data, eth0_tx_en, eth0_tx_er,
72
    eth0_rx_clk, eth0_rx_data, eth0_dv, eth0_rx_er,
73
    eth0_col, eth0_crs,
74
    eth0_mdc_pad_o, eth0_md_pad_io,
75
 `ifdef ETH0_PHY_RST
76
    eth0_rst_n_o,
77
 `endif
78
`endif
79
 
80
    sys_clk_in_p,sys_clk_in_n,
81
 
82
    rst_n_pad_i
83
 
84
    );
85
 
86
`include "orpsoc-params.v"
87
 
88
   input sys_clk_in_p,sys_clk_in_n;
89
 
90
   input rst_n_pad_i;
91
 
92
`ifdef JTAG_DEBUG
93
   output tdo_pad_o;
94
   input  tms_pad_i;
95
   input  tck_pad_i;
96
   input  tdi_pad_i;
97
`endif
98
`ifdef XILINX_DDR2
99
   output [12:0]               ddr2_a;
100
   output [1:0]        ddr2_ba;
101
   output                     ddr2_ras_n;
102
   output                     ddr2_cas_n;
103
   output                     ddr2_we_n;
104
   output [1:0]        ddr2_cs_n;
105
   output [1:0]        ddr2_odt;
106
   output [1:0]        ddr2_cke;
107
   output [7:0]        ddr2_dm;
108
 
109
   inout [63:0]        ddr2_dq;
110
   inout [7:0]                 ddr2_dqs;
111
   inout [7:0]                 ddr2_dqs_n;
112
   output [1:0]        ddr2_ck;
113
   output [1:0]        ddr2_ck_n;
114
`endif
115
`ifdef XILINX_SSRAM
116
   // ZBT SSRAM
117 530 julius
    output         sram_clk;
118
    input          sram_clk_fb;
119
    output [21:1]  sram_flash_addr;
120
    inout [31:0]   sram_flash_data;
121
    output         sram_cen;
122
    output         sram_flash_oe_n;
123
    output         sram_flash_we_n;
124
    output [3:0]   sram_bw;
125
    output         sram_adv_ld_n;
126
    output         sram_mode;
127 412 julius
`endif
128
`ifdef UART0
129
   input         uart0_srx_pad_i;
130
   output        uart0_stx_pad_o;
131
   // Duplicates of the UART signals, this time to the USB debug cable
132
   input         uart0_srx_expheader_pad_i;
133
   output        uart0_stx_expheader_pad_o;
134
`endif
135
`ifdef SPI0
136
   output        spi0_mosi_o;
137 415 julius
  output [spi0_ss_width-1:0] spi0_ss_o;
138
   /* via STARTUP_VIRTEX5
139
   output                    spi0_sck_o;
140 412 julius
   input                      spi0_miso_i;
141 415 julius
    */
142 412 julius
`endif
143
`ifdef I2C0
144
   inout                      i2c0_sda_io, i2c0_scl_io;
145
`endif
146
`ifdef I2C1
147
   inout                      i2c1_sda_io, i2c1_scl_io;
148
`endif
149
`ifdef GPIO0
150
   inout [gpio0_io_width-1:0] gpio0_io;
151
`endif
152
`ifdef ETH0
153
   input                      eth0_tx_clk;
154
   output [3:0]        eth0_tx_data;
155
   output                     eth0_tx_en;
156
   output                     eth0_tx_er;
157
   input                      eth0_rx_clk;
158
   input [3:0]                 eth0_rx_data;
159
   input                      eth0_dv;
160
   input                      eth0_rx_er;
161
   input                      eth0_col;
162
   input                      eth0_crs;
163
   output                     eth0_mdc_pad_o;
164
   inout                      eth0_md_pad_io;
165
 `ifdef ETH0_PHY_RST
166
   output                     eth0_rst_n_o;
167
 `endif
168
`endif //  `ifdef ETH0
169
 
170
   ////////////////////////////////////////////////////////////////////////
171
   //
172
   // Clock and reset generation module
173
   // 
174
   ////////////////////////////////////////////////////////////////////////
175
 
176
   //
177
   // Wires
178
   //
179
   wire                       wb_clk, wb_rst;
180
   wire                       ddr2_if_clk, ddr2_if_rst;
181
   wire                       clk200;
182
   wire                       dbg_tck;
183
 
184
 
185
   clkgen clkgen0
186
     (
187
      .sys_clk_in_p              (sys_clk_in_p),
188
      .sys_clk_in_n              (sys_clk_in_n),
189
 
190
      .wb_clk_o                  (wb_clk),
191
      .wb_rst_o                  (wb_rst),
192
 
193
`ifdef JTAG_DEBUG
194
      .tck_pad_i                 (tck_pad_i),
195
      .dbg_tck_o                 (dbg_tck),
196
`endif
197
`ifdef XILINX_DDR2
198
      .ddr2_if_clk_o             (ddr2_if_clk),
199
      .ddr2_if_rst_o             (ddr2_if_rst),
200
      .clk200_o                  (clk200),
201
`endif
202
 
203
      // Asynchronous active low reset
204
      .rst_n_pad_i               (rst_n_pad_i)
205
      );
206
 
207
 
208
   ////////////////////////////////////////////////////////////////////////
209
   //
210
   // Arbiter
211
   // 
212
   ////////////////////////////////////////////////////////////////////////
213
 
214
   // Wire naming convention:
215
   // First: wishbone master or slave (wbm/wbs)
216
   // Second: Which bus it's on instruction or data (i/d)
217
   // Third: Between which module and the arbiter the wires are
218
   // Fourth: Signal name
219
   // Fifth: Direction relative to module (not bus/arbiter!)
220
   //        ie. wbm_d_or12_adr_o is address OUT from the or1200
221
 
222
   // OR1200 instruction bus wires
223
   wire [wb_aw-1:0]            wbm_i_or12_adr_o;
224
   wire [wb_dw-1:0]            wbm_i_or12_dat_o;
225
   wire [3:0]                  wbm_i_or12_sel_o;
226
   wire                       wbm_i_or12_we_o;
227
   wire                       wbm_i_or12_cyc_o;
228
   wire                       wbm_i_or12_stb_o;
229
   wire [2:0]                  wbm_i_or12_cti_o;
230
   wire [1:0]                  wbm_i_or12_bte_o;
231
 
232
   wire [wb_dw-1:0]            wbm_i_or12_dat_i;
233
   wire                       wbm_i_or12_ack_i;
234
   wire                       wbm_i_or12_err_i;
235
   wire                       wbm_i_or12_rty_i;
236
 
237
   // OR1200 data bus wires   
238
   wire [wb_aw-1:0]            wbm_d_or12_adr_o;
239
   wire [wb_dw-1:0]            wbm_d_or12_dat_o;
240
   wire [3:0]                  wbm_d_or12_sel_o;
241
   wire                       wbm_d_or12_we_o;
242
   wire                       wbm_d_or12_cyc_o;
243
   wire                       wbm_d_or12_stb_o;
244
   wire [2:0]                  wbm_d_or12_cti_o;
245
   wire [1:0]                  wbm_d_or12_bte_o;
246
 
247
   wire [wb_dw-1:0]            wbm_d_or12_dat_i;
248
   wire                       wbm_d_or12_ack_i;
249
   wire                       wbm_d_or12_err_i;
250
   wire                       wbm_d_or12_rty_i;
251
 
252
   // Debug interface bus wires   
253
   wire [wb_aw-1:0]            wbm_d_dbg_adr_o;
254
   wire [wb_dw-1:0]            wbm_d_dbg_dat_o;
255
   wire [3:0]                  wbm_d_dbg_sel_o;
256
   wire                       wbm_d_dbg_we_o;
257
   wire                       wbm_d_dbg_cyc_o;
258
   wire                       wbm_d_dbg_stb_o;
259
   wire [2:0]                  wbm_d_dbg_cti_o;
260
   wire [1:0]                  wbm_d_dbg_bte_o;
261
 
262
   wire [wb_dw-1:0]            wbm_d_dbg_dat_i;
263
   wire                       wbm_d_dbg_ack_i;
264
   wire                       wbm_d_dbg_err_i;
265
   wire                       wbm_d_dbg_rty_i;
266
 
267
   // Byte bus bridge master signals
268
   wire [wb_aw-1:0]            wbm_b_d_adr_o;
269
   wire [wb_dw-1:0]            wbm_b_d_dat_o;
270
   wire [3:0]                  wbm_b_d_sel_o;
271
   wire                       wbm_b_d_we_o;
272
   wire                       wbm_b_d_cyc_o;
273
   wire                       wbm_b_d_stb_o;
274
   wire [2:0]                  wbm_b_d_cti_o;
275
   wire [1:0]                  wbm_b_d_bte_o;
276
 
277
   wire [wb_dw-1:0]            wbm_b_d_dat_i;
278
   wire                       wbm_b_d_ack_i;
279
   wire                       wbm_b_d_err_i;
280
   wire                       wbm_b_d_rty_i;
281
 
282
   // Instruction bus slave wires //
283
 
284
   // rom0 instruction bus wires
285
   wire [31:0]                 wbs_i_rom0_adr_i;
286
   wire [wbs_i_rom0_data_width-1:0] wbs_i_rom0_dat_i;
287
   wire [3:0]                        wbs_i_rom0_sel_i;
288
   wire                             wbs_i_rom0_we_i;
289
   wire                             wbs_i_rom0_cyc_i;
290
   wire                             wbs_i_rom0_stb_i;
291
   wire [2:0]                        wbs_i_rom0_cti_i;
292
   wire [1:0]                        wbs_i_rom0_bte_i;
293
   wire [wbs_i_rom0_data_width-1:0] wbs_i_rom0_dat_o;
294
   wire                             wbs_i_rom0_ack_o;
295
   wire                             wbs_i_rom0_err_o;
296
   wire                             wbs_i_rom0_rty_o;
297
 
298
   // mc0 instruction bus wires
299
   wire [31:0]                       wbs_i_mc0_adr_i;
300
   wire [wbs_i_mc0_data_width-1:0]  wbs_i_mc0_dat_i;
301
   wire [3:0]                        wbs_i_mc0_sel_i;
302
   wire                             wbs_i_mc0_we_i;
303
   wire                             wbs_i_mc0_cyc_i;
304
   wire                             wbs_i_mc0_stb_i;
305
   wire [2:0]                        wbs_i_mc0_cti_i;
306
   wire [1:0]                        wbs_i_mc0_bte_i;
307
   wire [wbs_i_mc0_data_width-1:0]  wbs_i_mc0_dat_o;
308
   wire                             wbs_i_mc0_ack_o;
309
   wire                             wbs_i_mc0_err_o;
310
   wire                             wbs_i_mc0_rty_o;
311
 
312
   // Data bus slave wires //
313
 
314
   // mc0 data bus wires
315
   wire [31:0]                       wbs_d_mc0_adr_i;
316
   wire [wbs_d_mc0_data_width-1:0]  wbs_d_mc0_dat_i;
317
   wire [3:0]                        wbs_d_mc0_sel_i;
318
   wire                             wbs_d_mc0_we_i;
319
   wire                             wbs_d_mc0_cyc_i;
320
   wire                             wbs_d_mc0_stb_i;
321
   wire [2:0]                        wbs_d_mc0_cti_i;
322
   wire [1:0]                        wbs_d_mc0_bte_i;
323
   wire [wbs_d_mc0_data_width-1:0]  wbs_d_mc0_dat_o;
324
   wire                             wbs_d_mc0_ack_o;
325
   wire                             wbs_d_mc0_err_o;
326
   wire                             wbs_d_mc0_rty_o;
327
 
328
   // i2c0 wires
329
   wire [31:0]                       wbs_d_i2c0_adr_i;
330
   wire [wbs_d_i2c0_data_width-1:0] wbs_d_i2c0_dat_i;
331
   wire [3:0]                        wbs_d_i2c0_sel_i;
332
   wire                             wbs_d_i2c0_we_i;
333
   wire                             wbs_d_i2c0_cyc_i;
334
   wire                             wbs_d_i2c0_stb_i;
335
   wire [2:0]                        wbs_d_i2c0_cti_i;
336
   wire [1:0]                        wbs_d_i2c0_bte_i;
337
   wire [wbs_d_i2c0_data_width-1:0] wbs_d_i2c0_dat_o;
338
   wire                             wbs_d_i2c0_ack_o;
339
   wire                             wbs_d_i2c0_err_o;
340
   wire                             wbs_d_i2c0_rty_o;
341
 
342
   // i2c1 wires
343
   wire [31:0]                       wbs_d_i2c1_adr_i;
344
   wire [wbs_d_i2c1_data_width-1:0] wbs_d_i2c1_dat_i;
345
   wire [3:0]                        wbs_d_i2c1_sel_i;
346
   wire                             wbs_d_i2c1_we_i;
347
   wire                             wbs_d_i2c1_cyc_i;
348
   wire                             wbs_d_i2c1_stb_i;
349
   wire [2:0]                        wbs_d_i2c1_cti_i;
350
   wire [1:0]                        wbs_d_i2c1_bte_i;
351
   wire [wbs_d_i2c1_data_width-1:0] wbs_d_i2c1_dat_o;
352
   wire                             wbs_d_i2c1_ack_o;
353
   wire                             wbs_d_i2c1_err_o;
354
   wire                             wbs_d_i2c1_rty_o;
355
 
356
   // spi0 wires
357
   wire [31:0]                       wbs_d_spi0_adr_i;
358
   wire [wbs_d_spi0_data_width-1:0] wbs_d_spi0_dat_i;
359
   wire [3:0]                        wbs_d_spi0_sel_i;
360
   wire                             wbs_d_spi0_we_i;
361
   wire                             wbs_d_spi0_cyc_i;
362
   wire                             wbs_d_spi0_stb_i;
363
   wire [2:0]                        wbs_d_spi0_cti_i;
364
   wire [1:0]                        wbs_d_spi0_bte_i;
365
   wire [wbs_d_spi0_data_width-1:0] wbs_d_spi0_dat_o;
366
   wire                             wbs_d_spi0_ack_o;
367
   wire                             wbs_d_spi0_err_o;
368
   wire                             wbs_d_spi0_rty_o;
369
 
370
   // uart0 wires
371
   wire [31:0]                        wbs_d_uart0_adr_i;
372
   wire [wbs_d_uart0_data_width-1:0] wbs_d_uart0_dat_i;
373
   wire [3:0]                         wbs_d_uart0_sel_i;
374
   wire                              wbs_d_uart0_we_i;
375
   wire                              wbs_d_uart0_cyc_i;
376
   wire                              wbs_d_uart0_stb_i;
377
   wire [2:0]                         wbs_d_uart0_cti_i;
378
   wire [1:0]                         wbs_d_uart0_bte_i;
379
   wire [wbs_d_uart0_data_width-1:0] wbs_d_uart0_dat_o;
380
   wire                              wbs_d_uart0_ack_o;
381
   wire                              wbs_d_uart0_err_o;
382
   wire                              wbs_d_uart0_rty_o;
383
 
384
   // gpio0 wires
385
   wire [31:0]                        wbs_d_gpio0_adr_i;
386
   wire [wbs_d_gpio0_data_width-1:0] wbs_d_gpio0_dat_i;
387
   wire [3:0]                         wbs_d_gpio0_sel_i;
388
   wire                              wbs_d_gpio0_we_i;
389
   wire                              wbs_d_gpio0_cyc_i;
390
   wire                              wbs_d_gpio0_stb_i;
391
   wire [2:0]                         wbs_d_gpio0_cti_i;
392
   wire [1:0]                         wbs_d_gpio0_bte_i;
393
   wire [wbs_d_gpio0_data_width-1:0] wbs_d_gpio0_dat_o;
394
   wire                              wbs_d_gpio0_ack_o;
395
   wire                              wbs_d_gpio0_err_o;
396
   wire                              wbs_d_gpio0_rty_o;
397
 
398
   // eth0 slave wires
399
   wire [31:0]                             wbs_d_eth0_adr_i;
400
   wire [wbs_d_eth0_data_width-1:0]        wbs_d_eth0_dat_i;
401
   wire [3:0]                              wbs_d_eth0_sel_i;
402
   wire                                   wbs_d_eth0_we_i;
403
   wire                                   wbs_d_eth0_cyc_i;
404
   wire                                   wbs_d_eth0_stb_i;
405
   wire [2:0]                              wbs_d_eth0_cti_i;
406
   wire [1:0]                              wbs_d_eth0_bte_i;
407
   wire [wbs_d_eth0_data_width-1:0]        wbs_d_eth0_dat_o;
408
   wire                                   wbs_d_eth0_ack_o;
409
   wire                                   wbs_d_eth0_err_o;
410
   wire                                   wbs_d_eth0_rty_o;
411
 
412
   // eth0 master wires
413
   wire [wbm_eth0_addr_width-1:0]          wbm_eth0_adr_o;
414
   wire [wbm_eth0_data_width-1:0]          wbm_eth0_dat_o;
415
   wire [3:0]                              wbm_eth0_sel_o;
416
   wire                                   wbm_eth0_we_o;
417
   wire                                   wbm_eth0_cyc_o;
418
   wire                                   wbm_eth0_stb_o;
419
   wire [2:0]                              wbm_eth0_cti_o;
420
   wire [1:0]                              wbm_eth0_bte_o;
421
   wire [wbm_eth0_data_width-1:0]         wbm_eth0_dat_i;
422
   wire                                   wbm_eth0_ack_i;
423
   wire                                   wbm_eth0_err_i;
424
   wire                                   wbm_eth0_rty_i;
425
 
426
 
427
 
428
   //
429
   // Wishbone instruction bus arbiter
430
   //
431
 
432
   arbiter_ibus arbiter_ibus0
433
     (
434
      // Instruction Bus Master
435
      // Inputs to arbiter from master
436
      .wbm_adr_o                        (wbm_i_or12_adr_o),
437
      .wbm_dat_o                        (wbm_i_or12_dat_o),
438
      .wbm_sel_o                        (wbm_i_or12_sel_o),
439
      .wbm_we_o                         (wbm_i_or12_we_o),
440
      .wbm_cyc_o                        (wbm_i_or12_cyc_o),
441
      .wbm_stb_o                        (wbm_i_or12_stb_o),
442
      .wbm_cti_o                        (wbm_i_or12_cti_o),
443
      .wbm_bte_o                        (wbm_i_or12_bte_o),
444
      // Outputs to master from arbiter
445
      .wbm_dat_i                        (wbm_i_or12_dat_i),
446
      .wbm_ack_i                        (wbm_i_or12_ack_i),
447
      .wbm_err_i                        (wbm_i_or12_err_i),
448
      .wbm_rty_i                        (wbm_i_or12_rty_i),
449
 
450
      // Slave 0
451
      // Inputs to slave from arbiter
452
      .wbs0_adr_i                       (wbs_i_rom0_adr_i),
453
      .wbs0_dat_i                       (wbs_i_rom0_dat_i),
454
      .wbs0_sel_i                       (wbs_i_rom0_sel_i),
455
      .wbs0_we_i                        (wbs_i_rom0_we_i),
456
      .wbs0_cyc_i                       (wbs_i_rom0_cyc_i),
457
      .wbs0_stb_i                       (wbs_i_rom0_stb_i),
458
      .wbs0_cti_i                       (wbs_i_rom0_cti_i),
459
      .wbs0_bte_i                       (wbs_i_rom0_bte_i),
460
      // Outputs from slave to arbiter      
461
      .wbs0_dat_o                       (wbs_i_rom0_dat_o),
462
      .wbs0_ack_o                       (wbs_i_rom0_ack_o),
463
      .wbs0_err_o                       (wbs_i_rom0_err_o),
464
      .wbs0_rty_o                       (wbs_i_rom0_rty_o),
465
 
466
      // Slave 1
467
      // Inputs to slave from arbiter
468
      .wbs1_adr_i                       (wbs_i_mc0_adr_i),
469
      .wbs1_dat_i                       (wbs_i_mc0_dat_i),
470
      .wbs1_sel_i                       (wbs_i_mc0_sel_i),
471
      .wbs1_we_i                        (wbs_i_mc0_we_i),
472
      .wbs1_cyc_i                       (wbs_i_mc0_cyc_i),
473
      .wbs1_stb_i                       (wbs_i_mc0_stb_i),
474
      .wbs1_cti_i                       (wbs_i_mc0_cti_i),
475
      .wbs1_bte_i                       (wbs_i_mc0_bte_i),
476
      // Outputs from slave to arbiter
477
      .wbs1_dat_o                       (wbs_i_mc0_dat_o),
478
      .wbs1_ack_o                       (wbs_i_mc0_ack_o),
479
      .wbs1_err_o                       (wbs_i_mc0_err_o),
480
      .wbs1_rty_o                       (wbs_i_mc0_rty_o),
481
 
482
      // Clock, reset inputs
483
      .wb_clk                           (wb_clk),
484
      .wb_rst                           (wb_rst));
485
 
486
   defparam arbiter_ibus0.wb_addr_match_width = ibus_arb_addr_match_width;
487
 
488
   defparam arbiter_ibus0.slave0_adr = ibus_arb_slave0_adr; // FLASH ROM
489
   defparam arbiter_ibus0.slave1_adr = ibus_arb_slave1_adr; // Main memory
490
 
491
   //
492
   // Wishbone data bus arbiter
493
   //
494
 
495
   arbiter_dbus arbiter_dbus0
496
     (
497
      // Master 0
498
      // Inputs to arbiter from master
499
      .wbm0_adr_o                       (wbm_d_or12_adr_o),
500
      .wbm0_dat_o                       (wbm_d_or12_dat_o),
501
      .wbm0_sel_o                       (wbm_d_or12_sel_o),
502
      .wbm0_we_o                        (wbm_d_or12_we_o),
503
      .wbm0_cyc_o                       (wbm_d_or12_cyc_o),
504
      .wbm0_stb_o                       (wbm_d_or12_stb_o),
505
      .wbm0_cti_o                       (wbm_d_or12_cti_o),
506
      .wbm0_bte_o                       (wbm_d_or12_bte_o),
507
      // Outputs to master from arbiter
508
      .wbm0_dat_i                       (wbm_d_or12_dat_i),
509
      .wbm0_ack_i                       (wbm_d_or12_ack_i),
510
      .wbm0_err_i                       (wbm_d_or12_err_i),
511
      .wbm0_rty_i                       (wbm_d_or12_rty_i),
512
 
513
      // Master 0
514
      // Inputs to arbiter from master
515
      .wbm1_adr_o                       (wbm_d_dbg_adr_o),
516
      .wbm1_dat_o                       (wbm_d_dbg_dat_o),
517
      .wbm1_we_o                        (wbm_d_dbg_we_o),
518
      .wbm1_cyc_o                       (wbm_d_dbg_cyc_o),
519
      .wbm1_sel_o                       (wbm_d_dbg_sel_o),
520
      .wbm1_stb_o                       (wbm_d_dbg_stb_o),
521
      .wbm1_cti_o                       (wbm_d_dbg_cti_o),
522
      .wbm1_bte_o                       (wbm_d_dbg_bte_o),
523
      // Outputs to master from arbiter      
524
      .wbm1_dat_i                       (wbm_d_dbg_dat_i),
525
      .wbm1_ack_i                       (wbm_d_dbg_ack_i),
526
      .wbm1_err_i                       (wbm_d_dbg_err_i),
527
      .wbm1_rty_i                       (wbm_d_dbg_rty_i),
528
 
529
      // Slaves
530
 
531
      .wbs0_adr_i                       (wbs_d_mc0_adr_i),
532
      .wbs0_dat_i                       (wbs_d_mc0_dat_i),
533
      .wbs0_sel_i                       (wbs_d_mc0_sel_i),
534
      .wbs0_we_i                        (wbs_d_mc0_we_i),
535
      .wbs0_cyc_i                       (wbs_d_mc0_cyc_i),
536
      .wbs0_stb_i                       (wbs_d_mc0_stb_i),
537
      .wbs0_cti_i                       (wbs_d_mc0_cti_i),
538
      .wbs0_bte_i                       (wbs_d_mc0_bte_i),
539
      .wbs0_dat_o                       (wbs_d_mc0_dat_o),
540
      .wbs0_ack_o                       (wbs_d_mc0_ack_o),
541
      .wbs0_err_o                       (wbs_d_mc0_err_o),
542
      .wbs0_rty_o                       (wbs_d_mc0_rty_o),
543
 
544
      .wbs1_adr_i                       (wbs_d_eth0_adr_i),
545
      .wbs1_dat_i                       (wbs_d_eth0_dat_i),
546
      .wbs1_sel_i                       (wbs_d_eth0_sel_i),
547
      .wbs1_we_i                        (wbs_d_eth0_we_i),
548
      .wbs1_cyc_i                       (wbs_d_eth0_cyc_i),
549
      .wbs1_stb_i                       (wbs_d_eth0_stb_i),
550
      .wbs1_cti_i                       (wbs_d_eth0_cti_i),
551
      .wbs1_bte_i                       (wbs_d_eth0_bte_i),
552
      .wbs1_dat_o                       (wbs_d_eth0_dat_o),
553
      .wbs1_ack_o                       (wbs_d_eth0_ack_o),
554
      .wbs1_err_o                       (wbs_d_eth0_err_o),
555
      .wbs1_rty_o                       (wbs_d_eth0_rty_o),
556
 
557
      .wbs2_adr_i                       (wbm_b_d_adr_o),
558
      .wbs2_dat_i                       (wbm_b_d_dat_o),
559
      .wbs2_sel_i                       (wbm_b_d_sel_o),
560
      .wbs2_we_i                        (wbm_b_d_we_o),
561
      .wbs2_cyc_i                       (wbm_b_d_cyc_o),
562
      .wbs2_stb_i                       (wbm_b_d_stb_o),
563
      .wbs2_cti_i                       (wbm_b_d_cti_o),
564
      .wbs2_bte_i                       (wbm_b_d_bte_o),
565
      .wbs2_dat_o                       (wbm_b_d_dat_i),
566
      .wbs2_ack_o                       (wbm_b_d_ack_i),
567
      .wbs2_err_o                       (wbm_b_d_err_i),
568
      .wbs2_rty_o                       (wbm_b_d_rty_i),
569
 
570
      // Clock, reset inputs
571
      .wb_clk                   (wb_clk),
572
      .wb_rst                   (wb_rst));
573
 
574
   // These settings are from top level params file
575
   defparam arbiter_dbus0.wb_addr_match_width = dbus_arb_wb_addr_match_width;
576
   defparam arbiter_dbus0.wb_num_slaves = dbus_arb_wb_num_slaves;
577
   defparam arbiter_dbus0.slave0_adr = dbus_arb_slave0_adr;
578
   defparam arbiter_dbus0.slave1_adr = dbus_arb_slave1_adr;
579
 
580
   //
581
   // Wishbone byte-wide bus arbiter
582
   //   
583
 
584
   arbiter_bytebus arbiter_bytebus0
585
     (
586
 
587
      // Master 0
588
      // Inputs to arbiter from master
589
      .wbm0_adr_o                       (wbm_b_d_adr_o),
590
      .wbm0_dat_o                       (wbm_b_d_dat_o),
591
      .wbm0_sel_o                       (wbm_b_d_sel_o),
592
      .wbm0_we_o                        (wbm_b_d_we_o),
593
      .wbm0_cyc_o                       (wbm_b_d_cyc_o),
594
      .wbm0_stb_o                       (wbm_b_d_stb_o),
595
      .wbm0_cti_o                       (wbm_b_d_cti_o),
596
      .wbm0_bte_o                       (wbm_b_d_bte_o),
597
      // Outputs to master from arbiter
598
      .wbm0_dat_i                       (wbm_b_d_dat_i),
599
      .wbm0_ack_i                       (wbm_b_d_ack_i),
600
      .wbm0_err_i                       (wbm_b_d_err_i),
601
      .wbm0_rty_i                       (wbm_b_d_rty_i),
602
 
603
      // Byte bus slaves
604
 
605
      .wbs0_adr_i                       (wbs_d_uart0_adr_i),
606
      .wbs0_dat_i                       (wbs_d_uart0_dat_i),
607
      .wbs0_we_i                        (wbs_d_uart0_we_i),
608
      .wbs0_cyc_i                       (wbs_d_uart0_cyc_i),
609
      .wbs0_stb_i                       (wbs_d_uart0_stb_i),
610
      .wbs0_cti_i                       (wbs_d_uart0_cti_i),
611
      .wbs0_bte_i                       (wbs_d_uart0_bte_i),
612
      .wbs0_dat_o                       (wbs_d_uart0_dat_o),
613
      .wbs0_ack_o                       (wbs_d_uart0_ack_o),
614
      .wbs0_err_o                       (wbs_d_uart0_err_o),
615
      .wbs0_rty_o                       (wbs_d_uart0_rty_o),
616
 
617
      .wbs1_adr_i                       (wbs_d_gpio0_adr_i),
618
      .wbs1_dat_i                       (wbs_d_gpio0_dat_i),
619
      .wbs1_we_i                        (wbs_d_gpio0_we_i),
620
      .wbs1_cyc_i                       (wbs_d_gpio0_cyc_i),
621
      .wbs1_stb_i                       (wbs_d_gpio0_stb_i),
622
      .wbs1_cti_i                       (wbs_d_gpio0_cti_i),
623
      .wbs1_bte_i                       (wbs_d_gpio0_bte_i),
624
      .wbs1_dat_o                       (wbs_d_gpio0_dat_o),
625
      .wbs1_ack_o                       (wbs_d_gpio0_ack_o),
626
      .wbs1_err_o                       (wbs_d_gpio0_err_o),
627
      .wbs1_rty_o                       (wbs_d_gpio0_rty_o),
628
 
629
      .wbs2_adr_i                       (wbs_d_i2c0_adr_i),
630
      .wbs2_dat_i                       (wbs_d_i2c0_dat_i),
631
      .wbs2_we_i                        (wbs_d_i2c0_we_i),
632
      .wbs2_cyc_i                       (wbs_d_i2c0_cyc_i),
633
      .wbs2_stb_i                       (wbs_d_i2c0_stb_i),
634
      .wbs2_cti_i                       (wbs_d_i2c0_cti_i),
635
      .wbs2_bte_i                       (wbs_d_i2c0_bte_i),
636
      .wbs2_dat_o                       (wbs_d_i2c0_dat_o),
637
      .wbs2_ack_o                       (wbs_d_i2c0_ack_o),
638
      .wbs2_err_o                       (wbs_d_i2c0_err_o),
639
      .wbs2_rty_o                       (wbs_d_i2c0_rty_o),
640
 
641
      .wbs3_adr_i                       (wbs_d_i2c1_adr_i),
642
      .wbs3_dat_i                       (wbs_d_i2c1_dat_i),
643
      .wbs3_we_i                        (wbs_d_i2c1_we_i),
644
      .wbs3_cyc_i                       (wbs_d_i2c1_cyc_i),
645
      .wbs3_stb_i                       (wbs_d_i2c1_stb_i),
646
      .wbs3_cti_i                       (wbs_d_i2c1_cti_i),
647
      .wbs3_bte_i                       (wbs_d_i2c1_bte_i),
648
      .wbs3_dat_o                       (wbs_d_i2c1_dat_o),
649
      .wbs3_ack_o                       (wbs_d_i2c1_ack_o),
650
      .wbs3_err_o                       (wbs_d_i2c1_err_o),
651
      .wbs3_rty_o                       (wbs_d_i2c1_rty_o),
652
 
653
      .wbs4_adr_i                       (wbs_d_spi0_adr_i),
654
      .wbs4_dat_i                       (wbs_d_spi0_dat_i),
655
      .wbs4_we_i                        (wbs_d_spi0_we_i),
656
      .wbs4_cyc_i                       (wbs_d_spi0_cyc_i),
657
      .wbs4_stb_i                       (wbs_d_spi0_stb_i),
658
      .wbs4_cti_i                       (wbs_d_spi0_cti_i),
659
      .wbs4_bte_i                       (wbs_d_spi0_bte_i),
660
      .wbs4_dat_o                       (wbs_d_spi0_dat_o),
661
      .wbs4_ack_o                       (wbs_d_spi0_ack_o),
662
      .wbs4_err_o                       (wbs_d_spi0_err_o),
663
      .wbs4_rty_o                       (wbs_d_spi0_rty_o),
664
 
665
      // Clock, reset inputs
666
      .wb_clk                   (wb_clk),
667
      .wb_rst                   (wb_rst));
668
 
669
   defparam arbiter_bytebus0.wb_addr_match_width = bbus_arb_wb_addr_match_width;
670
   defparam arbiter_bytebus0.wb_num_slaves = bbus_arb_wb_num_slaves;
671
 
672
   defparam arbiter_bytebus0.slave0_adr = bbus_arb_slave0_adr;
673
   defparam arbiter_bytebus0.slave1_adr = bbus_arb_slave1_adr;
674
   defparam arbiter_bytebus0.slave2_adr = bbus_arb_slave2_adr;
675
   defparam arbiter_bytebus0.slave3_adr = bbus_arb_slave3_adr;
676
   defparam arbiter_bytebus0.slave4_adr = bbus_arb_slave4_adr;
677
 
678
 
679
`ifdef JTAG_DEBUG
680
   ////////////////////////////////////////////////////////////////////////
681
   //
682
   // JTAG TAP
683
   // 
684
   ////////////////////////////////////////////////////////////////////////
685
 
686
   //
687
   // Wires
688
   //
689
   wire                                   dbg_if_select;
690
   wire                                   dbg_if_tdo;
691
   wire                                   jtag_tap_tdo;
692
   wire                                   jtag_tap_shift_dr, jtag_tap_pause_dr,
693
                                          jtag_tap_upate_dr, jtag_tap_capture_dr;
694
   //
695
   // Instantiation
696
   //
697
 
698
   jtag_tap jtag_tap0
699
     (
700
      // Ports to pads
701
      .tdo_pad_o                        (tdo_pad_o),
702
      .tms_pad_i                        (tms_pad_i),
703
      .tck_pad_i                        (dbg_tck),
704
      .trst_pad_i                       (async_rst),
705
      .tdi_pad_i                        (tdi_pad_i),
706
 
707
      .tdo_padoe_o                      (tdo_padoe_o),
708
 
709
      .tdo_o                            (jtag_tap_tdo),
710
 
711
      .shift_dr_o                       (jtag_tap_shift_dr),
712
      .pause_dr_o                       (jtag_tap_pause_dr),
713
      .update_dr_o                      (jtag_tap_update_dr),
714
      .capture_dr_o                     (jtag_tap_capture_dr),
715
 
716
      .extest_select_o                  (),
717
      .sample_preload_select_o          (),
718
      .mbist_select_o                   (),
719
      .debug_select_o                   (dbg_if_select),
720
 
721
 
722
      .bs_chain_tdi_i                   (1'b0),
723
      .mbist_tdi_i                      (1'b0),
724
      .debug_tdi_i                      (dbg_if_tdo)
725
 
726
      );
727
 
728
   ////////////////////////////////////////////////////////////////////////
729
`endif //  `ifdef JTAG_DEBUG
730
 
731
   ////////////////////////////////////////////////////////////////////////
732
   //
733
   // OpenRISC processor
734
   // 
735
   ////////////////////////////////////////////////////////////////////////
736
 
737
   // 
738
   // Wires
739
   // 
740
 
741
   wire [30:0]                             or1200_pic_ints;
742
 
743
   wire [31:0]                             or1200_dbg_dat_i;
744
   wire [31:0]                             or1200_dbg_adr_i;
745
   wire                                   or1200_dbg_we_i;
746
   wire                                   or1200_dbg_stb_i;
747
   wire                                   or1200_dbg_ack_o;
748
   wire [31:0]                             or1200_dbg_dat_o;
749
 
750
   wire                                   or1200_dbg_stall_i;
751
   wire                                   or1200_dbg_ewt_i;
752
   wire [3:0]                              or1200_dbg_lss_o;
753
   wire [1:0]                              or1200_dbg_is_o;
754
   wire [10:0]                             or1200_dbg_wp_o;
755
   wire                                   or1200_dbg_bp_o;
756
   wire                                   or1200_dbg_rst;
757
 
758
   wire                                   or1200_clk, or1200_rst;
759
   wire                                   sig_tick;
760
 
761
   //
762
   // Assigns
763
   //
764
   assign or1200_clk = wb_clk;
765
   assign or1200_rst = wb_rst | or1200_dbg_rst;
766
 
767
   // 
768
   // Instantiation
769
   //    
770
   or1200_top or1200_top0
771
       (
772
        // Instruction bus, clocks, reset
773
        .iwb_clk_i                      (wb_clk),
774
        .iwb_rst_i                      (wb_rst),
775
        .iwb_ack_i                      (wbm_i_or12_ack_i),
776
        .iwb_err_i                      (wbm_i_or12_err_i),
777
        .iwb_rty_i                      (wbm_i_or12_rty_i),
778
        .iwb_dat_i                      (wbm_i_or12_dat_i),
779
 
780
        .iwb_cyc_o                      (wbm_i_or12_cyc_o),
781
        .iwb_adr_o                      (wbm_i_or12_adr_o),
782
        .iwb_stb_o                      (wbm_i_or12_stb_o),
783
        .iwb_we_o                               (wbm_i_or12_we_o),
784
        .iwb_sel_o                      (wbm_i_or12_sel_o),
785
        .iwb_dat_o                      (wbm_i_or12_dat_o),
786
        .iwb_cti_o                      (wbm_i_or12_cti_o),
787
        .iwb_bte_o                      (wbm_i_or12_bte_o),
788
 
789
        // Data bus, clocks, reset            
790
        .dwb_clk_i                      (wb_clk),
791
        .dwb_rst_i                      (wb_rst),
792
        .dwb_ack_i                      (wbm_d_or12_ack_i),
793
        .dwb_err_i                      (wbm_d_or12_err_i),
794
        .dwb_rty_i                      (wbm_d_or12_rty_i),
795
        .dwb_dat_i                      (wbm_d_or12_dat_i),
796
 
797
        .dwb_cyc_o                      (wbm_d_or12_cyc_o),
798
        .dwb_adr_o                      (wbm_d_or12_adr_o),
799
        .dwb_stb_o                      (wbm_d_or12_stb_o),
800
        .dwb_we_o                               (wbm_d_or12_we_o),
801
        .dwb_sel_o                      (wbm_d_or12_sel_o),
802
        .dwb_dat_o                      (wbm_d_or12_dat_o),
803
        .dwb_cti_o                      (wbm_d_or12_cti_o),
804
        .dwb_bte_o                      (wbm_d_or12_bte_o),
805
 
806
        // Debug interface ports
807
        .dbg_stall_i                    (or1200_dbg_stall_i),
808
        //.dbg_ewt_i                    (or1200_dbg_ewt_i),
809
        .dbg_ewt_i                      (1'b0),
810
        .dbg_lss_o                      (or1200_dbg_lss_o),
811
        .dbg_is_o                               (or1200_dbg_is_o),
812
        .dbg_wp_o                               (or1200_dbg_wp_o),
813
        .dbg_bp_o                               (or1200_dbg_bp_o),
814
 
815
        .dbg_adr_i                      (or1200_dbg_adr_i),
816
        .dbg_we_i                               (or1200_dbg_we_i ),
817
        .dbg_stb_i                      (or1200_dbg_stb_i),
818
        .dbg_dat_i                      (or1200_dbg_dat_i),
819
        .dbg_dat_o                      (or1200_dbg_dat_o),
820
        .dbg_ack_o                      (or1200_dbg_ack_o),
821
 
822
        .pm_clksd_o                     (),
823
        .pm_dc_gate_o                   (),
824
        .pm_ic_gate_o                   (),
825
        .pm_dmmu_gate_o                 (),
826
        .pm_immu_gate_o                 (),
827
        .pm_tt_gate_o                   (),
828
        .pm_cpu_gate_o                  (),
829
        .pm_wakeup_o                    (),
830
        .pm_lvolt_o                     (),
831
 
832
        // Core clocks, resets
833
        .clk_i                          (or1200_clk),
834
        .rst_i                          (or1200_rst),
835
 
836
        .clmode_i                               (2'b00),
837
        // Interrupts      
838
        .pic_ints_i                     (or1200_pic_ints),
839
        .sig_tick(sig_tick),
840
        /*
841
         .mbist_so_o                    (),
842
         .mbist_si_i                    (0),
843
         .mbist_ctrl_i                  (0),
844
         */
845
 
846
        .pm_cpustall_i                  (1'b0)
847
 
848
        );
849
 
850
   ////////////////////////////////////////////////////////////////////////
851
 
852
 
853
`ifdef JTAG_DEBUG
854
   ////////////////////////////////////////////////////////////////////////
855
         //
856
   // OR1200 Debug Interface
857
   // 
858
   ////////////////////////////////////////////////////////////////////////
859
 
860
   dbg_if dbg_if0
861
     (
862
      // OR1200 interface
863
      .cpu0_clk_i                       (or1200_clk),
864
      .cpu0_rst_o                       (or1200_dbg_rst),
865
      .cpu0_addr_o                      (or1200_dbg_adr_i),
866
      .cpu0_data_o                      (or1200_dbg_dat_i),
867
      .cpu0_stb_o                       (or1200_dbg_stb_i),
868
      .cpu0_we_o                        (or1200_dbg_we_i),
869
      .cpu0_data_i                      (or1200_dbg_dat_o),
870
      .cpu0_ack_i                       (or1200_dbg_ack_o),
871
 
872
 
873
      .cpu0_stall_o                     (or1200_dbg_stall_i),
874
      .cpu0_bp_i                        (or1200_dbg_bp_o),
875
 
876
      // TAP interface
877
      .tck_i                            (dbg_tck),
878
      .tdi_i                            (jtag_tap_tdo),
879
      .tdo_o                            (dbg_if_tdo),
880
      .rst_i                            (wb_rst),
881
      .shift_dr_i                       (jtag_tap_shift_dr),
882
      .pause_dr_i                       (jtag_tap_pause_dr),
883
      .update_dr_i                      (jtag_tap_update_dr),
884
      .debug_select_i                   (dbg_if_select),
885
 
886
      // Wishbone debug master
887
      .wb_clk_i                         (wb_clk),
888
      .wb_dat_i                         (wbm_d_dbg_dat_i),
889
      .wb_ack_i                         (wbm_d_dbg_ack_i),
890
      .wb_err_i                         (wbm_d_dbg_err_i),
891
      .wb_adr_o                         (wbm_d_dbg_adr_o),
892
      .wb_dat_o                         (wbm_d_dbg_dat_o),
893
      .wb_cyc_o                         (wbm_d_dbg_cyc_o),
894
      .wb_stb_o                         (wbm_d_dbg_stb_o),
895
      .wb_sel_o                         (wbm_d_dbg_sel_o),
896
      .wb_we_o                          (wbm_d_dbg_we_o ),
897
      .wb_cti_o                         (wbm_d_dbg_cti_o),
898
      .wb_cab_o                         (/*   UNUSED  */),
899
      .wb_bte_o                         (wbm_d_dbg_bte_o)
900
      );
901
 
902
   ////////////////////////////////////////////////////////////////////////   
903
`else // !`ifdef JTAG_DEBUG
904
 
905
   assign wbm_d_dbg_adr_o = 0;
906
   assign wbm_d_dbg_dat_o = 0;
907
   assign wbm_d_dbg_cyc_o = 0;
908
   assign wbm_d_dbg_stb_o = 0;
909
   assign wbm_d_dbg_sel_o = 0;
910
   assign wbm_d_dbg_we_o  = 0;
911
   assign wbm_d_dbg_cti_o = 0;
912
   assign wbm_d_dbg_bte_o = 0;
913
 
914
   assign or1200_dbg_adr_i = 0;
915
   assign or1200_dbg_dat_i = 0;
916
   assign or1200_dbg_stb_i = 0;
917
   assign or1200_dbg_we_i = 0;
918
   assign or1200_dbg_stall_i = 0;
919
 
920
   ////////////////////////////////////////////////////////////////////////   
921
`endif // !`ifdef JTAG_DEBUG
922
 
923
`ifdef XILINX_DDR2
924
   ////////////////////////////////////////////////////////////////////////
925
   //
926
   // Xilinx MIG DDR2 controller, Wishbone interface
927
   // 
928
   ////////////////////////////////////////////////////////////////////////
929
   xilinx_ddr2 xilinx_ddr2_0
930
     (
931
      .wbm0_adr_i                       (wbm_eth0_adr_o),
932
      .wbm0_bte_i                       (wbm_eth0_bte_o),
933
      .wbm0_cti_i                       (wbm_eth0_cti_o),
934
      .wbm0_cyc_i                       (wbm_eth0_cyc_o),
935
      .wbm0_dat_i                       (wbm_eth0_dat_o),
936
      .wbm0_sel_i                       (wbm_eth0_sel_o),
937
      .wbm0_stb_i                       (wbm_eth0_stb_o),
938
      .wbm0_we_i                        (wbm_eth0_we_o),
939
      .wbm0_ack_o                       (wbm_eth0_ack_i),
940
      .wbm0_err_o                       (wbm_eth0_err_i),
941
      .wbm0_rty_o                       (wbm_eth0_rty_i),
942
      .wbm0_dat_o                       (wbm_eth0_dat_i),
943
 
944
      .wbm1_adr_i                       (wbs_d_mc0_adr_i),
945
      .wbm1_bte_i                       (wbs_d_mc0_bte_i),
946
      .wbm1_cti_i                       (wbs_d_mc0_cti_i),
947
      .wbm1_cyc_i                       (wbs_d_mc0_cyc_i),
948
      .wbm1_dat_i                       (wbs_d_mc0_dat_i),
949
      .wbm1_sel_i                       (wbs_d_mc0_sel_i),
950
      .wbm1_stb_i                       (wbs_d_mc0_stb_i),
951
      .wbm1_we_i                        (wbs_d_mc0_we_i),
952
      .wbm1_ack_o                       (wbs_d_mc0_ack_o),
953
      .wbm1_err_o                       (wbs_d_mc0_err_o),
954
      .wbm1_rty_o                       (wbs_d_mc0_rty_o),
955
      .wbm1_dat_o                       (wbs_d_mc0_dat_o),
956
 
957
      .wbm2_adr_i                       (wbs_i_mc0_adr_i),
958
      .wbm2_bte_i                       (wbs_i_mc0_bte_i),
959
      .wbm2_cti_i                       (wbs_i_mc0_cti_i),
960
      .wbm2_cyc_i                       (wbs_i_mc0_cyc_i),
961
      .wbm2_dat_i                       (wbs_i_mc0_dat_i),
962
      .wbm2_sel_i                       (wbs_i_mc0_sel_i),
963
      .wbm2_stb_i                       (wbs_i_mc0_stb_i),
964
      .wbm2_we_i                        (wbs_i_mc0_we_i),
965
      .wbm2_ack_o                       (wbs_i_mc0_ack_o),
966
      .wbm2_err_o                       (wbs_i_mc0_err_o),
967
      .wbm2_rty_o                       (wbs_i_mc0_rty_o),
968
      .wbm2_dat_o                       (wbs_i_mc0_dat_o),
969
 
970
      .wb_clk                           (wb_clk),
971
      .wb_rst                           (wb_rst),
972
 
973
      .ddr2_a                           (ddr2_a[12:0]),
974
      .ddr2_ba                          (ddr2_ba[1:0]),
975
      .ddr2_ras_n                       (ddr2_ras_n),
976
      .ddr2_cas_n                       (ddr2_cas_n),
977
      .ddr2_we_n                        (ddr2_we_n),
978
      .ddr2_cs_n                        (ddr2_cs_n),
979
      .ddr2_odt                         (ddr2_odt),
980
      .ddr2_cke                         (ddr2_cke),
981
      .ddr2_dm                          (ddr2_dm[7:0]),
982
      .ddr2_ck                          (ddr2_ck[1:0]),
983
      .ddr2_ck_n                        (ddr2_ck_n[1:0]),
984
      .ddr2_dq                          (ddr2_dq[63:0]),
985
      .ddr2_dqs                         (ddr2_dqs[7:0]),
986
      .ddr2_dqs_n                       (ddr2_dqs_n[7:0]),
987
      .ddr2_if_clk                      (ddr2_if_clk),
988
      .clk200                           (clk200),
989
      .ddr2_if_rst                      (ddr2_if_rst)
990
      );
991
 
992
`endif
993
 
994
 
995
   ////////////////////////////////////////////////////////////////////////
996
   //
997
   // ROM
998
   // 
999
   ////////////////////////////////////////////////////////////////////////
1000
 
1001
   rom rom0
1002
     (
1003
      .wb_dat_o                         (wbs_i_rom0_dat_o),
1004
      .wb_ack_o                         (wbs_i_rom0_ack_o),
1005
      .wb_adr_i                         (wbs_i_rom0_adr_i[(wbs_i_rom0_addr_width+2)-1:2]),
1006
      .wb_stb_i                         (wbs_i_rom0_stb_i),
1007
      .wb_cyc_i                         (wbs_i_rom0_cyc_i),
1008
      .wb_cti_i                         (wbs_i_rom0_cti_i),
1009
      .wb_bte_i                         (wbs_i_rom0_bte_i),
1010
      .wb_clk                           (wb_clk),
1011
      .wb_rst                           (wb_rst));
1012
 
1013
   defparam rom0.addr_width = wbs_i_rom0_addr_width;
1014
 
1015
   assign wbs_i_rom0_err_o = 0;
1016
   assign wbs_i_rom0_rty_o = 0;
1017
 
1018
   ////////////////////////////////////////////////////////////////////////
1019
 
1020
`ifdef RAM_WB
1021
   ////////////////////////////////////////////////////////////////////////
1022
   //
1023
   // Generic RAM
1024
   // 
1025
   ////////////////////////////////////////////////////////////////////////
1026
 
1027
   ram_wb ram_wb0
1028
     (
1029
      // Wishbone slave interface 0
1030
      .wbm0_dat_i                       (wbs_i_mc0_dat_i),
1031
      .wbm0_adr_i                       (wbs_i_mc0_adr_i),
1032
      .wbm0_sel_i                       (wbs_i_mc0_sel_i),
1033
      .wbm0_cti_i                       (wbs_i_mc0_cti_i),
1034
      .wbm0_bte_i                       (wbs_i_mc0_bte_i),
1035
      .wbm0_we_i                        (wbs_i_mc0_we_i ),
1036
      .wbm0_cyc_i                       (wbs_i_mc0_cyc_i),
1037
      .wbm0_stb_i                       (wbs_i_mc0_stb_i),
1038
      .wbm0_dat_o                       (wbs_i_mc0_dat_o),
1039
      .wbm0_ack_o                       (wbs_i_mc0_ack_o),
1040 439 julius
      .wbm0_err_o                       (wbs_i_mc0_err_o),
1041
      .wbm0_rty_o                       (wbs_i_mc0_rty_o),
1042 412 julius
      // Wishbone slave interface 1
1043
      .wbm1_dat_i                       (wbs_d_mc0_dat_i),
1044
      .wbm1_adr_i                       (wbs_d_mc0_adr_i),
1045
      .wbm1_sel_i                       (wbs_d_mc0_sel_i),
1046
      .wbm1_cti_i                       (wbs_d_mc0_cti_i),
1047
      .wbm1_bte_i                       (wbs_d_mc0_bte_i),
1048
      .wbm1_we_i                        (wbs_d_mc0_we_i ),
1049
      .wbm1_cyc_i                       (wbs_d_mc0_cyc_i),
1050
      .wbm1_stb_i                       (wbs_d_mc0_stb_i),
1051
      .wbm1_dat_o                       (wbs_d_mc0_dat_o),
1052
      .wbm1_ack_o                       (wbs_d_mc0_ack_o),
1053 439 julius
      .wbm1_err_o                       (wbs_d_mc0_err_o),
1054
      .wbm1_rty_o                       (wbs_d_mc0_rty_o),
1055
      // Wishbone slave interface 2
1056
      .wbm2_dat_i                       (wbm_eth0_dat_o),
1057
      .wbm2_adr_i                       (wbm_eth0_adr_o),
1058
      .wbm2_sel_i                       (wbm_eth0_sel_o),
1059
      .wbm2_cti_i                       (wbm_eth0_cti_o),
1060
      .wbm2_bte_i                       (wbm_eth0_bte_o),
1061
      .wbm2_we_i                        (wbm_eth0_we_o ),
1062
      .wbm2_cyc_i                       (wbm_eth0_cyc_o),
1063
      .wbm2_stb_i                       (wbm_eth0_stb_o),
1064
      .wbm2_dat_o                       (wbm_eth0_dat_i),
1065
      .wbm2_ack_o                       (wbm_eth0_ack_i),
1066
      .wbm2_err_o                       (wbm_eth0_err_i),
1067
      .wbm2_rty_o                       (wbm_eth0_rty_i),
1068 412 julius
      // Clock, reset
1069
      .wb_clk_i                         (wb_clk),
1070
      .wb_rst_i                         (wb_rst));
1071
 
1072
   defparam ram_wb0.aw = wb_aw;
1073
   defparam ram_wb0.dw = wb_dw;
1074 439 julius
 
1075
   defparam ram_wb0.mem_size_bytes = (8192*1024); // 8MB
1076
   defparam ram_wb0.mem_adr_width = 23; // log2(8192*1024)
1077 412 julius
   ////////////////////////////////////////////////////////////////////////
1078
`endif //  `ifdef RAM_WB
1079
 
1080
 
1081
`ifdef ETH0
1082
 
1083
   //
1084
   // Wires
1085
   //
1086
   wire        eth0_irq;
1087
   wire [3:0]  eth0_mtxd;
1088
   wire        eth0_mtxen;
1089
   wire        eth0_mtxerr;
1090
   wire        eth0_mtx_clk;
1091
   wire        eth0_mrx_clk;
1092
   wire [3:0]  eth0_mrxd;
1093
   wire        eth0_mrxdv;
1094
   wire        eth0_mrxerr;
1095
   wire        eth0_mcoll;
1096
   wire        eth0_mcrs;
1097
   wire        eth0_speed;
1098
   wire        eth0_duplex;
1099
   wire        eth0_link;
1100
   // Management interface wires
1101
   wire        eth0_md_i;
1102
   wire        eth0_md_o;
1103
   wire        eth0_md_oe;
1104
 
1105
 
1106
   //
1107
   // assigns
1108
 
1109
   // Hook up MII wires
1110
   assign eth0_mtx_clk   = eth0_tx_clk;
1111
   assign eth0_tx_data   = eth0_mtxd[3:0];
1112
   assign eth0_tx_en     = eth0_mtxen;
1113
   assign eth0_tx_er     = eth0_mtxerr;
1114
   assign eth0_mrxd[3:0] = eth0_rx_data;
1115
   assign eth0_mrxdv     = eth0_dv;
1116
   assign eth0_mrxerr    = eth0_rx_er;
1117
   assign eth0_mrx_clk   = eth0_rx_clk;
1118
   assign eth0_mcoll     = eth0_col;
1119
   assign eth0_mcrs      = eth0_crs;
1120
 
1121
`ifdef XILINX
1122
   // Xilinx primitive for MDIO tristate
1123
   IOBUF iobuf_phy_smi_data
1124
     (
1125
      // Outputs
1126
      .O                                 (eth0_md_i),
1127
      // Inouts
1128
      .IO                                (eth0_md_pad_io),
1129
      // Inputs
1130
      .I                                 (eth0_md_o),
1131
      .T                                 (!eth0_md_oe));
1132
`else // !`ifdef XILINX
1133
 
1134
   // Generic technology tristate control for management interface
1135
   assign eth0_md_pad_io = eth0_md_oe ? eth0_md_o : 1'bz;
1136
   assign eth0_md_i = eth0_md_pad_io;
1137
 
1138
`endif // !`ifdef XILINX
1139
 
1140
`ifdef ETH0_PHY_RST
1141
   assign eth0_rst_n_o = !wb_rst;
1142
`endif
1143
 
1144
   ethmac ethmac0
1145
     (
1146
      // Wishbone Slave interface
1147
      .wb_clk_i         (wb_clk),
1148
      .wb_rst_i         (wb_rst),
1149
      .wb_dat_i         (wbs_d_eth0_dat_i[31:0]),
1150
      .wb_adr_i         (wbs_d_eth0_adr_i[wbs_d_eth0_addr_width-1:2]),
1151
      .wb_sel_i         (wbs_d_eth0_sel_i[3:0]),
1152
      .wb_we_i          (wbs_d_eth0_we_i),
1153
      .wb_cyc_i         (wbs_d_eth0_cyc_i),
1154
      .wb_stb_i         (wbs_d_eth0_stb_i),
1155
      .wb_dat_o         (wbs_d_eth0_dat_o[31:0]),
1156
      .wb_err_o         (wbs_d_eth0_err_o),
1157
      .wb_ack_o         (wbs_d_eth0_ack_o),
1158
      // Wishbone Master Interface
1159
      .m_wb_adr_o       (wbm_eth0_adr_o[31:0]),
1160
      .m_wb_sel_o       (wbm_eth0_sel_o[3:0]),
1161
      .m_wb_we_o        (wbm_eth0_we_o),
1162
      .m_wb_dat_o       (wbm_eth0_dat_o[31:0]),
1163
      .m_wb_cyc_o       (wbm_eth0_cyc_o),
1164
      .m_wb_stb_o       (wbm_eth0_stb_o),
1165
      .m_wb_cti_o       (wbm_eth0_cti_o[2:0]),
1166
      .m_wb_bte_o       (wbm_eth0_bte_o[1:0]),
1167
      .m_wb_dat_i       (wbm_eth0_dat_i[31:0]),
1168
      .m_wb_ack_i       (wbm_eth0_ack_i),
1169
      .m_wb_err_i       (wbm_eth0_err_i),
1170
 
1171
      // Ethernet MII interface
1172
      // Transmit
1173
      .mtxd_pad_o       (eth0_mtxd[3:0]),
1174
      .mtxen_pad_o      (eth0_mtxen),
1175
      .mtxerr_pad_o     (eth0_mtxerr),
1176
      .mtx_clk_pad_i    (eth0_mtx_clk),
1177
      // Receive
1178
      .mrx_clk_pad_i    (eth0_mrx_clk),
1179
      .mrxd_pad_i       (eth0_mrxd[3:0]),
1180
      .mrxdv_pad_i      (eth0_mrxdv),
1181
      .mrxerr_pad_i     (eth0_mrxerr),
1182
      .mcoll_pad_i      (eth0_mcoll),
1183
      .mcrs_pad_i       (eth0_mcrs),
1184
      // Management interface
1185
      .md_pad_i         (eth0_md_i),
1186
      .mdc_pad_o        (eth0_mdc_pad_o),
1187
      .md_pad_o         (eth0_md_o),
1188
      .md_padoe_o       (eth0_md_oe),
1189
 
1190
      // Processor interrupt
1191
      .int_o            (eth0_irq)
1192
 
1193
      /*
1194
       .mbist_so_o                      (),
1195
       .mbist_si_i                      (),
1196
       .mbist_ctrl_i                    ()
1197
       */
1198
 
1199
      );
1200
 
1201
   assign wbs_d_eth0_rty_o = 0;
1202
 
1203
`else
1204
   assign wbs_d_eth0_dat_o = 0;
1205
   assign wbs_d_eth0_err_o = 0;
1206
   assign wbs_d_eth0_ack_o = 0;
1207
   assign wbs_d_eth0_rty_o = 0;
1208
   assign wbm_eth0_adr_o = 0;
1209
   assign wbm_eth0_sel_o = 0;
1210
   assign wbm_eth0_we_o = 0;
1211
   assign wbm_eth0_dat_o = 0;
1212
   assign wbm_eth0_cyc_o = 0;
1213
   assign wbm_eth0_stb_o = 0;
1214
   assign wbm_eth0_cti_o = 0;
1215
   assign wbm_eth0_bte_o = 0;
1216
`endif
1217
 
1218
`ifdef UART0
1219
   ////////////////////////////////////////////////////////////////////////
1220
   //
1221
   // UART0
1222
   // 
1223
   ////////////////////////////////////////////////////////////////////////
1224
 
1225
   //
1226
   // Wires
1227
   //
1228
   wire        uart0_srx;
1229
   wire        uart0_stx;
1230
 
1231
   wire        uart0_irq;
1232
 
1233
   //
1234
   // Assigns
1235
   //
1236
   assign wbs_d_uart0_err_o = 0;
1237
   assign wbs_d_uart0_rty_o = 0;
1238
 
1239
   // Two UART lines coming to single one (ensure they go high when unconnected)
1240 415 julius
   assign uart0_srx = uart0_srx_pad_i & uart0_srx_expheader_pad_i;
1241 412 julius
   assign uart0_stx_pad_o = uart0_stx;
1242
   assign uart0_stx_expheader_pad_o = uart0_stx;
1243
 
1244
 
1245
   uart16550 uart16550_0
1246
     (
1247
      // Wishbone slave interface
1248
      .wb_clk_i                         (wb_clk),
1249
      .wb_rst_i                         (wb_rst),
1250
      .wb_adr_i                         (wbs_d_uart0_adr_i[uart0_addr_width-1:0]),
1251
      .wb_dat_i                         (wbs_d_uart0_dat_i),
1252
      .wb_we_i                          (wbs_d_uart0_we_i),
1253
      .wb_stb_i                         (wbs_d_uart0_stb_i),
1254
      .wb_cyc_i                         (wbs_d_uart0_cyc_i),
1255
      //.wb_sel_i                               (),
1256
      .wb_dat_o                         (wbs_d_uart0_dat_o),
1257
      .wb_ack_o                         (wbs_d_uart0_ack_o),
1258
 
1259
      .int_o                            (uart0_irq),
1260
      .stx_pad_o                        (uart0_stx),
1261
      .rts_pad_o                        (),
1262
      .dtr_pad_o                        (),
1263
      //      .baud_o                           (),
1264
      // Inputs
1265
      .srx_pad_i                        (uart0_srx),
1266
      .cts_pad_i                        (1'b0),
1267
      .dsr_pad_i                        (1'b0),
1268
      .ri_pad_i                         (1'b0),
1269
      .dcd_pad_i                        (1'b0));
1270
 
1271
   ////////////////////////////////////////////////////////////////////////          
1272
`else // !`ifdef UART0
1273
 
1274
   //
1275
   // Assigns
1276
   //
1277
   assign wbs_d_uart0_err_o = 0;
1278
   assign wbs_d_uart0_rty_o = 0;
1279
   assign wbs_d_uart0_ack_o = 0;
1280
   assign wbs_d_uart0_dat_o = 0;
1281
 
1282
   ////////////////////////////////////////////////////////////////////////       
1283
`endif // !`ifdef UART0
1284
 
1285
`ifdef SPI0
1286
   ////////////////////////////////////////////////////////////////////////
1287
   //
1288
   // SPI0 controller
1289
   // 
1290
   ////////////////////////////////////////////////////////////////////////
1291
 
1292
   //
1293
   // Wires
1294
   //
1295
   wire                              spi0_irq;
1296
 
1297
   //
1298
   // Assigns
1299
   //
1300
   assign wbs_d_spi0_err_o = 0;
1301
   assign wbs_d_spi0_rty_o = 0;
1302
   //assign spi0_hold_n_o = 1;
1303
   //assign spi0_w_n_o = 1;
1304
 
1305
 
1306
   simple_spi spi0
1307
     (
1308
      // Wishbone slave interface
1309
      .clk_i                            (wb_clk),
1310
      .rst_i                            (wb_rst),
1311
      .cyc_i                            (wbs_d_spi0_cyc_i),
1312
      .stb_i                            (wbs_d_spi0_stb_i),
1313
      .adr_i                            (wbs_d_spi0_adr_i[spi0_wb_adr_width-1:0]),
1314
      .we_i                             (wbs_d_spi0_we_i),
1315
      .dat_i                            (wbs_d_spi0_dat_i),
1316
      .dat_o                            (wbs_d_spi0_dat_o),
1317
      .ack_o                            (wbs_d_spi0_ack_o),
1318
      // SPI IRQ
1319
      .inta_o                           (spi0_irq),
1320
      // External SPI interface
1321
      .sck_o                            (spi0_sck_o),
1322
      .ss_o                             (spi0_ss_o),
1323
      .mosi_o                           (spi0_mosi_o),
1324
      .miso_i                           (spi0_miso_i)
1325
      );
1326
 
1327
   defparam spi0.slave_select_width = spi0_ss_width;
1328 415 julius
 
1329
   // SPI clock and MISO lines must go through STARTUP_VIRTEX5 block.
1330
   STARTUP_VIRTEX5 startup_virtex5
1331
     (
1332
      .CFGCLK(),
1333
      .CFGMCLK(),
1334
      .DINSPI(spi0_miso_i),
1335
      .EOS(),
1336
      .TCKSPI(),
1337
      .CLK(),
1338
      .GSR(1'b0),
1339
      .GTS(1'b0),
1340
      .USRCCLKO(spi0_sck_o),
1341
      .USRCCLKTS(1'b0),
1342
      .USRDONEO(),
1343
      .USRDONETS()
1344
      );
1345 412 julius
 
1346
   ////////////////////////////////////////////////////////////////////////   
1347
`else // !`ifdef SPI0
1348
 
1349
   //
1350
   // Assigns
1351
   //
1352
   assign wbs_d_spi0_dat_o = 0;
1353
   assign wbs_d_spi0_ack_o = 0;
1354
   assign wbs_d_spi0_err_o = 0;
1355
   assign wbs_d_spi0_rty_o = 0;
1356
 
1357
   ////////////////////////////////////////////////////////////////////////
1358
`endif // !`ifdef SPI0   
1359
 
1360
 
1361
`ifdef I2C0
1362
   ////////////////////////////////////////////////////////////////////////
1363
   //
1364
   // i2c controller 0
1365
   // 
1366
   ////////////////////////////////////////////////////////////////////////
1367
 
1368
   //
1369
   // Wires
1370
   //
1371
   wire                              i2c0_irq;
1372
   wire                              scl0_pad_o;
1373
   wire                              scl0_padoen_o;
1374
   wire                              sda0_pad_o;
1375
   wire                              sda0_padoen_o;
1376
 
1377
  i2c_master_slave
1378
    #
1379
    (
1380
     .DEFAULT_SLAVE_ADDR(HV0_SADR)
1381
    )
1382
  i2c_master_slave0
1383
    (
1384
     .wb_clk_i                       (wb_clk),
1385
     .wb_rst_i                       (wb_rst),
1386
     .arst_i                         (wb_rst),
1387
     .wb_adr_i                       (wbs_d_i2c0_adr_i[i2c_0_wb_adr_width-1:0]),
1388
     .wb_dat_i                       (wbs_d_i2c0_dat_i),
1389
     .wb_we_i                        (wbs_d_i2c0_we_i ),
1390
     .wb_cyc_i                       (wbs_d_i2c0_cyc_i),
1391
     .wb_stb_i                       (wbs_d_i2c0_stb_i),
1392
     .wb_dat_o                       (wbs_d_i2c0_dat_o),
1393
     .wb_ack_o                       (wbs_d_i2c0_ack_o),
1394
     .scl_pad_i                      (i2c0_scl_io     ),
1395
     .scl_pad_o                      (scl0_pad_o         ),
1396
     .scl_padoen_o                   (scl0_padoen_o      ),
1397
     .sda_pad_i                      (i2c0_sda_io        ),
1398
     .sda_pad_o                      (sda0_pad_o         ),
1399
     .sda_padoen_o                   (sda0_padoen_o      ),
1400
 
1401
      // Interrupt
1402
     .wb_inta_o                      (i2c0_irq)
1403
 
1404
      );
1405
 
1406
   assign wbs_d_i2c0_err_o = 0;
1407
   assign wbs_d_i2c0_rty_o = 0;
1408
 
1409
   // i2c phy lines
1410
   assign i2c0_scl_io = scl0_padoen_o ? 1'bz : scl0_pad_o;
1411
   assign i2c0_sda_io = sda0_padoen_o ? 1'bz : sda0_pad_o;
1412
 
1413
 
1414
   ////////////////////////////////////////////////////////////////////////
1415
`else // !`ifdef I2C0
1416
 
1417
   assign wbs_d_i2c0_dat_o = 0;
1418
   assign wbs_d_i2c0_ack_o = 0;
1419
   assign wbs_d_i2c0_err_o = 0;
1420
   assign wbs_d_i2c0_rty_o = 0;
1421
 
1422
   ////////////////////////////////////////////////////////////////////////
1423
`endif // !`ifdef I2C0   
1424
 
1425
`ifdef I2C1
1426
   ////////////////////////////////////////////////////////////////////////
1427
   //
1428
   // i2c controller 1
1429
   // 
1430
   ////////////////////////////////////////////////////////////////////////
1431
 
1432
   //
1433
   // Wires
1434
   //
1435
   wire                              i2c1_irq;
1436
   wire                              scl1_pad_o;
1437
   wire                              scl1_padoen_o;
1438
   wire                              sda1_pad_o;
1439
   wire                              sda1_padoen_o;
1440
 
1441
   i2c_master_slave
1442
    #
1443
    (
1444
     .DEFAULT_SLAVE_ADDR(HV1_SADR)
1445
    )
1446
   i2c_master_slave1
1447
     (
1448
      .wb_clk_i                      (wb_clk),
1449
      .wb_rst_i                      (wb_rst),
1450
      .arst_i                        (wb_rst),
1451
      .wb_adr_i                      (wbs_d_i2c1_adr_i[i2c_1_wb_adr_width-1:0]),
1452
      .wb_dat_i                      (wbs_d_i2c1_dat_i),
1453
      .wb_we_i                       (wbs_d_i2c1_we_i ),
1454
      .wb_cyc_i                      (wbs_d_i2c1_cyc_i),
1455
      .wb_stb_i                      (wbs_d_i2c1_stb_i),
1456
      .wb_dat_o                      (wbs_d_i2c1_dat_o),
1457
      .wb_ack_o                      (wbs_d_i2c1_ack_o),
1458
      .scl_pad_i                     (i2c1_scl_io     ),
1459
      .scl_pad_o                     (scl1_pad_o         ),
1460
      .scl_padoen_o                  (scl1_padoen_o      ),
1461
      .sda_pad_i                     (i2c1_sda_io        ),
1462
      .sda_pad_o                     (sda1_pad_o         ),
1463
      .sda_padoen_o                  (sda1_padoen_o      ),
1464
 
1465
      // Interrupt
1466
      .wb_inta_o                     (i2c1_irq)
1467
 
1468
      );
1469
 
1470
   assign wbs_d_i2c1_err_o = 0;
1471
   assign wbs_d_i2c1_rty_o = 0;
1472
 
1473
   // i2c phy lines
1474
   assign i2c1_scl_io = scl1_padoen_o ? 1'bz : scl1_pad_o;
1475
   assign i2c1_sda_io = sda1_padoen_o ? 1'bz : sda1_pad_o;
1476
 
1477
   ////////////////////////////////////////////////////////////////////////
1478
`else // !`ifdef I2C1   
1479
 
1480
   assign wbs_d_i2c1_dat_o = 0;
1481
   assign wbs_d_i2c1_ack_o = 0;
1482
   assign wbs_d_i2c1_err_o = 0;
1483
   assign wbs_d_i2c1_rty_o = 0;
1484
 
1485
   ////////////////////////////////////////////////////////////////////////
1486
`endif // !`ifdef I2C1   
1487
 
1488
`ifdef GPIO0
1489
   ////////////////////////////////////////////////////////////////////////
1490
   //
1491
   // GPIO 0
1492
   // 
1493
   ////////////////////////////////////////////////////////////////////////
1494
 
1495
   gpio gpio0
1496
     (
1497
      // GPIO bus
1498
      .gpio_io                          (gpio0_io[gpio0_io_width-1:0]),
1499
      // Wishbone slave interface
1500
      .wb_adr_i                         (wbs_d_gpio0_adr_i[gpio0_wb_adr_width-1:0]),
1501
      .wb_dat_i                         (wbs_d_gpio0_dat_i),
1502
      .wb_we_i                          (wbs_d_gpio0_we_i),
1503
      .wb_cyc_i                         (wbs_d_gpio0_cyc_i),
1504
      .wb_stb_i                         (wbs_d_gpio0_stb_i),
1505
      .wb_cti_i                         (wbs_d_gpio0_cti_i),
1506
      .wb_bte_i                         (wbs_d_gpio0_bte_i),
1507
      .wb_dat_o                         (wbs_d_gpio0_dat_o),
1508
      .wb_ack_o                         (wbs_d_gpio0_ack_o),
1509
      .wb_err_o                         (wbs_d_gpio0_err_o),
1510
      .wb_rty_o                         (wbs_d_gpio0_rty_o),
1511
 
1512
      .wb_clk                           (wb_clk),
1513
      .wb_rst                           (wb_rst)
1514
      );
1515
 
1516
   defparam gpio0.gpio_io_width = gpio0_io_width;
1517
   defparam gpio0.gpio_dir_reset_val = gpio0_dir_reset_val;
1518
   defparam gpio0.gpio_o_reset_val = gpio0_o_reset_val;
1519
 
1520
   ////////////////////////////////////////////////////////////////////////
1521
`else // !`ifdef GPIO0
1522
   assign wbs_d_gpio0_dat_o = 0;
1523
   assign wbs_d_gpio0_ack_o = 0;
1524
   assign wbs_d_gpio0_err_o = 0;
1525
   assign wbs_d_gpio0_rty_o = 0;
1526
   ////////////////////////////////////////////////////////////////////////
1527
`endif // !`ifdef GPIO0
1528
 
1529
   ////////////////////////////////////////////////////////////////////////
1530
   //
1531
   // OR1200 Interrupt assignment
1532
   // 
1533
   ////////////////////////////////////////////////////////////////////////
1534
 
1535
   assign or1200_pic_ints[0] = 0; // Non-maskable inside OR1200
1536
   assign or1200_pic_ints[1] = 0; // Non-maskable inside OR1200
1537
`ifdef UART0
1538
   assign or1200_pic_ints[2] = uart0_irq;
1539
`else
1540
   assign or1200_pic_ints[2] = 0;
1541
`endif
1542
   assign or1200_pic_ints[3] = 0;
1543
`ifdef ETH0
1544
   assign or1200_pic_ints[4] = eth0_irq;
1545
`else
1546
   assign or1200_pic_ints[4] = 0;
1547
`endif
1548
   assign or1200_pic_ints[5] = 0;
1549
`ifdef SPI0
1550
   assign or1200_pic_ints[6] = spi0_irq;
1551
`else
1552
   assign or1200_pic_ints[6] = 0;
1553
`endif
1554
   assign or1200_pic_ints[7] = 0;
1555
   assign or1200_pic_ints[8] = 0;
1556
   assign or1200_pic_ints[9] = 0;
1557
`ifdef I2C0
1558
   assign or1200_pic_ints[10] = i2c0_irq;
1559
`else
1560
   assign or1200_pic_ints[10] = 0;
1561
`endif
1562
`ifdef I2C1
1563
   assign or1200_pic_ints[11] = i2c1_irq;
1564
`else
1565
   assign or1200_pic_ints[11] = 0;
1566
`endif
1567
   assign or1200_pic_ints[12] = 0;
1568
   assign or1200_pic_ints[13] = 0;
1569
   assign or1200_pic_ints[14] = 0;
1570
   assign or1200_pic_ints[15] = 0;
1571
   assign or1200_pic_ints[16] = 0;
1572
   assign or1200_pic_ints[17] = 0;
1573
   assign or1200_pic_ints[18] = 0;
1574
   assign or1200_pic_ints[19] = 0;
1575
   assign or1200_pic_ints[20] = 0;
1576
   assign or1200_pic_ints[21] = 0;
1577
   assign or1200_pic_ints[22] = 0;
1578
   assign or1200_pic_ints[23] = 0;
1579
   assign or1200_pic_ints[24] = 0;
1580
   assign or1200_pic_ints[25] = 0;
1581
   assign or1200_pic_ints[26] = 0;
1582
   assign or1200_pic_ints[27] = 0;
1583
   assign or1200_pic_ints[28] = 0;
1584
   assign or1200_pic_ints[29] = 0;
1585
   assign or1200_pic_ints[30] = 0;
1586
 
1587
endmodule // orpsoc_top
1588
 
1589
 

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