Subversion Repositories openrisc

//*****************************************************************************

// DISCLAIMER OF LIABILITY

//

// This file contains proprietary and confidential information of

// Xilinx, Inc. ("Xilinx"), that is distributed under a license

// from Xilinx, and may be used, copied and/or disclosed only

// pursuant to the terms of a valid license agreement with Xilinx.

//

// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION

// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER

// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT

// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,

// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx

// does not warrant that functions included in the Materials will

// meet the requirements of Licensee, or that the operation of the

// Materials will be uninterrupted or error-free, or that defects

// in the Materials will be corrected. Furthermore, Xilinx does

// not warrant or make any representations regarding use, or the

// results of the use, of the Materials in terms of correctness,

// accuracy, reliability or otherwise.

//

// Xilinx products are not designed or intended to be fail-safe,

// or for use in any application requiring fail-safe performance,

// such as life-support or safety devices or systems, Class III

// medical devices, nuclear facilities, applications related to

// the deployment of airbags, or any other applications that could

// lead to death, personal injury or severe property or

// environmental damage (individually and collectively, "critical

// applications"). Customer assumes the sole risk and liability

// of any use of Xilinx products in critical applications,

// subject only to applicable laws and regulations governing

// limitations on product liability.

//

// Copyright 2006, 2007, 2008 Xilinx, Inc.

// All rights reserved.

//

// This disclaimer and copyright notice must be retained as part

// of this file at all times.

//*****************************************************************************

//   ____  ____

//  /   /\/   /

// /___/  \  /    Vendor: Xilinx

// \   \   \/     Version: 3.0

//  \   \         Application: MIG

//  /   /         Filename: ddr2_ctrl.v

// /___/   /\     Date Last Modified: $Date: 2008/12/23 14:26:00 $

// \   \  /  \    Date Created: Wed Aug 30 2006

//  \___\/\___\

//

//

//Device: Virtex-5

//Design Name: DDR/DDR2

//Purpose:

//   This module is the main control logic of the memory interface. All

//   commands are issued from here according to the burst, CAS Latency and the

//   user commands.

//Reference:

//Revision History:

//   Rev 1.2 - Fixed auto refresh to activate bug. KP 11-19-2007

//   Rev 1.3 - For Dual Rank parts support CS logic modified. KP. 05/08/08

//   Rev 1.4 - AUTO_REFRESH_WAIT state modified for Auto Refresh flag asserted

//             immediately after calibration is completed. KP. 07/28/08

//   Rev 1.5 - Assignment of bank_valid_r is modified to fix a bug in 

//             Bank Management logic. PK. 10/29/08

//*****************************************************************************

`timescale 1ns/1ps

module ddr2_ctrl #

  (

   // Following parameters are for 72-bit RDIMM design (for ML561 Reference

   // board design). Actual values may be different. Actual parameters values

   // are passed from design top module ddr2_mig module. Please refer to

   // the ddr2_mig module for actual values.

   parameter BANK_WIDTH    = 2,

   parameter COL_WIDTH     = 10,

   parameter CS_BITS       = 0,

   parameter CS_NUM        = 1,

   parameter ROW_WIDTH     = 14,

   parameter ADDITIVE_LAT  = 0,

   parameter BURST_LEN     = 4,

   parameter CAS_LAT       = 5,

   parameter ECC_ENABLE    = 0,

   parameter REG_ENABLE    = 1,

   parameter TREFI_NS      = 7800,

   parameter TRAS          = 40000,

   parameter TRCD          = 15000,

   parameter TRRD          = 10000,

   parameter TRFC          = 105000,

   parameter TRP           = 15000,

   parameter TRTP          = 7500,

   parameter TWR           = 15000,

   parameter TWTR          = 10000,

   parameter CLK_PERIOD    = 3000,

   parameter MULTI_BANK_EN = 1,

   parameter TWO_T_TIME_EN = 0,

   parameter DDR_TYPE      = 1

   )

  (

   input                   clk,

   input                   rst,

   input [2:0]             af_cmd,

   input [30:0]            af_addr,

   input                   af_empty,

   input                   phy_init_done,

   output                  ctrl_ref_flag,

   output                  ctrl_af_rden,

   output reg              ctrl_wren,

   output reg              ctrl_rden,

   output [ROW_WIDTH-1:0]  ctrl_addr,

   output [BANK_WIDTH-1:0] ctrl_ba,

   output                  ctrl_ras_n,

   output                  ctrl_cas_n,

   output                  ctrl_we_n,

   output [CS_NUM-1:0]     ctrl_cs_n

   );

  // input address split into various ranges

  localparam ROW_RANGE_START     = COL_WIDTH;

  localparam ROW_RANGE_END       = ROW_WIDTH + ROW_RANGE_START - 1;

  localparam BANK_RANGE_START    = ROW_RANGE_END + 1;

  localparam BANK_RANGE_END      = BANK_WIDTH + BANK_RANGE_START - 1;

  localparam CS_RANGE_START      = BANK_RANGE_START + BANK_WIDTH;

  localparam CS_RANGE_END        = CS_BITS + CS_RANGE_START - 1;

  // compare address (for determining bank/row hits) split into various ranges

  // (compare address doesn't include column bits)

  localparam CMP_WIDTH            = CS_BITS + BANK_WIDTH + ROW_WIDTH;

  localparam CMP_ROW_RANGE_START  = 0;

  localparam CMP_ROW_RANGE_END    = ROW_WIDTH + CMP_ROW_RANGE_START - 1;

  localparam CMP_BANK_RANGE_START = CMP_ROW_RANGE_END + 1;

  localparam CMP_BANK_RANGE_END   = BANK_WIDTH + CMP_BANK_RANGE_START - 1;

  localparam CMP_CS_RANGE_START   = CMP_BANK_RANGE_END + 1;

  localparam CMP_CS_RANGE_END     = CS_BITS + CMP_CS_RANGE_START-1;

  localparam BURST_LEN_DIV2      = BURST_LEN / 2;

  localparam OPEN_BANK_NUM       = 4;

  localparam CS_BITS_FIX         = (CS_BITS == 0) ? 1 : CS_BITS;

  // calculation counters based on clock cycle and memory parameters

  // TRAS: ACTIVE->PRECHARGE interval - 2

  localparam integer TRAS_CYC = (TRAS + CLK_PERIOD)/CLK_PERIOD;

  // TRCD: ACTIVE->READ/WRITE interval - 3 (for DDR2 factor in ADD_LAT)

  localparam integer TRRD_CYC = (TRRD + CLK_PERIOD)/CLK_PERIOD;

  localparam integer TRCD_CYC = (((TRCD + CLK_PERIOD)/CLK_PERIOD) >

                                 ADDITIVE_LAT )?

             ((TRCD+CLK_PERIOD)/ CLK_PERIOD) - ADDITIVE_LAT : 0;

  // TRFC: REFRESH->REFRESH, REFRESH->ACTIVE interval - 2

  localparam integer TRFC_CYC = (TRFC + CLK_PERIOD)/CLK_PERIOD;

  // TRP: PRECHARGE->COMMAND interval - 2

   // for precharge all add 1 extra clock cycle

  localparam integer TRP_CYC =  ((TRP + CLK_PERIOD)/CLK_PERIOD) +1;

  // TRTP: READ->PRECHARGE interval - 2 (Al + BL/2 + (max (TRTP, 2tck))-2

  localparam integer TRTP_TMP_MIN = (((TRTP + CLK_PERIOD)/CLK_PERIOD) >= 2)?

                                     ((TRTP + CLK_PERIOD)/CLK_PERIOD) : 2;

  localparam integer TRTP_CYC = TRTP_TMP_MIN + ADDITIVE_LAT

                                + BURST_LEN_DIV2 - 2;

  // TWR: WRITE->PRECHARGE interval - 2

  localparam integer WR_LAT = (DDR_TYPE > 0) ? CAS_LAT + ADDITIVE_LAT - 1 : 1;

  localparam integer TWR_CYC = ((TWR + CLK_PERIOD)/CLK_PERIOD) +

             WR_LAT + BURST_LEN_DIV2 ;

  // TWTR: WRITE->READ interval - 3 (for DDR1, TWTR = 2 clks)

  // DDR2 = CL-1 + BL/2 +TWTR

  localparam integer TWTR_TMP_MIN = (TWTR + CLK_PERIOD)/CLK_PERIOD;

  localparam integer TWTR_CYC = (DDR_TYPE > 0) ? (TWTR_TMP_MIN + (CAS_LAT -1)

                                 + BURST_LEN_DIV2 ): 2;

  //  TRTW: READ->WRITE interval - 3

  //  DDR1: CL + (BL/2)

  //  DDR2: (BL/2) + 2. Two more clocks are added to

  //  the DDR2 counter to account for the delay in

  //  arrival of the DQS during reads (pcb trace + buffer

  //  delays + memory parameters).

  localparam TRTW_CYC = (DDR_TYPE > 0) ? BURST_LEN_DIV2 + 4 :

             (CAS_LAT == 25) ? 2 + BURST_LEN_DIV2 : CAS_LAT + BURST_LEN_DIV2;

  localparam integer CAS_LAT_RD = (CAS_LAT == 25) ? 2 : CAS_LAT;

  // Make sure all values >= 0 (some may be = 0)

  localparam TRAS_COUNT = (TRAS_CYC > 0) ? TRAS_CYC : 0;

  localparam TRCD_COUNT = (TRCD_CYC > 0) ? TRCD_CYC : 0;

  localparam TRRD_COUNT = (TRRD_CYC > 0) ? TRRD_CYC : 0;

  localparam TRFC_COUNT = (TRFC_CYC > 0) ? TRFC_CYC : 0;

  localparam TRP_COUNT  = (TRP_CYC > 0)  ? TRP_CYC  : 0;

  localparam TRTP_COUNT = (TRTP_CYC > 0) ? TRTP_CYC : 0;

  localparam TWR_COUNT  = (TWR_CYC > 0)  ? TWR_CYC  : 0;

  localparam TWTR_COUNT = (TWTR_CYC > 0) ? TWTR_CYC : 0;

  localparam TRTW_COUNT = (TRTW_CYC > 0) ? TRTW_CYC : 0;

  // Auto refresh interval

  localparam TREFI_COUNT = ((TREFI_NS * 1000)/CLK_PERIOD) - 1;

  // memory controller states

  localparam   CTRL_IDLE                =     5'h00;

  localparam   CTRL_PRECHARGE           =     5'h01;

  localparam   CTRL_PRECHARGE_WAIT      =     5'h02;

  localparam   CTRL_AUTO_REFRESH        =     5'h03;

  localparam   CTRL_AUTO_REFRESH_WAIT   =     5'h04;

  localparam   CTRL_ACTIVE              =     5'h05;

  localparam   CTRL_ACTIVE_WAIT         =     5'h06;

  localparam   CTRL_BURST_READ          =     5'h07;

  localparam   CTRL_READ_WAIT           =     5'h08;

  localparam   CTRL_BURST_WRITE         =     5'h09;

  localparam   CTRL_WRITE_WAIT          =     5'h0A;

  localparam   CTRL_PRECHARGE_WAIT1     =     5'h0B;

  reg [CMP_WIDTH-1:0]                      act_addr_r;

  wire [30:0]                              af_addr_r;

  reg [30:0]                               af_addr_r1;

  reg [30:0]                               af_addr_r2;

  reg [30:0]                               af_addr_r3;

  wire [2:0]                               af_cmd_r;

  reg [2:0]                                af_cmd_r1;

  reg [2:0]                                af_cmd_r2;

  reg                                      af_valid_r;

  reg                                      af_valid_r1;

  reg                                      af_valid_r2;

  reg [CS_BITS_FIX :0]                     auto_cnt_r;

  reg                                      auto_ref_r;

  reg [(OPEN_BANK_NUM*CMP_WIDTH)-1:0]      bank_cmp_addr_r;

  reg [OPEN_BANK_NUM-1:0]                  bank_hit;

  reg [OPEN_BANK_NUM-1:0]                  bank_hit_r;

  reg [OPEN_BANK_NUM-1:0]                  bank_hit_r1;

  reg [OPEN_BANK_NUM-1:0]                  bank_valid_r;

  reg                                      bank_conflict_r;

  reg                                      conflict_resolved_r;

  reg                                      ctrl_af_rden_r;

  reg                                      conflict_detect_r;

  wire                                     conflict_detect;

  reg                                      cs_change_r;

  reg                                      cs_change_sticky_r;

  reg [ROW_WIDTH-1:0]                      ddr_addr_r;

  wire [ROW_WIDTH-1:0]                     ddr_addr_col;

  wire [ROW_WIDTH-1:0]                     ddr_addr_row;

  reg [BANK_WIDTH-1:0]                     ddr_ba_r;

  reg                                      ddr_cas_n_r;

  reg [CS_NUM-1:0]                         ddr_cs_n_r;

  reg                                      ddr_ras_n_r;

  reg                                      ddr_we_n_r;

  reg [4:0]                                next_state;

  reg                                      no_precharge_wait_r;

  reg                                      no_precharge_r;

  reg                                      no_precharge_r1;

  reg                                      phy_init_done_r;

  reg [4:0]                                precharge_ok_cnt_r;

  reg                                      precharge_ok_r;

  reg [4:0]                                ras_cnt_r;

  reg [3:0]                                rcd_cnt_r;

  reg                                      rcd_cnt_ok_r;

  reg [2:0]                                rdburst_cnt_r;

  reg                                      rdburst_ok_r;

  reg                                      rdburst_rden_ok_r;

  reg                                      rd_af_flag_r;

  wire                                     rd_flag;

  reg                                      rd_flag_r;

  reg [4:0]                                rd_to_wr_cnt_r;

  reg                                      rd_to_wr_ok_r;

  reg                                      ref_flag_r;

  reg [11:0]                               refi_cnt_r;

  reg                                      refi_cnt_ok_r;

  reg                                      rst_r

                                           /* synthesis syn_preserve = 1 */;

  reg                                      rst_r1

                                           /* synthesis syn_maxfan = 10 */;

  reg [7:0]                                rfc_cnt_r;

  reg                                      rfc_ok_r;

  reg [3:0]                                row_miss;

  reg [3:0]                                row_conflict_r;

  reg [3:0]                                rp_cnt_r;

  reg                                      rp_cnt_ok_r;

  reg [CMP_WIDTH-1:0]                      sb_open_add_r;

  reg [4:0]                                state_r;

  reg [4:0]                                state_r1;

  wire                                     sm_rden;

  reg                                      sm_rden_r;

  reg [2:0]                                trrd_cnt_r;

  reg                                      trrd_cnt_ok_r;

  reg [2:0]                                two_t_enable_r;

  reg [CS_NUM-1:0]                         two_t_enable_r1;

  reg [2:0]                                wrburst_cnt_r;

  reg                                      wrburst_ok_r;

  reg                                      wrburst_wren_ok_r;

  wire                                     wr_flag;

  reg                                      wr_flag_r;

  reg [4:0]                                wr_to_rd_cnt_r;

  reg                                      wr_to_rd_ok_r;

  // XST attributes for local reset "tree"

  // synthesis attribute shreg_extract of rst_r is "no";

  // synthesis attribute shreg_extract of rst_r1 is "no";

  // synthesis attribute equivalent_register_removal of rst_r is "no"

  //***************************************************************************

  // sm_rden is used to assert read enable to the address FIFO

  assign sm_rden = ((state_r == CTRL_BURST_WRITE) ||

                    (state_r == CTRL_BURST_READ)) ;

   // Assert this when approaching refresh and not in an access

   reg                                     ref_approaching;

   always @(posedge clk)

     ref_approaching <= (refi_cnt_r >= (TREFI_COUNT -80)) & ~af_valid_r2;

   reg                                     ref_just_happened;

   always @(posedge clk)

     ref_just_happened <= (refi_cnt_r <  12'h30) & ~af_valid_r2;

  // assert read flag to the adress FIFO

  assign ctrl_af_rden = (sm_rden || rd_af_flag_r) & !(ref_approaching | ref_just_happened);

  // local reset "tree" for controller logic only. Create this to ease timing

  // on reset path. Prohibit equivalent register removal on RST_R to prevent

  // "sharing" with other local reset trees (caution: make sure global fanout

  // limit is set to large enough value, otherwise SLICES may be used for

  // fanout control on RST_R.

  always @(posedge clk) begin

    rst_r  <= rst;

    rst_r1 <= rst_r;

  end

  //*****************************************************************

  // interpret commands from Command/Address FIFO

  //*****************************************************************

  assign wr_flag = (af_valid_r2) ? ((af_cmd_r2 == 3'b000) ? 1'b1 : 1'b0): 1'b0;

  assign rd_flag = (af_valid_r2) ? ((af_cmd_r2 == 3'b001) ? 1'b1 : 1'b0): 1'b0;

  always @(posedge clk) begin

    rd_flag_r <= rd_flag;

    wr_flag_r <= wr_flag;

  end

  //////////////////////////////////////////////////

  // The data from the address FIFO is fetched and

  // stored in two register stages. The data will be

  // pulled out of the second register stage whenever

  // the state machine can handle new data from the

  // address FIFO.

  // This flag is asserted when there is no

  // cmd & address in the pipe. When there is

  // valid cmd & addr from the address FIFO the

  // af_valid signals will be asserted. This flag will

  // be set the cycle af_valid_r is de-asserted.

  always @(posedge clk) begin

    // for simulation purposes - to force CTRL_AF_RDEN low during reset

    if (rst_r1)

      rd_af_flag_r <= 1'd0;

    else if (rd_af_flag_r) // jb - probably should find a way to stop this toggling all the time

      rd_af_flag_r <= 0;     // jb

    else if((ctrl_af_rden_r) ||

            (/*rd_af_flag_r &&*/ (af_valid_r || af_valid_r1))) // Fixed bug where third addresses would get lost (pulled off fifo and then  clobbered by other value later, thus ignored/skipped) - just make sure we don't get too excited and pull too many off at once  - jb

         rd_af_flag_r <= 1'd0;

    else if (~af_valid_r1 || ~af_valid_r)

         rd_af_flag_r <= 1'd1;

  end // always @ (posedge clk)

  // First register stage for the cmd & add from the FIFO.

  // The af_valid_r signal gives the status of the data

  // in this stage. The af_valid_r will be asserted when there

  // is valid data. This register stage will be updated

  // 1. read to the FIFO and the FIFO not empty

  // 2. After write and read states

  // 3. The valid signal is not asserted in the last stage.

  always @(posedge clk) begin

    if (rst_r1)begin

      af_valid_r <= 1'd0;

    end else begin

      if (ctrl_af_rden_r || sm_rden_r || ~af_valid_r1

          || ~af_valid_r2)begin

        af_valid_r <= ctrl_af_rden_r;

      end

    end

  end

  // The output register in the FIFO is used. The addr

  // and command are already registered in the FIFO.

  assign af_addr_r = af_addr;

  assign af_cmd_r = af_cmd;

  // Second register stage for the cmd & add from the FIFO.

  // The af_valid_r1 signal gives the status of the data

  // in this stage. The af_valid_r will be asserted when there

  // is valid data. This register stage will be updated

  // 1. read to the FIFO and the FIFO not empty and there

  // is no valid data on this stage

  // 2. After write and read states

  // 3. The valid signal is not asserted in the last stage.

  always@(posedge clk) begin

    if (rst_r1)begin

      af_valid_r1 <= 1'd0;

      af_addr_r1 <= {31{1'bx}};

      af_cmd_r1 <= {3{1'bx}};

    end else if (~af_valid_r1 || sm_rden_r ||

                  ~af_valid_r2) begin

      af_valid_r1 <= af_valid_r;

      af_addr_r1 <= af_addr_r;

      af_cmd_r1 <= af_cmd_r;

    end

  end

  // The state machine uses the address and command in this

  // register stage. The data is fetched from the second

  // register stage whenever the state machine can accept new

  // addr. The conflict flags are also generated based on the

  // second register stage and updated when the new address

  // is loaded for the state machine.

  always@(posedge clk) begin

    if (rst_r1)begin

      af_valid_r2 <= 1'd0;

      af_addr_r2 <= {31{1'bx}};

      af_cmd_r2 <= {3{1'bx}};

      bank_hit_r <= {OPEN_BANK_NUM{1'bx}};

      bank_conflict_r <= 1'bx;

      row_conflict_r <= 4'bx;

    end else if(sm_rden || ~af_valid_r2)begin

      af_valid_r2 <= af_valid_r1;

      af_addr_r2 <= af_addr_r1;

      af_cmd_r2 <= af_cmd_r1;

      if(MULTI_BANK_EN)begin

        bank_hit_r <= bank_hit;

        row_conflict_r <= row_miss;

        bank_conflict_r <= (~(|bank_hit));

      end else begin

        bank_hit_r <= {OPEN_BANK_NUM{1'b0}};

        bank_conflict_r <= 1'd0;

        row_conflict_r[0] <= (af_addr_r1[CS_RANGE_END:ROW_RANGE_START]

                              != sb_open_add_r[CMP_WIDTH-1:0]);

      end

    end

  end // always@ (posedge clk)

  //detecting cs change for multi chip select case

  generate

    if(CS_NUM > 1) begin: gen_cs_change

       always @(posedge clk) begin

          if(sm_rden || ~af_valid_r2)begin

            cs_change_r <= af_addr_r1[CS_RANGE_END:CS_RANGE_START] !=

                       af_addr_r2[CS_RANGE_END:CS_RANGE_START] ;

            cs_change_sticky_r <=

             af_addr_r1[CS_RANGE_END:CS_RANGE_START] !=

             af_addr_r2[CS_RANGE_END:CS_RANGE_START] ;

          end else

            cs_change_r <= 1'd0;

       end

    end // block: gen_cs_change

    else begin: gen_cs_0

       always @(posedge clk) begin

          cs_change_r <= 1'd0;

          cs_change_sticky_r <= 1'd0;

       end

    end

 endgenerate

  assign conflict_detect = (MULTI_BANK_EN) ?

                           ((|(row_conflict_r[3:0] & bank_hit_r[3:0]))

                            | bank_conflict_r) & af_valid_r2 :

                           row_conflict_r[0] & af_valid_r2;

  always @(posedge clk) begin

    conflict_detect_r <= conflict_detect;

    sm_rden_r <= sm_rden;

    af_addr_r3 <= af_addr_r2;

    ctrl_af_rden_r <= ctrl_af_rden & ~af_empty;

  end

  // conflict resolved signal. When this signal is asserted

  // the conflict is resolved. The address to be compared

  // for the conflict_resolved_r will be stored in act_add_r

  // when the bank is opened.

  always @(posedge clk) begin

   conflict_resolved_r <= (act_addr_r ==

                           af_addr_r2[CS_RANGE_END:ROW_RANGE_START]);

    if((state_r == CTRL_ACTIVE))

      act_addr_r <= af_addr_r2[CS_RANGE_END:ROW_RANGE_START];

  end

  //***************************************************************************

  // Bank management logic

  // Semi-hardcoded for now for 4 banks

  // will keep multiple banks open if MULTI_BANK_EN is true.

  //***************************************************************************

  genvar bank_i;

  generate // if multiple bank option chosen

    if(MULTI_BANK_EN) begin: gen_multi_bank_open

      for (bank_i = 0; bank_i < OPEN_BANK_NUM;

           bank_i = bank_i + 1) begin: gen_bank_hit1

        // asserted if bank address match + open bank entry is valid

        always @(*) begin

          bank_hit[bank_i]

            = ((bank_cmp_addr_r[(CMP_WIDTH*(bank_i+1))-1:

                                (CMP_WIDTH*bank_i)+ROW_WIDTH] ==

                af_addr_r1[CS_RANGE_END:BANK_RANGE_START]) &&

               bank_valid_r[bank_i]);

          // asserted if row address match (no check for bank entry valid, rely

          // on this term to be used in conjunction with BANK_HIT[])

          row_miss[bank_i]

            = (bank_cmp_addr_r[(CMP_WIDTH*bank_i)+ROW_WIDTH-1:

                               (CMP_WIDTH*bank_i)] !=

               af_addr_r1[ROW_RANGE_END:ROW_RANGE_START]);

        end

      end

      always @(posedge clk) begin

        no_precharge_wait_r  <= bank_valid_r[3] & bank_conflict_r;

        bank_hit_r1 <= bank_hit_r;

      end

      always@(*)

        no_precharge_r = ~bank_valid_r[3] & bank_conflict_r;

      always@(posedge clk)

        no_precharge_r1 <= no_precharge_r;

      always @(posedge clk) begin

        // Clear all bank valid bits during AR (i.e. since all banks get

        // precharged during auto-refresh)

        if ((state_r1 == CTRL_AUTO_REFRESH)) begin

          bank_valid_r    <= {OPEN_BANK_NUM{1'b0}};

          bank_cmp_addr_r <= {(OPEN_BANK_NUM*CMP_WIDTH-1){1'b0}};

        end else begin

          if (state_r1 == CTRL_ACTIVE) begin

            // 00 is always going to have the latest bank and row.

            bank_cmp_addr_r[CMP_WIDTH-1:0]

              <= af_addr_r3[CS_RANGE_END:ROW_RANGE_START];

            // This indicates the bank was activated

            bank_valid_r[0] <= 1'b1;

            case ({bank_hit_r1[2:0]})

              3'b001: begin

                bank_cmp_addr_r[CMP_WIDTH-1:0]

                  <= af_addr_r3[CS_RANGE_END:ROW_RANGE_START];

                // This indicates the bank was activated

                bank_valid_r[0] <= 1'b1;

              end

              3'b010: begin //(b0->b1)

                bank_cmp_addr_r[(2*CMP_WIDTH)-1:CMP_WIDTH]

                  <= bank_cmp_addr_r[CMP_WIDTH-1:0];

                bank_valid_r[1] <= bank_valid_r[0];

              end

              3'b100:begin //(b0->b1, b1->b2)

                bank_cmp_addr_r[(2*CMP_WIDTH)-1:CMP_WIDTH]

                  <= bank_cmp_addr_r[CMP_WIDTH-1:0];

                bank_cmp_addr_r[(3*CMP_WIDTH)-1:2*CMP_WIDTH]

                  <= bank_cmp_addr_r[(2*CMP_WIDTH)-1:CMP_WIDTH];

                bank_valid_r[1] <= bank_valid_r[0];

                bank_valid_r[2] <= bank_valid_r[1];

              end

              default: begin //(b0->b1, b1->b2, b2->b3)

                bank_cmp_addr_r[(2*CMP_WIDTH)-1:CMP_WIDTH]

                  <= bank_cmp_addr_r[CMP_WIDTH-1:0];

                bank_cmp_addr_r[(3*CMP_WIDTH)-1:2*CMP_WIDTH]

                  <= bank_cmp_addr_r[(2*CMP_WIDTH)-1:CMP_WIDTH];

                bank_cmp_addr_r[(4*CMP_WIDTH)-1:3*CMP_WIDTH]

                  <= bank_cmp_addr_r[(3*CMP_WIDTH)-1:2*CMP_WIDTH];

                bank_valid_r[1] <= bank_valid_r[0];

                bank_valid_r[2] <= bank_valid_r[1];

                bank_valid_r[3] <= bank_valid_r[2];

              end

            endcase

          end

        end

      end

    end else begin: gen_single_bank_open // single bank option

      always @(posedge clk) begin

        no_precharge_r       <= 1'd0;

        no_precharge_r1      <= 1'd0;

        no_precharge_wait_r  <= 1'd0;

        if (rst_r1)

          sb_open_add_r <= {CMP_WIDTH{1'b0}};

        else if (state_r == CTRL_ACTIVE)

          sb_open_add_r <= af_addr_r2[CS_RANGE_END:ROW_RANGE_START];

      end

    end

  endgenerate

  //***************************************************************************

  // Timing counters

  //***************************************************************************

  //*****************************************************************

  // Write and read enable generation for PHY

  //*****************************************************************

  // write burst count. Counts from (BL/2 to 1).

  // Also logic for controller write enable.

  always @(posedge clk) begin

    if (state_r == CTRL_BURST_WRITE) begin

      wrburst_cnt_r <= BURST_LEN_DIV2;

    end else if (wrburst_cnt_r >= 3'd1)

      wrburst_cnt_r <= wrburst_cnt_r - 1;

  end // always @ (posedge clk)

  always @(posedge clk) begin

    if (rst_r1) begin

      ctrl_wren   <= 1'b0;

    end else if (state_r == CTRL_BURST_WRITE) begin

      ctrl_wren   <= 1'b1;

    end else if (wrburst_wren_ok_r)

      ctrl_wren   <= 1'b0;

  end

  always @(posedge clk) begin

    if ((state_r == CTRL_BURST_WRITE)

        && (BURST_LEN_DIV2 > 2))

      wrburst_ok_r <= 1'd0;

    else if ((wrburst_cnt_r <= 3'd3) ||

             (BURST_LEN_DIV2 <= 2))

      wrburst_ok_r <= 1'b1;

  end

  // flag to check when wrburst count has reached

  // a value of 1. This flag is used in the ctrl_wren

  // logic

  always @(posedge clk) begin

     if(wrburst_cnt_r == 3'd2)

       wrburst_wren_ok_r <=1'b1;

     else

       wrburst_wren_ok_r <= 1'b0;

  end

  // read burst count. Counts from (BL/2 to 1)