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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [rtl/] [verilog/] [xilinx_ddr2/] [ddr2_usr_addr_fifo.v] - Blame information for rev 412

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//*****************************************************************************
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// DISCLAIMER OF LIABILITY
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//
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// This file contains proprietary and confidential information of
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// Xilinx, Inc. ("Xilinx"), that is distributed under a license
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// from Xilinx, and may be used, copied and/or disclosed only
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// pursuant to the terms of a valid license agreement with Xilinx.
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//
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// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
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// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
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// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
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// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
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// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
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// does not warrant that functions included in the Materials will
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// meet the requirements of Licensee, or that the operation of the
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// Materials will be uninterrupted or error-free, or that defects
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// in the Materials will be corrected. Furthermore, Xilinx does
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// not warrant or make any representations regarding use, or the
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// results of the use, of the Materials in terms of correctness,
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// accuracy, reliability or otherwise.
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//
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// Xilinx products are not designed or intended to be fail-safe,
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// or for use in any application requiring fail-safe performance,
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// such as life-support or safety devices or systems, Class III
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// medical devices, nuclear facilities, applications related to
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// the deployment of airbags, or any other applications that could
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// lead to death, personal injury or severe property or
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// environmental damage (individually and collectively, "critical
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// applications"). Customer assumes the sole risk and liability
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// of any use of Xilinx products in critical applications,
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// subject only to applicable laws and regulations governing
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// limitations on product liability.
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//
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// Copyright 2006, 2007 Xilinx, Inc.
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// All rights reserved.
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//
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// This disclaimer and copyright notice must be retained as part
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// of this file at all times.
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//*****************************************************************************
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//   ____  ____
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//  /   /\/   /
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// /___/  \  /    Vendor: Xilinx
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// \   \   \/     Version: 3.0
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//  \   \         Application: MIG
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//  /   /         Filename: ddr2_usr_addr_fifo.v
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// /___/   /\     Date Last Modified: $Date: 2008/12/23 14:26:01 $
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// \   \  /  \    Date Created: Mon Aug 28 2006
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//  \___\/\___\
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//
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//Device: Virtex-5
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//Design Name: DDR2
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//Purpose:
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//   This module instantiates the block RAM based FIFO to store the user
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//   address and the command information. Also calculates potential bank/row
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//   conflicts by comparing the new address with last address issued.
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//Reference:
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//Revision History:
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//*****************************************************************************
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`timescale 1ns/1ps
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module ddr2_usr_addr_fifo #
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  (
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   // Following parameters are for 72-bit RDIMM design (for ML561 Reference 
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   // board design). Actual values may be different. Actual parameters values 
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   // are passed from design top module ddr2_mig module. Please refer to
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   // the ddr2_mig module for actual values.
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   parameter BANK_WIDTH    = 2,
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   parameter COL_WIDTH     = 10,
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   parameter CS_BITS       = 0,
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   parameter ROW_WIDTH     = 14
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   )
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  (
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   input          clk0,
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    input         rst0,
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    input         usr_clk,
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   input [2:0]    app_af_cmd,
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   input [30:0]   app_af_addr,
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   input          app_af_wren,
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   input          ctrl_af_rden,
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   output [2:0]   af_cmd,
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   output [30:0]  af_addr,
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   output         af_empty,
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   output         app_af_afull
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   );
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  wire [35:0]     fifo_data_out;
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   reg            rst_r;
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  always @(posedge clk0)
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     rst_r <= rst0;
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  //***************************************************************************
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  assign af_cmd      = fifo_data_out[33:31];
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  assign af_addr     = fifo_data_out[30:0];
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  //***************************************************************************
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  FIFO36 #
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    (
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     .ALMOST_EMPTY_OFFSET     (13'h0007),
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     .ALMOST_FULL_OFFSET      (13'h000F),
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     .DATA_WIDTH              (36),
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     .DO_REG                  (1),
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     .EN_SYN                  ("FALSE"), // changed to FALSE - jb
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     .FIRST_WORD_FALL_THROUGH ("FALSE")
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     )
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    u_af
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      (
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       .ALMOSTEMPTY (),
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       .ALMOSTFULL  (app_af_afull),
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       .DO          (fifo_data_out[31:0]),
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       .DOP         (fifo_data_out[35:32]),
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       .EMPTY       (af_empty),
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       .FULL        (),
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       .RDCOUNT     (),
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       .RDERR       (),
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       .WRCOUNT     (),
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       .WRERR       (),
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       .DI          ({app_af_cmd[0],app_af_addr}),
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       .DIP         ({2'b00,app_af_cmd[2:1]}),
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       .RDCLK       (clk0),
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       .RDEN        (ctrl_af_rden),
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       .RST         (rst_r),
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       //.WRCLK       (clk0),
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       .WRCLK       (usr_clk),
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       .WREN        (app_af_wren)
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       );
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endmodule

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