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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_alu.v] - Blame information for rev 801

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1 350 julius
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  OR1200's ALU                                                ////
4
////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
6
////  http://www.opencores.org/project,or1k                       ////
7
////                                                              ////
8
////  Description                                                 ////
9
////  ALU                                                         ////
10
////                                                              ////
11
////  To Do:                                                      ////
12
////   - make it smaller and faster                               ////
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////                                                              ////
14
////  Author(s):                                                  ////
15
////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
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//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
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////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44
// $Log: or1200_alu.v,v $
45
// Revision 2.0  2010/06/30 11:00:00  ORSoC
46
// Minor update: 
47
// Defines added, flags are corrected. 
48
 
49
// synopsys translate_off
50
`include "timescale.v"
51
// synopsys translate_on
52
`include "or1200_defines.v"
53
 
54
module or1200_alu(
55
        a, b, mult_mac_result, macrc_op,
56 499 julius
        alu_op, alu_op2, comp_op,
57 350 julius
        cust5_op, cust5_limm,
58
        result, flagforw, flag_we,
59 502 julius
        ovforw, ov_we,
60 350 julius
        cyforw, cy_we, carry, flag
61
);
62
 
63
parameter width = `OR1200_OPERAND_WIDTH;
64
 
65
//
66
// I/O
67
//
68
input   [width-1:0]              a;
69
input   [width-1:0]              b;
70
input   [width-1:0]              mult_mac_result;
71
input                           macrc_op;
72
input   [`OR1200_ALUOP_WIDTH-1:0]        alu_op;
73 403 julius
input   [`OR1200_ALUOP2_WIDTH-1:0]       alu_op2;
74 350 julius
input   [`OR1200_COMPOP_WIDTH-1:0]       comp_op;
75
input   [4:0]                    cust5_op;
76
input   [5:0]                    cust5_limm;
77
output  [width-1:0]              result;
78
output                          flagforw;
79
output                          flag_we;
80
output                          cyforw;
81
output                          cy_we;
82 502 julius
output                          ovforw;
83
output                          ov_we;
84 350 julius
input                           carry;
85
input         flag;
86
 
87
//
88
// Internal wires and regs
89
//
90
reg     [width-1:0]              result;
91
reg     [width-1:0]              shifted_rotated;
92 499 julius
reg     [width-1:0]              extended;
93 788 julius
`ifdef OR1200_IMPL_ALU_CUST5
94 350 julius
reg     [width-1:0]              result_cust5;
95 788 julius
`endif
96 350 julius
reg                             flagforw;
97
reg                             flagcomp;
98
reg                             flag_we;
99 502 julius
reg                             cyforw;
100 350 julius
reg                             cy_we;
101 502 julius
reg                             ovforw;
102
reg                             ov_we;
103 350 julius
wire    [width-1:0]              comp_a;
104
wire    [width-1:0]              comp_b;
105
wire                            a_eq_b;
106
wire                            a_lt_b;
107
wire    [width-1:0]              result_sum;
108
wire    [width-1:0]              result_and;
109
wire                            cy_sum;
110
`ifdef OR1200_IMPL_SUB
111
wire                            cy_sub;
112
`endif
113 502 julius
wire                            ov_sum;
114
wire    [width-1:0]              carry_in;
115 350 julius
 
116 502 julius
wire    [width-1:0]              b_mux;
117
 
118
 
119
 
120 350 julius
//
121
// Combinatorial logic
122
//
123 504 julius
 
124 350 julius
assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};
125
assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};
126
`ifdef OR1200_IMPL_ALU_COMP1
127
assign a_eq_b = (comp_a == comp_b);
128
assign a_lt_b = (comp_a < comp_b);
129
`endif
130 504 julius
`ifdef OR1200_IMPL_ALU_COMP3
131
assign a_eq_b = !(|result_sum);
132 619 julius
// signed compare when comp_op[3] is set
133 504 julius
assign a_lt_b = comp_op[3] ? ((a[width-1] & !b[width-1]) |
134
                              (!a[width-1] & !b[width-1] & result_sum[width-1])|
135
                              (a[width-1] & b[width-1] & result_sum[width-1])):
136 672 julius
                (a < b);
137
 
138 504 julius
`endif
139
 
140 350 julius
`ifdef OR1200_IMPL_SUB
141 504 julius
 `ifdef OR1200_IMPL_ALU_COMP3
142
assign cy_sub = a_lt_b;
143
 `else
144 502 julius
assign cy_sub = (comp_a < comp_b);
145 504 julius
 `endif
146 350 julius
`endif
147 504 julius
 
148 502 julius
`ifdef OR1200_IMPL_ADDC
149
assign carry_in = (alu_op==`OR1200_ALUOP_ADDC) ?
150
                  {{width-1{1'b0}},carry} : {width{1'b0}};
151
`else
152
assign carry_in = {width-1{1'b0}};
153 350 julius
`endif
154 504 julius
 
155
`ifdef OR1200_IMPL_ALU_COMP3
156 502 julius
`ifdef OR1200_IMPL_SUB
157 504 julius
assign b_mux = ((alu_op==`OR1200_ALUOP_SUB) | (alu_op==`OR1200_ALUOP_COMP)) ?
158
                (~b)+1 : b;
159
`else
160
assign b_mux = (alu_op==`OR1200_ALUOP_COMP) ? (~b)+1 : b;
161
`endif
162
`else // ! `ifdef OR1200_IMPL_ALU_COMP3
163
`ifdef OR1200_IMPL_SUB
164 502 julius
assign b_mux = (alu_op==`OR1200_ALUOP_SUB) ? (~b)+1 : b;
165
`else
166
assign b_mux = b;
167 504 julius
`endif
168
`endif
169 502 julius
assign {cy_sum, result_sum} = (a + b_mux) + carry_in;
170
// Numbers either both +ve and bit 31 of result set
171
assign ov_sum = ((!a[width-1] & !b_mux[width-1]) & result_sum[width-1]) |
172
// or both -ve and bit 31 of result clear
173
                ((a[width-1] & b_mux[width-1]) & !result_sum[width-1]);
174 350 julius
assign result_and = a & b;
175
 
176
//
177
// Simulation check for bad ALU behavior
178
//
179
`ifdef OR1200_WARNINGS
180
// synopsys translate_off
181
always @(result) begin
182
        if (result === 32'bx)
183
                $display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);
184
end
185
// synopsys translate_on
186
`endif
187
 
188
//
189
// Central part of the ALU
190
//
191 403 julius
always @(alu_op or alu_op2 or a or b or result_sum or result_and or macrc_op
192 788 julius
         or shifted_rotated or mult_mac_result or flag or carry
193 499 julius
`ifdef OR1200_IMPL_ALU_EXT
194
         or extended
195
`endif
196 788 julius
`ifdef OR1200_IMPL_ALU_CUST5
197
         or result_cust5
198
`endif
199 350 julius
) begin
200
`ifdef OR1200_CASE_DEFAULT
201 363 julius
        casez (alu_op)          // synopsys parallel_case
202 350 julius
`else
203 363 julius
        casez (alu_op)          // synopsys full_case parallel_case
204 350 julius
`endif
205 403 julius
`ifdef OR1200_IMPL_ALU_FFL1
206
                `OR1200_ALUOP_FFL1: begin
207
`ifdef OR1200_CASE_DEFAULT
208
                   casez (alu_op2) // synopsys parallel_case
209
`else
210
                   casez (alu_op2) // synopsys full_case parallel_case
211
`endif
212
                     0: begin // FF1
213 350 julius
                        result = a[0] ? 1 : a[1] ? 2 : a[2] ? 3 : a[3] ? 4 : a[4] ? 5 : a[5] ? 6 : a[6] ? 7 : a[7] ? 8 : a[8] ? 9 : a[9] ? 10 : a[10] ? 11 : a[11] ? 12 : a[12] ? 13 : a[13] ? 14 : a[14] ? 15 : a[15] ? 16 : a[16] ? 17 : a[17] ? 18 : a[18] ? 19 : a[19] ? 20 : a[20] ? 21 : a[21] ? 22 : a[22] ? 23 : a[23] ? 24 : a[24] ? 25 : a[25] ? 26 : a[26] ? 27 : a[27] ? 28 : a[28] ? 29 : a[29] ? 30 : a[30] ? 31 : a[31] ? 32 : 0;
214 403 julius
                     end
215
                     default: begin // FL1
216
                        result = a[31] ? 32 : a[30] ? 31 : a[29] ? 30 : a[28] ? 29 : a[27] ? 28 : a[26] ? 27 : a[25] ? 26 : a[24] ? 25 : a[23] ? 24 : a[22] ? 23 : a[21] ? 22 : a[20] ? 21 : a[19] ? 20 : a[18] ? 19 : a[17] ? 18 : a[16] ? 17 : a[15] ? 16 : a[14] ? 15 : a[13] ? 14 : a[12] ? 13 : a[11] ? 12 : a[10] ? 11 : a[9] ? 10 : a[8] ? 9 : a[7] ? 8 : a[6] ? 7 : a[5] ? 6 : a[4] ? 5 : a[3] ? 4 : a[2] ? 3 : a[1] ? 2 : a[0] ? 1 : 0 ;
217
                     end
218
                   endcase // casez (alu_op2)
219
                end // case: `OR1200_ALUOP_FFL1
220 499 julius
`endif //  `ifdef OR1200_IMPL_ALU_FFL1
221
`ifdef OR1200_IMPL_ALU_CUST5
222
 
223 350 julius
                `OR1200_ALUOP_CUST5 : begin
224
                                result = result_cust5;
225
                end
226 499 julius
`endif
227 350 julius
                `OR1200_ALUOP_SHROT : begin
228
                                result = shifted_rotated;
229
                end
230
`ifdef OR1200_IMPL_ADDC
231 502 julius
                `OR1200_ALUOP_ADDC,
232 350 julius
`endif
233
`ifdef OR1200_IMPL_SUB
234 502 julius
                `OR1200_ALUOP_SUB,
235
`endif
236
                `OR1200_ALUOP_ADD : begin
237
                                result = result_sum;
238 350 julius
                end
239
                `OR1200_ALUOP_XOR : begin
240
                                result = a ^ b;
241
                end
242
                `OR1200_ALUOP_OR  : begin
243
                                result = a | b;
244
                end
245 499 julius
`ifdef OR1200_IMPL_ALU_EXT
246
                `OR1200_ALUOP_EXTHB  : begin
247
                                result = extended;
248
                end
249
                `OR1200_ALUOP_EXTW  : begin
250 801 julius
                                result = a;
251 499 julius
                end
252
`endif
253 350 julius
                `OR1200_ALUOP_MOVHI : begin
254
                                if (macrc_op) begin
255
                                        result = mult_mac_result;
256
                                end
257
                                else begin
258
                                        result = b << 16;
259
                                end
260
                end
261
`ifdef OR1200_MULT_IMPLEMENTED
262
`ifdef OR1200_DIV_IMPLEMENTED
263
                `OR1200_ALUOP_DIV,
264
                `OR1200_ALUOP_DIVU,
265
`endif
266 435 julius
                `OR1200_ALUOP_MUL,
267
                `OR1200_ALUOP_MULU : begin
268 350 julius
                                result = mult_mac_result;
269
                end
270
`endif
271
                `OR1200_ALUOP_CMOV: begin
272
                        result = flag ? a : b;
273
                end
274
 
275
`ifdef OR1200_CASE_DEFAULT
276
                default: begin
277
`else
278
                `OR1200_ALUOP_COMP, `OR1200_ALUOP_AND: begin
279
`endif
280
                        result=result_and;
281
                end
282
        endcase
283
end
284
 
285
//
286
// Generate flag and flag write enable
287
//
288
always @(alu_op or result_sum or result_and or flagcomp
289
) begin
290 363 julius
        casez (alu_op)          // synopsys parallel_case
291 350 julius
`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
292 502 julius
`ifdef OR1200_IMPL_ADDC
293
                `OR1200_ALUOP_ADDC,
294
`endif
295 350 julius
                `OR1200_ALUOP_ADD : begin
296
                        flagforw = (result_sum == 32'h0000_0000);
297
                        flag_we = 1'b1;
298
                end
299
                `OR1200_ALUOP_AND: begin
300
                        flagforw = (result_and == 32'h0000_0000);
301
                        flag_we = 1'b1;
302
                end
303
`endif
304
                `OR1200_ALUOP_COMP: begin
305
                        flagforw = flagcomp;
306
                        flag_we = 1'b1;
307
                end
308
                default: begin
309
                        flagforw = flagcomp;
310
                        flag_we = 1'b0;
311
                end
312
        endcase
313
end
314
 
315
//
316
// Generate SR[CY] write enable
317
//
318
always @(alu_op or cy_sum
319
`ifdef OR1200_IMPL_CY
320
`ifdef OR1200_IMPL_SUB
321
        or cy_sub
322
`endif
323
`endif
324
) begin
325 363 julius
        casez (alu_op)          // synopsys parallel_case
326 350 julius
`ifdef OR1200_IMPL_CY
327 502 julius
`ifdef OR1200_IMPL_ADDC
328
                `OR1200_ALUOP_ADDC,
329
`endif
330 350 julius
                `OR1200_ALUOP_ADD : begin
331
                        cyforw = cy_sum;
332
                        cy_we = 1'b1;
333
                end
334
`ifdef OR1200_IMPL_SUB
335
                `OR1200_ALUOP_SUB: begin
336
                        cyforw = cy_sub;
337
                        cy_we = 1'b1;
338
                end
339
`endif
340
`endif
341
                default: begin
342
                        cyforw = 1'b0;
343
                        cy_we = 1'b0;
344
                end
345
        endcase
346
end
347
 
348 502 julius
 
349 350 julius
//
350 502 julius
// Generate SR[OV] write enable
351
//
352
always @(alu_op or ov_sum) begin
353
        casez (alu_op)          // synopsys parallel_case
354
`ifdef OR1200_IMPL_OV
355
`ifdef OR1200_IMPL_ADDC
356
                `OR1200_ALUOP_ADDC,
357
`endif
358
`ifdef OR1200_IMPL_SUB
359
                `OR1200_ALUOP_SUB,
360
`endif
361
                `OR1200_ALUOP_ADD : begin
362
                        ovforw = ov_sum;
363
                        ov_we = 1'b1;
364
                end
365
`endif
366
                default: begin
367
                        ovforw = 1'b0;
368
                        ov_we = 1'b0;
369
                end
370
        endcase
371
end
372
 
373
//
374 350 julius
// Shifts and rotation
375
//
376 499 julius
always @(alu_op2 or a or b) begin
377
        case (alu_op2)          // synopsys parallel_case
378
          `OR1200_SHROTOP_SLL :
379 350 julius
                                shifted_rotated = (a << b[4:0]);
380 499 julius
          `OR1200_SHROTOP_SRL :
381 350 julius
                                shifted_rotated = (a >> b[4:0]);
382
 
383
`ifdef OR1200_IMPL_ALU_ROTATE
384 499 julius
          `OR1200_SHROTOP_ROR :
385
                                shifted_rotated = (a << (6'd32-{1'b0,b[4:0]})) |
386
                                                  (a >> b[4:0]);
387 350 julius
`endif
388 499 julius
          default:
389
                                shifted_rotated = ({32{a[31]}} <<
390
                                                   (6'd32-{1'b0, b[4:0]})) |
391
                                                  a >> b[4:0];
392 350 julius
        endcase
393
end
394
 
395
//
396
// First type of compare implementation
397
//
398
`ifdef OR1200_IMPL_ALU_COMP1
399
always @(comp_op or a_eq_b or a_lt_b) begin
400
        case(comp_op[2:0])       // synopsys parallel_case
401
                `OR1200_COP_SFEQ:
402
                        flagcomp = a_eq_b;
403
                `OR1200_COP_SFNE:
404
                        flagcomp = ~a_eq_b;
405
                `OR1200_COP_SFGT:
406
                        flagcomp = ~(a_eq_b | a_lt_b);
407
                `OR1200_COP_SFGE:
408
                        flagcomp = ~a_lt_b;
409
                `OR1200_COP_SFLT:
410
                        flagcomp = a_lt_b;
411
                `OR1200_COP_SFLE:
412
                        flagcomp = a_eq_b | a_lt_b;
413
                default:
414
                        flagcomp = 1'b0;
415
        endcase
416
end
417
`endif
418
 
419
//
420
// Second type of compare implementation
421
//
422
`ifdef OR1200_IMPL_ALU_COMP2
423
always @(comp_op or comp_a or comp_b) begin
424
        case(comp_op[2:0])       // synopsys parallel_case
425
                `OR1200_COP_SFEQ:
426
                        flagcomp = (comp_a == comp_b);
427
                `OR1200_COP_SFNE:
428
                        flagcomp = (comp_a != comp_b);
429
                `OR1200_COP_SFGT:
430
                        flagcomp = (comp_a > comp_b);
431
                `OR1200_COP_SFGE:
432
                        flagcomp = (comp_a >= comp_b);
433
                `OR1200_COP_SFLT:
434
                        flagcomp = (comp_a < comp_b);
435
                `OR1200_COP_SFLE:
436
                        flagcomp = (comp_a <= comp_b);
437
                default:
438
                        flagcomp = 1'b0;
439
        endcase
440
end
441 504 julius
`endif //  `ifdef OR1200_IMPL_ALU_COMP2
442
 
443
`ifdef OR1200_IMPL_ALU_COMP3
444
always @(comp_op or a_eq_b or a_lt_b) begin
445
        case(comp_op[2:0])       // synopsys parallel_case
446
                `OR1200_COP_SFEQ:
447
                        flagcomp = a_eq_b;
448
                `OR1200_COP_SFNE:
449
                        flagcomp = ~a_eq_b;
450
                `OR1200_COP_SFGT:
451
                        flagcomp = ~(a_eq_b | a_lt_b);
452
                `OR1200_COP_SFGE:
453
                        flagcomp = ~a_lt_b;
454
                `OR1200_COP_SFLT:
455
                        flagcomp = a_lt_b;
456
                `OR1200_COP_SFLE:
457
                        flagcomp = a_eq_b | a_lt_b;
458
                default:
459
                        flagcomp = 1'b0;
460
        endcase
461
end
462 350 julius
`endif
463 504 julius
 
464 350 julius
 
465 499 julius
`ifdef OR1200_IMPL_ALU_EXT
466
   always @(alu_op or alu_op2 or a) begin
467
      casez (alu_op2)
468
        `OR1200_EXTHBOP_HS : extended = {{16{a[15]}},a[15:0]};
469
        `OR1200_EXTHBOP_BS : extended = {{24{a[7]}},a[7:0]};
470
        `OR1200_EXTHBOP_HZ : extended = {16'd0,a[15:0]};
471
        `OR1200_EXTHBOP_BZ : extended = {24'd0,a[7:0]};
472
        default: extended = a; // Used for l.extw instructions
473
      endcase // casez (alu_op2)
474
   end
475
`endif
476
 
477
 
478
//
479
// l.cust5 custom instructions
480
//
481
`ifdef OR1200_IMPL_ALU_CUST5
482
// Examples for move byte, set bit and clear bit
483
//
484
always @(cust5_op or cust5_limm or a or b) begin
485
        casez (cust5_op)                // synopsys parallel_case
486
                5'h1 : begin
487
                        casez (cust5_limm[1:0])
488
                          2'h0: result_cust5 = {a[31:8], b[7:0]};
489
                          2'h1: result_cust5 = {a[31:16], b[7:0], a[7:0]};
490
                          2'h2: result_cust5 = {a[31:24], b[7:0], a[15:0]};
491
                          2'h3: result_cust5 = {b[7:0], a[23:0]};
492
                        endcase
493
                end
494
                5'h2 :
495
                        result_cust5 = a | (1 << cust5_limm);
496
                5'h3 :
497
                        result_cust5 = a & (32'hffffffff ^ (1 << cust5_limm));
498
//
499
// *** Put here new l.cust5 custom instructions ***
500
//
501
                default: begin
502
                        result_cust5 = a;
503
                end
504
        endcase
505
end // always @ (cust5_op or cust5_limm or a or b)
506
`endif
507
 
508 350 julius
endmodule

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