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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [drivers/] [or1200/] [cache.S] - Blame information for rev 530

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Line No. Rev Author Line
1 530 julius 
#include "spr-defs.h"
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        /* Cache init. To be called during init ONLY */
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        .global _cache_init
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        .type   _cache_init,@function
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_cache_init:
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        /* Instruction cache enable */
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        /* Check if IC present and skip enabling otherwise */
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        l.mfspr r3,r0,SPR_UPR
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        l.andi  r4,r3,SPR_UPR_ICP
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        l.sfeq  r4,r0
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        l.bf    .L8
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        l.nop
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        /* Disable IC */
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        l.mfspr r6,r0,SPR_SR
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        l.addi  r5,r0,-1
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        l.xori  r5,r5,SPR_SR_ICE
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        l.and   r5,r6,r5
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        l.mtspr r0,r5,SPR_SR
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        /* Establish cache block size
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        If BS=0, 16;
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        If BS=1, 32;
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        r14 contain block size
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        */
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        l.mfspr r3,r0,SPR_ICCFGR
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        l.andi  r4,r3,SPR_ICCFGR_CBS
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        l.srli  r5,r4,7
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        l.ori   r6,r0,16
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        l.sll   r14,r6,r5
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        /* Establish number of cache sets
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        r7 contains number of cache sets
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        r5 contains log(# of cache sets)
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        */
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        l.andi  r4,r3,SPR_ICCFGR_NCS
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        l.srli  r5,r4,3
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        l.ori   r6,r0,1
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        l.sll   r7,r6,r5
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        /* Invalidate IC */
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        l.addi  r6,r0,0
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        l.sll   r5,r14,r5
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.L7:
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        l.mtspr r0,r6,SPR_ICBIR
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        l.sfne  r6,r5
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        l.bf    .L7
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        l.add   r6,r6,r14
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        /* Enable IC */
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        l.mfspr r6,r0,SPR_SR
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        l.ori   r6,r6,SPR_SR_ICE
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        l.mtspr r0,r6,SPR_SR
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        l.nop
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        l.nop
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        l.nop
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        l.nop
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        l.nop
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        l.nop
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        l.nop
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        l.nop
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.L8:
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        /* Data cache enable */
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        /* Check if DC present and skip enabling otherwise */
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        l.mfspr r3,r0,SPR_UPR
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        l.andi  r4,r3,SPR_UPR_DCP
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        l.sfeq  r4,r0
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        l.bf    .L10
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        l.nop
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        /* Disable DC */
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        l.mfspr r6,r0,SPR_SR
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        l.addi  r5,r0,-1
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        l.xori  r5,r5,SPR_SR_DCE
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        l.and   r5,r6,r5
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        l.mtspr r0,r5,SPR_SR
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        /* Establish cache block size
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           If BS=0, 16;
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           If BS=1, 32;
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           r14 contain block size
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        */
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        l.mfspr r3,r0,SPR_DCCFGR
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        l.andi  r4,r3,SPR_DCCFGR_CBS
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        l.srli  r5,r4,7
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        l.ori   r6,r0,16
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        l.sll   r14,r6,r5
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        /* Establish number of cache sets
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           r7 contains number of cache sets
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           r5 contains log(# of cache sets)
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        */
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        l.andi  r4,r3,SPR_DCCFGR_NCS
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        l.srli  r5,r4,3
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        l.ori   r6,r0,1
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        l.sll   r7,r6,r5
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        /* Invalidate DC */
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        l.addi  r6,r0,0
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        l.sll   r5,r14,r5
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.L9:
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        l.mtspr r0,r6,SPR_DCBIR
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        l.sfne  r6,r5
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        l.bf    .L9
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        l.add   r6,r6,r14
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        /* Enable DC */
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        l.mfspr r6,r0,SPR_SR
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        l.ori   r6,r6,SPR_SR_DCE
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        l.mtspr r0,r6,SPR_SR
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.L10:
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        /* Return */
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        l.jr    r9
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        l.nop

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