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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [ethmac/] [sim/] [ethmac-tx.c] - Blame information for rev 439

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1 349 julius
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  Interrupt-driven Ethernet MAC transmit test code            ////
4
////                                                              ////
5
////  Description                                                 ////
6
////  Transmits packets, testing both 100mbit and 10mbit modes.   ////
7
////  Expects testbench to be checking each packet sent.          ////   
8
////  Define, ETH_TX_TEST_LENGTH, set further down, controls how  ////
9
////  many packets the test will send.                            ////
10
////                                                              ////
11
////  Author(s):                                                  ////
12
////      - jb, jb@orsoc.se, with parts taken from Linux kernel   ////
13
////        open_eth driver.                                      ////
14
////                                                              ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
 
43 411 julius
#include "cpu-utils.h"
44 349 julius
#include "board.h"
45
#include "int.h"
46 411 julius
#include "ethmac.h"
47 349 julius
#include "eth-phy-mii.h"
48
 
49
volatile unsigned tx_done;
50
volatile unsigned rx_done;
51
static int next_tx_buf_num;
52
 
53
/* Functions in this file */
54
void ethmac_setup(void);
55
/* Interrupt functions */
56
void oeth_interrupt(void);
57
static void oeth_rx(void);
58
static void oeth_tx(void);
59
 
60
/* Let the ethernet packets use a space beginning here for buffering */
61 439 julius
#define ETH_BUFF_BASE 0x200000;
62 349 julius
 
63
#define RXBUFF_PREALLOC 1
64
#define TXBUFF_PREALLOC 1
65
//#undef RXBUFF_PREALLOC
66
//#undef TXBUFF_PREALLOC
67
 
68
/* The transmitter timeout
69
 */
70
#define TX_TIMEOUT      (2*HZ)
71
 
72
/* Buffer number (must be 2^n)
73
 */
74
#define OETH_RXBD_NUM           16
75
#define OETH_TXBD_NUM           16
76
#define OETH_RXBD_NUM_MASK      (OETH_RXBD_NUM-1)
77
#define OETH_TXBD_NUM_MASK      (OETH_TXBD_NUM-1)
78
 
79
/* Buffer size
80
 */
81
#define OETH_RX_BUFF_SIZE       0x600 - 4
82
#define OETH_TX_BUFF_SIZE       0x600 - 4
83
 
84
/* Buffer size  (if not XXBUF_PREALLOC
85
 */
86
#define MAX_FRAME_SIZE          1518
87
 
88
/* The buffer descriptors track the ring buffers.
89
 */
90
struct oeth_private {
91
 
92 411 julius
  unsigned short        tx_next;/* Next buffer to be sent */
93
  unsigned short        tx_last;/* Next buffer to be checked if packet sent */
94
  unsigned short        tx_full;/* Buffer ring fuul indicator */
95
  unsigned short        rx_cur; /* Next buffer to check if packet received */
96 349 julius
 
97 411 julius
  oeth_regs             *regs;          /* Address of controller registers. */
98 349 julius
  oeth_bd               *rx_bd_base;            /* Address of Rx BDs. */
99
  oeth_bd               *tx_bd_base;            /* Address of Tx BDs. */
100
 
101
  //    struct net_device_stats stats;
102
};
103
 
104
 
105
// Data array of data to transmit, tx_data_array[]
106 411 julius
// Not included in ORPSoC - #include "eth-rxtx-data.h"
107
//int tx_data_pointer;
108 349 julius
 
109
#define PHYNUM 7
110
 
111
void
112
eth_mii_write(char phynum, short regnum, short data)
113
{
114
  static volatile oeth_regs *regs = (oeth_regs *)(OETH_REG_BASE);
115
  regs->miiaddress = (regnum << 8) | phynum;
116
  regs->miitx_data = data;
117
  regs->miicommand = OETH_MIICOMMAND_WCTRLDATA;
118
  regs->miicommand = 0;
119
  while(regs->miistatus & OETH_MIISTATUS_BUSY);
120
}
121
 
122
short
123
eth_mii_read(char phynum, short regnum)
124
{
125
  static volatile oeth_regs *regs = (oeth_regs *)(OETH_REG_BASE);
126
  regs->miiaddress = (regnum << 8) | phynum;
127
  regs->miicommand = OETH_MIICOMMAND_RSTAT;
128
  regs->miicommand = 0;
129
  while(regs->miistatus & OETH_MIISTATUS_BUSY);
130
 
131
  return regs->miirx_data;
132
}
133
 
134
 
135
// Wait here until all packets have been transmitted
136
void wait_until_all_tx_clear(void)
137
{
138
 
139
  int i;
140
  volatile oeth_bd *tx_bd;
141
  tx_bd = (volatile oeth_bd *)OETH_BD_BASE; /* Search from beginning*/
142
 
143
  int some_tx_waiting = 1;
144
 
145
  while (some_tx_waiting)
146
    {
147
      some_tx_waiting = 0;
148
      /* Go through the TX buffs, search for unused one */
149
      for(i = 0; i < OETH_TXBD_NUM; i++) {
150
 
151
        if((tx_bd[i].len_status & OETH_TX_BD_READY)) // Looking for buffer ready for transmit
152
          some_tx_waiting = 1;
153
 
154
      }
155
    }
156
 
157
}
158
 
159
 
160
void
161
ethphy_set_10mbit(int phynum)
162
{
163
  wait_until_all_tx_clear();
164
  // Hardset PHY to just use 10Mbit mode
165
  short cr = eth_mii_read(phynum, MII_BMCR);
166
  cr &= ~BMCR_ANENABLE; // Clear auto negotiate bit
167
  cr &= ~BMCR_SPEED100; // Clear fast eth. bit
168
  eth_mii_write(phynum, MII_BMCR, cr);
169
}
170
 
171
 
172
void
173
ethphy_set_100mbit(int phynum)
174
{
175
  wait_until_all_tx_clear();
176
  // Hardset PHY to just use 100Mbit mode
177
  short cr = eth_mii_read(phynum, MII_BMCR);
178
  cr |= BMCR_ANENABLE; // Clear auto negotiate bit
179
  cr |= BMCR_SPEED100; // Clear fast eth. bit
180
  eth_mii_write(phynum, MII_BMCR, cr);
181
}
182
 
183
 
184
void ethmac_setup(void)
185
{
186
  // from arch/or32/drivers/open_eth.c
187
  volatile oeth_regs *regs;
188
 
189
  regs = (oeth_regs *)(OETH_REG_BASE);
190
 
191
  /* Reset MII mode module */
192
  regs->miimoder = OETH_MIIMODER_RST; /* MII Reset ON */
193
  regs->miimoder &= ~OETH_MIIMODER_RST; /* MII Reset OFF */
194
  regs->miimoder = 0x64; /* Clock divider for MII Management interface */
195
 
196
  /* Reset the controller.
197
   */
198
  regs->moder = OETH_MODER_RST; /* Reset ON */
199
  regs->moder &= ~OETH_MODER_RST;       /* Reset OFF */
200
 
201
  /* Setting TXBD base to OETH_TXBD_NUM.
202
   */
203
  regs->tx_bd_num = OETH_TXBD_NUM;
204
 
205
 
206
  /* Set min/max packet length
207
   */
208
  regs->packet_len = 0x00400600;
209
 
210
  /* Set IPGT register to recomended value
211
   */
212
  regs->ipgt = 0x12;
213
 
214
  /* Set IPGR1 register to recomended value
215
   */
216
  regs->ipgr1 = 0x0000000c;
217
 
218
  /* Set IPGR2 register to recomended value
219
   */
220
  regs->ipgr2 = 0x00000012;
221
 
222
  /* Set COLLCONF register to recomended value
223
   */
224
  regs->collconf = 0x000f003f;
225
 
226
  /* Set control module mode
227
   */
228
#if 0
229
  regs->ctrlmoder = OETH_CTRLMODER_TXFLOW | OETH_CTRLMODER_RXFLOW;
230
#else
231
  regs->ctrlmoder = 0;
232
#endif
233
 
234
  /* Clear MIIM registers */
235
  regs->miitx_data = 0;
236
  regs->miiaddress = 0;
237
  regs->miicommand = 0;
238
 
239
  regs->mac_addr1 = ETH_MACADDR0 << 8 | ETH_MACADDR1;
240
  regs->mac_addr0 = ETH_MACADDR2 << 24 | ETH_MACADDR3 << 16 | ETH_MACADDR4 << 8 | ETH_MACADDR5;
241
 
242
  /* Clear all pending interrupts
243
   */
244
  regs->int_src = 0xffffffff;
245
 
246
  /* Promisc, IFG, CRCEn
247
   */
248
  regs->moder |= OETH_MODER_PRO | OETH_MODER_PAD | OETH_MODER_IFG | OETH_MODER_CRCEN | OETH_MODER_FULLD;
249
 
250
  /* Enable interrupt sources.
251
   */
252
 
253
  regs->int_mask = OETH_INT_MASK_TXB    |
254
    OETH_INT_MASK_TXE   |
255
    OETH_INT_MASK_RXF   |
256
    OETH_INT_MASK_RXE   |
257
    OETH_INT_MASK_BUSY  |
258
    OETH_INT_MASK_TXC   |
259
    OETH_INT_MASK_RXC;
260
 
261
  // Buffer setup stuff
262
  volatile oeth_bd *tx_bd, *rx_bd;
263
  int i,j,k;
264
 
265
  /* Initialize TXBD pointer
266
   */
267
  tx_bd = (volatile oeth_bd *)OETH_BD_BASE;
268
 
269
  /* Initialize RXBD pointer
270
   */
271
  rx_bd = ((volatile oeth_bd *)OETH_BD_BASE) + OETH_TXBD_NUM;
272
 
273
  /* Preallocated ethernet buffer setup */
274
  unsigned long mem_addr = ETH_BUFF_BASE; /* Defined at top */
275
 
276
 // Setup TX Buffers
277
  for(i = 0; i < OETH_TXBD_NUM; i++) {
278
      //tx_bd[i].len_status = OETH_TX_BD_PAD | OETH_TX_BD_CRC | OETH_RX_BD_IRQ;
279
      tx_bd[i].len_status = OETH_TX_BD_PAD | OETH_TX_BD_CRC;
280
      tx_bd[i].addr = mem_addr;
281
      mem_addr += OETH_TX_BUFF_SIZE;
282
  }
283
  tx_bd[OETH_TXBD_NUM - 1].len_status |= OETH_TX_BD_WRAP;
284
 
285
  // Setup RX buffers
286
  for(i = 0; i < OETH_RXBD_NUM; i++) {
287
    rx_bd[i].len_status = OETH_RX_BD_EMPTY | OETH_RX_BD_IRQ; // Init. with IRQ
288
    rx_bd[i].addr = mem_addr;
289
    mem_addr += OETH_RX_BUFF_SIZE;
290
  }
291
  rx_bd[OETH_RXBD_NUM - 1].len_status |= OETH_RX_BD_WRAP; // Last buffer wraps
292
 
293
  /* Enable JUST the transmiter
294
   */
295
  regs->moder &= ~(OETH_MODER_RXEN | OETH_MODER_TXEN);
296
  regs->moder |= /*OETH_MODER_RXEN |*/ OETH_MODER_TXEN;
297
 
298
  next_tx_buf_num = 0; // init tx buffer pointer
299
 
300
  return;
301
}
302
 
303
 
304
 
305
/* Setup buffer descriptors with data */
306
/* length is in BYTES */
307
void tx_packet(void* data, int length)
308
{
309
  volatile oeth_regs *regs;
310
  regs = (oeth_regs *)(OETH_REG_BASE);
311
 
312
  volatile oeth_bd *tx_bd;
313
  volatile int i;
314
 
315
   tx_bd = (volatile oeth_bd *)OETH_BD_BASE;
316
   tx_bd = (struct oeth_bd*) &tx_bd[next_tx_buf_num];
317
 
318
   // If it's in use - wait
319
   while ((tx_bd->len_status & OETH_TX_BD_IRQ));
320
 
321
   /* Clear all of the status flags.
322
   */
323
   tx_bd->len_status &= ~OETH_TX_BD_STATS;
324
 
325
  /* If the frame is short, tell CPM to pad it.
326
   */
327
  #define ETH_ZLEN        60   /* Min. octets in frame sans FCS */
328
  if (length <= ETH_ZLEN)
329
    tx_bd->len_status |= OETH_TX_BD_PAD;
330
  else
331
    tx_bd->len_status &= ~OETH_TX_BD_PAD;
332
 
333
  if (data){
334
    //Copy the data into the transmit buffer, byte at a time 
335
    char* data_p = (char*) data;
336
    char* data_b = (char*) tx_bd->addr;
337
    for(i=0;i<length;i++)
338
      {
339
        data_b[i] = data_p[i];
340
      }
341
  }
342
 
343
  /* Set the length of the packet's data in the buffer descriptor */
344
  tx_bd->len_status = (tx_bd->len_status & 0x0000ffff) |
345
    ((length&0xffff) << 16);
346
 
347
  /* Send it on its way.  Tell controller its ready, interrupt when sent
348
  * and to put the CRC on the end.
349
  */
350
  tx_bd->len_status |= (OETH_TX_BD_READY  | OETH_TX_BD_CRC | OETH_TX_BD_IRQ);
351
 
352
  next_tx_buf_num = (next_tx_buf_num + 1) & OETH_TXBD_NUM_MASK;
353
 
354
  return;
355
 
356
}
357
 
358
/* The interrupt handler.
359
 */
360
void
361
oeth_interrupt(void)
362
{
363
 
364
  volatile oeth_regs *regs;
365
  regs = (oeth_regs *)(OETH_REG_BASE);
366
 
367
  uint  int_events;
368
  int serviced;
369
 
370
        serviced = 0;
371
 
372
        /* Get the interrupt events that caused us to be here.
373
         */
374
        int_events = regs->int_src;
375
        regs->int_src = int_events;
376
 
377
 
378
        /* Handle receive event in its own function.
379
         */
380
        if (int_events & (OETH_INT_RXF | OETH_INT_RXE)) {
381
                serviced |= 0x1;
382
                oeth_rx();
383
        }
384
 
385
        /* Handle transmit event in its own function.
386
         */
387
        if (int_events & (OETH_INT_TXB | OETH_INT_TXE)) {
388
                serviced |= 0x2;
389
                oeth_tx();
390
                serviced |= 0x2;
391
 
392
        }
393
 
394
        /* Check for receive busy, i.e. packets coming but no place to
395
         * put them.
396
         */
397
        if (int_events & OETH_INT_BUSY) {
398
                serviced |= 0x4;
399
                if (!(int_events & (OETH_INT_RXF | OETH_INT_RXE)))
400
                  oeth_rx();
401
        }
402
 
403
        return;
404
}
405
 
406
 
407
 
408
static void
409
oeth_rx(void)
410
{
411
  volatile oeth_regs *regs;
412
  regs = (oeth_regs *)(OETH_REG_BASE);
413
 
414
  volatile oeth_bd *rx_bdp;
415
  int   pkt_len, i;
416
  int   bad = 0;
417
 
418
  rx_bdp = ((oeth_bd *)OETH_BD_BASE) + OETH_TXBD_NUM;
419
 
420
 
421
  /* Find RX buffers marked as having received data */
422
  for(i = 0; i < OETH_RXBD_NUM; i++)
423
    {
424
      bad=0;
425
      if(!(rx_bdp[i].len_status & OETH_RX_BD_EMPTY)){ /* Looking for NOT empty buffers desc. */
426
        /* Check status for errors.
427
         */
428
        if (rx_bdp[i].len_status & (OETH_RX_BD_TOOLONG | OETH_RX_BD_SHORT)) {
429
          bad = 1;
430
          report(0xbaad0001);
431
        }
432
        if (rx_bdp[i].len_status & OETH_RX_BD_DRIBBLE) {
433
          bad = 1;
434
          report(0xbaad0002);
435
        }
436
        if (rx_bdp[i].len_status & OETH_RX_BD_CRCERR) {
437
          bad = 1;
438
          report(0xbaad0003);
439
        }
440
        if (rx_bdp[i].len_status & OETH_RX_BD_OVERRUN) {
441
          bad = 1;
442
          report(0xbaad0004);
443
        }
444
        if (rx_bdp[i].len_status & OETH_RX_BD_MISS) {
445
          report(0xbaad0005);
446
        }
447
        if (rx_bdp[i].len_status & OETH_RX_BD_LATECOL) {
448
          bad = 1;
449
          report(0xbaad0006);
450
        }
451
        if (bad) {
452
          rx_bdp[i].len_status &= ~OETH_RX_BD_STATS;
453
          rx_bdp[i].len_status |= OETH_RX_BD_EMPTY;
454
          exit(0xbaaaaaad);
455
 
456
          continue;
457
        }
458
        else {
459
          /* Process the incoming frame.
460
           */
461
          pkt_len = rx_bdp[i].len_status >> 16;
462
 
463
          /* Do something here with the data - copy it into userspace, perhaps*/
464
 
465
          /* finish up */
466
          rx_bdp[i].len_status &= ~OETH_RX_BD_STATS; /* Clear stats */
467
          rx_bdp[i].len_status |= OETH_RX_BD_EMPTY; /* Mark RX BD as empty */
468
          rx_done++;
469
        }
470
      }
471
    }
472
}
473
 
474
 
475
 
476
static void
477
oeth_tx(void)
478
{
479
  volatile oeth_bd *tx_bd;
480
  int i;
481
 
482
  tx_bd = (volatile oeth_bd *)OETH_BD_BASE; /* Search from beginning*/
483
 
484
  /* Go through the TX buffs, search for one that was just sent */
485
  for(i = 0; i < OETH_TXBD_NUM; i++)
486
    {
487
      /* Looking for buffer NOT ready for transmit. and IRQ enabled */
488
      if( (!(tx_bd[i].len_status & (OETH_TX_BD_READY))) && (tx_bd[i].len_status & (OETH_TX_BD_IRQ)) )
489
        {
490
          /* Single threaded so no chance we have detected a buffer that has had its IRQ bit set but not its BD_READ flag. Maybe this won't work in linux */
491
          tx_bd[i].len_status &= ~OETH_TX_BD_IRQ;
492
 
493
          /* Probably good to check for TX errors here */
494
 
495
          /* set our test variable */
496
          tx_done++;
497
 
498
        }
499
    }
500
  return;
501
}
502
 
503
// A function and defines to fill and transmit a packet
504
#define MAX_TX_BUFFER 1532
505
static char tx_buffer[MAX_TX_BUFFER];
506
 
507
void
508
fill_and_tx_packet(int size)
509
{
510
  int i;
511
  char tx_byte;
512
 
513
  volatile oeth_regs *regs;
514
  regs = (oeth_regs *)(OETH_REG_BASE);
515
 
516
  volatile oeth_bd *tx_bd;
517
 
518
  tx_bd = (volatile oeth_bd *)OETH_BD_BASE;
519
  tx_bd = (struct oeth_bd*) &tx_bd[next_tx_buf_num];
520
 
521
  // If it's in use - wait
522
  while ((tx_bd->len_status & OETH_TX_BD_IRQ));
523
 
524 411 julius
  // Use rand() function to generate data for transmission
525
  // Assumption: ethernet buffer descriptors are 4byte aligned
526 349 julius
  char* data_b = (char*) tx_bd->addr;
527 411 julius
  // We will fill with words until there' less than a word to go
528
  int words_to_fill = size/ sizeof(unsigned int);
529
  unsigned int* data_w = (unsigned int*) data_b;
530
 
531
  for(i=0;i<words_to_fill;i++)
532
    data_w[i] = rand();
533
 
534
  // Point data_b to offset wher word fills ended
535
  data_b += (words_to_fill * sizeof(unsigned int));
536
 
537
  int leftover_size = size - (words_to_fill * sizeof(unsigned int));
538
 
539
  for(i=0;i<leftover_size;i++)
540 349 julius
    {
541 411 julius
      data_b[i] = rand()&0xff;
542 349 julius
    }
543
 
544
   tx_packet((void*)0, size);
545
}
546
 
547 411 julius
int
548
main ()
549
{
550
  int i;
551 349 julius
 
552
  /* Initialise handler vector */
553
  int_init();
554
 
555
  /* Install ethernet interrupt handler, it is enabled here too */
556
  int_add(ETH0_IRQ, oeth_interrupt, 0);
557
 
558
  /* Enable interrupts in supervisor register */
559 411 julius
  cpu_enable_user_interrupts();
560 349 julius
 
561
  ethmac_setup(); /* Configure MAC, TX/RX BDs and enable RX and TX in MODER */
562
 
563
  /* clear tx_done, the tx interrupt handler will set it when it's been transmitted */
564
  tx_done = 0;
565
  rx_done = 0;
566
 
567
  ethphy_set_100mbit(0);
568
 
569
#ifndef ETH_TX_TEST_LENGTH
570 411 julius
# define ETH_TX_START_LENGTH  40
571
# define ETH_TX_TEST_LENGTH  1024
572
# define ETH_TX_TEST_LENGTH_INCREMENT  21
573 349 julius
  //# define ETH_TX_TEST_LENGTH  OETH_TX_BUFF_SIZE
574
#endif
575
 
576 411 julius
  for(i=ETH_TX_START_LENGTH;i<ETH_TX_TEST_LENGTH;
577
      i+=ETH_TX_TEST_LENGTH_INCREMENT)
578 349 julius
    fill_and_tx_packet(i);
579
 
580
  ethphy_set_10mbit(0);
581 411 julius
 
582
  for(i=ETH_TX_START_LENGTH;i<ETH_TX_TEST_LENGTH;
583
      i+=ETH_TX_TEST_LENGTH_INCREMENT)
584 349 julius
    fill_and_tx_packet(i);
585
 
586
  exit(0x8000000d);
587
 
588
 
589
}

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