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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [or1200/] [sim/] [or1200-except.S] - Blame information for rev 412

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Line No. Rev Author Line
1 349 julius
/*
2
        Exception test.
3
 
4
        The following list outlines the tests performed
5
 
6
        Execption test
7
        - 0x100 reset                        - start addr after reset
8
        - 0x200 bus error                    - unimplemented addr is accessed
9
        - 0x300 data page fault              - NOT tested here
10
        - 0x400 instruction page fault       - NOT tested here
11
        - 0x500 tick timer                   - NOT tested here
12
        - 0x600 alignment                    - write to unaligned addr
13
        - 0x700 illegal instruction          - use unimplemented inst. l.div
14
        - 0x800 external interrupt           - int triggered from wb slave
15
        - 0x900 d-tlb miss                   - translation tests
16
        - 0xA00 i-tlb miss                   - NOT tested here
17
        - 0xB00 range                        - NOT tested here
18
        - 0xC00 system call                  - NOT tested here
19
        - 0xD00 floating point               - NOT tested here
20
        - 0xE00 trap                         - NOT tested here
21
        - 0xF00 RESERVED
22
 
23
        r11 - 1st exception counter incremented inside exception
24
        r12 - 2nd exception counter incremented outside and rigth after
25
              exception
26
        ... other register use to be documented...
27
 
28
        Julius Baxter, julius@opencores.org
29
        Tadej Markovic, tadej@opencores.org
30
 
31
*/
32
//////////////////////////////////////////////////////////////////////
33
////                                                              ////
34
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
35
////                                                              ////
36
//// This source file may be used and distributed without         ////
37
//// restriction provided that this copyright statement is not    ////
38
//// removed from the file and that any derivative work contains  ////
39
//// the original copyright notice and the associated disclaimer. ////
40
////                                                              ////
41
//// This source file is free software; you can redistribute it   ////
42
//// and/or modify it under the terms of the GNU Lesser General   ////
43
//// Public License as published by the Free Software Foundation; ////
44
//// either version 2.1 of the License, or (at your option) any   ////
45
//// later version.                                               ////
46
////                                                              ////
47
//// This source is distributed in the hope that it will be       ////
48
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
49
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
50
//// PURPOSE.  See the GNU Lesser General Public License for more ////
51
//// details.                                                     ////
52
////                                                              ////
53
//// You should have received a copy of the GNU Lesser General    ////
54
//// Public License along with this source; if not, download it   ////
55
//// from http://www.opencores.org/lgpl.shtml                     ////
56
////                                                              ////
57
//////////////////////////////////////////////////////////////////////
58
 
59
#include "spr-defs.h"
60
#include "board.h"
61
#include "or1200-defines.h"
62
 
63
/* =================================================== [ exceptions ] === */
64
        .section .vectors, "ax"
65
 
66
 
67
/* ---[ 0x100: RESET exception ]----------------------------------------- */
68
        .org 0x100
69
        l.movhi r0, 0
70
        /* Clear status register */
71
        l.ori   r1, r0, SPR_SR_SM
72
        l.mtspr r0, r1, SPR_SR
73
        /* Clear timer  */
74
        l.mtspr r0, r0, SPR_TTMR
75
        /* Init the stack */
76
        .global stack
77
        l.movhi r1, hi(stack)
78
        l.ori   r1, r1, lo(stack)
79
        l.addi  r2, r0, -3
80
        l.and   r1, r1, r2
81
        /* Jump to program initialisation code */
82
        .global _start
83
        l.movhi r4, hi(_start)
84
        l.ori   r4, r4, lo(_start)
85
        l.jr    r4
86
        l.nop
87
 
88
 
89
/* ---[ 0x200: BUS error ]------------------------------------------------ */
90
        .org 0x200
91
        .global _bus_handler
92
_bus_handler:
93
        l.mfspr r3,r0,SPR_EPCR_BASE     /* Get EPC */
94
        l.nop   2
95
        l.mfspr r3,r0,SPR_EEAR_BASE     /* Get EEA */
96
        l.nop   2
97
        l.addi  r11,r11,1               /* Increment 1st exception counter */
98
        l.sfeqi r30, 0xd /* Is this a data bus test, if so return with l.rfe */
99
        l.bf 1f
100
        l.movhi r5, 0    /* r5 should be the one causing the error on dbus */
101
        /* Instruction bus error test return */
102
        l.movhi r5, hi(0x44004800) /* Put "l.jr r9" instruction in r5 */
103
        l.ori r5, r5, lo(0x44004800)
104
        l.sw 0x0(r0), r5 /* Write "l.j r9" to address 0x0 in RAM */
105
        l.movhi r5,0x1500       /* Put a "l.nop"  instruction in r5 */
106
        l.sw    0x4(r0),r5      /* Write l.nop instruction to RAM addr 0x4 */
107
        l.mtspr r0,r0,SPR_ICBIR         /* Invalidate line 0 of cache */
108
        l.mtspr r0,r0,SPR_EPCR_BASE     /* RFE to 0x0, which is l.jr r9 */
109
1:      l.rfe
110
 
111
/* ---[ 0x600: ALIGN error ]------------------------------------------------ */
112
        .org 0x600
113
        .global _align_handler
114
_align_handler:
115
        l.mfspr r3,r0,SPR_EPCR_BASE     /* Get EPC */
116
        l.nop   2
117
        l.addi  r11,r11,1               /* Increment 1st exception counter */
118
        l.movhi r5,0                    /* Clear the pointer register */
119
        l.rfe
120
 
121
 
122
/* ---[ 0x700: ILLEGAL INSN exception ]------------------------------------- */
123
        .org 0x700
124
        .global _illinsn_handler
125
_illinsn_handler:
126
        l.mfspr r3,r0,SPR_EPCR_BASE     /* Get EPC */
127
        l.nop   2
128
        l.addi  r11,r11,1               /* Increment 1st exception counter */
129
        /* Delay slot test needs this instruction "fixed" */
130
        l.movhi r5,0x1500               /* Put a "l.nop"  instruction in r5 */
131
        l.sw    0x4(r0),r5      /* Write l.nop instruction to RAM addr 0x4 */
132
        l.mtspr r0,r0,SPR_ICBIR         /* Invalidate line 0 of cache */
133
        l.mtspr r0,r0,SPR_EPCR_BASE     /* Jump to 0, which is l.jr r9 */
134
        l.rfe
135
 
136
/* ---[ 0x900: DTLB exception ]--------------------------------------------- */
137
        .org 0x900
138
        .global _dtlb_handler
139
/* Exception handler - DMMU TLB miss */
140
/* Assume 64-entry TLB cache */
141
_dtlb_handler:
142
        l.mfspr r20, r0, SPR_EEAR_BASE
143
        /* Find the entry/set for this address */
144
        l.srli r21, r20, 13 /* r21 = VPN, shift by size 8192 = 2**13 */
145
        l.andi r22, r21, 0x3f /* 64 entries = 6 bit mask, r22 = set number */
146
        /* If page is in the 0xc0000000 space we map to 16MB part of
147
        memory, ie 0x0 => 0x01000000, otherwise 1-1 mapping */
148
        l.movhi r23, hi(0xc0000000)
149
        l.ori r23, r23, lo(0xc0000000)
150
        l.srli r23, r23, 13 /* Get page address, shift by page size, 13 bits */
151
        l.movhi r24, hi(0xff << 11) /* Mask for top byte of VPN */
152
        l.ori r24, r24, lo(0xff << 11)
153
        l.and r24, r24, r21 /* Mask in only top byte of VPN */
154
        l.sfeq r23, r24 /* Decide if it's in our special mapped region or not*/
155
 
156
        /* First, Setup value for DTLBM (match) reg, is same for both cases */
157
        l.movhi r24, hi(SPR_ITLBMR_VPN) /* VPN mask into r24 */
158
        l.ori r24, r24, lo(SPR_ITLBMR_VPN)
159
        l.and r25, r20, r24 /* AND address with VPN mask */
160
        l.ori r25, r25, SPR_DTLBMR_V /* OR in valid bit */
161
        l.mtspr r22, r25, SPR_DTLBMR_BASE(0) /* Write to DTLBR register */
162
 
163
        l.bf _highmem_map
164
        l.nop
165
 
166
_lomem_map:
167
        /* Do 1:1 mapping for this request */
168
        /* Setup value for translate register */
169
        l.movhi r24, hi(SPR_ITLBTR_PPN) /* PPN mask into r24 */
170
        l.ori r24, r24, lo(SPR_ITLBTR_PPN)
171
        l.and r25, r20, r24 /* AND address with PPN mask */
172
        l.ori r25, r25, DTLB_PR_NOLIMIT /* Set all execute enables, no lims. */
173
        l.mtspr r22, r25, SPR_DTLBTR_BASE(0) /* Write to DTLTR register */
174
        l.j _dtlb_done
175
        l.addi r18, r18, 1 /* Incremement low-mapping counter */
176
 
177
_highmem_map:
178
        /* Do top byte, 0xc0->0x01, mapping for this request */
179
        /* Setup value for translate register */
180
        l.movhi r24, hi(SPR_ITLBTR_PPN) /* PPN mask into r24 */
181
        l.ori r24, r24, lo(SPR_ITLBTR_PPN)
182
        l.and r25, r20, r24 /* AND address with PPN mask */
183
        l.movhi r26, hi(0xff000000) /* Top byte address mask */
184
        l.or r25, r26, r25 /* Set top byte to 0xff */
185
        l.xor r25, r26, r25 /* Now clear top byte with XOR */
186
        l.movhi r26, hi(0x01000000) /* Top address byte */
187
        l.or r25, r26, r25 /* Set top address byte */
188
        l.ori r25, r25, DTLB_PR_NOLIMIT /* Set all execute enables, no lims. */
189
        l.mtspr r22, r25, SPR_DTLBTR_BASE(0) /* Write to DTLTR register */
190
        l.addi r19, r19, 1 /* Incremement low-mapping counter */
191
 
192
_dtlb_done:
193
 
194
        l.rfe
195
 
196
 
197
 
198
/* =================================================== [ text section ] === */
199
        .section  .text
200
 
201
/* =================================================== [ start ] === */
202
 
203
        .global _start
204
_start:
205
 
206
        /* Instruction cache enable */
207
        /* Check if IC present and skip enabling otherwise */
208
        l.mfspr r24,r0,SPR_UPR
209
        l.andi  r26,r24,SPR_UPR_ICP
210
        l.sfeq  r26,r0
211
        l.bf    .L8
212
        l.nop
213
 
214
        /* Disable IC */
215
        l.mfspr r6,r0,SPR_SR
216
        l.addi  r5,r0,-1
217
        l.xori  r5,r5,SPR_SR_ICE
218
        l.and   r5,r6,r5
219
        l.mtspr r0,r5,SPR_SR
220
 
221
        /* Establish cache block size
222
        If BS=0, 16;
223
        If BS=1, 32;
224
        r14 contain block size
225
        */
226
        l.mfspr r24,r0,SPR_ICCFGR
227
        l.andi  r26,r24,SPR_ICCFGR_CBS
228
        l.srli  r28,r26,7
229
        l.ori   r30,r0,16
230
        l.sll   r14,r30,r28
231
 
232
        /* Establish number of cache sets
233
        r16 contains number of cache sets
234
        r28 contains log(# of cache sets)
235
        */
236
        l.andi  r26,r24,SPR_ICCFGR_NCS
237
        l.srli  r28,r26,3
238
        l.ori   r30,r0,1
239
        l.sll   r16,r30,r28
240
 
241
        /* Invalidate IC */
242
        l.addi  r6,r0,0
243
        l.sll   r5,r14,r28
244
 
245
.L7:
246
        l.mtspr r0,r6,SPR_ICBIR
247
        l.sfne  r6,r5
248
        l.bf    .L7
249
        l.add   r6,r6,r14
250
 
251
        /* Enable IC */
252
        l.mfspr r6,r0,SPR_SR
253
        l.ori   r6,r6,SPR_SR_ICE
254
        l.mtspr r0,r6,SPR_SR
255
        l.nop
256
        l.nop
257
        l.nop
258
        l.nop
259
        l.nop
260
        l.nop
261
        l.nop
262
        l.nop
263
 
264
.L8:
265
        /* Data cache enable */
266
        /* Check if DC present and skip enabling otherwise */
267
        l.mfspr r24,r0,SPR_UPR
268
        l.andi  r26,r24,SPR_UPR_DCP
269
        l.sfeq  r26,r0
270
        l.bf    .L10
271
        l.nop
272
        /* Disable DC */
273
        l.mfspr r6,r0,SPR_SR
274
        l.addi  r5,r0,-1
275
        l.xori  r5,r5,SPR_SR_DCE
276
        l.and   r5,r6,r5
277
        l.mtspr r0,r5,SPR_SR
278
        /* Establish cache block size
279
           If BS=0, 16;
280
           If BS=1, 32;
281
           r14 contain block size
282
        */
283
        l.mfspr r24,r0,SPR_DCCFGR
284
        l.andi  r26,r24,SPR_DCCFGR_CBS
285
        l.srli  r28,r26,7
286
        l.ori   r30,r0,16
287
        l.sll   r14,r30,r28
288
        /* Establish number of cache sets
289
           r16 contains number of cache sets
290
           r28 contains log(# of cache sets)
291
        */
292
        l.andi  r26,r24,SPR_DCCFGR_NCS
293
        l.srli  r28,r26,3
294
        l.ori   r30,r0,1
295
        l.sll   r16,r30,r28
296
        /* Invalidate DC */
297
        l.addi  r6,r0,0
298
        l.sll   r5,r14,r28
299
.L9:
300
        l.mtspr r0,r6,SPR_DCBIR
301
        l.sfne  r6,r5
302
        l.bf    .L9
303
        l.add   r6,r6,r14
304
        /* Enable DC */
305
        l.mfspr r6,r0,SPR_SR
306
        l.ori   r6,r6,SPR_SR_DCE
307
        l.mtspr r0,r6,SPR_SR
308
.L10:
309
        // Kick off test
310
        l.jal   _main
311
        l.nop
312
 
313
/* ========================================================= [ main ] === */
314
 
315
        .global _main
316
        .global _dmmu_invalidate
317
        .global _dmmu_except1
318
 
319
_main:
320
        l.nop
321
        l.addi  r3,r0,0
322
        l.addi  r5,r0,0
323
        l.addi  r11,r0,0 /* exception counter 1 */
324
        l.addi  r12,r0,0 /* exception counter 2 */
325
        l.addi  r13,r0,0
326
        l.addi  r18,r0,0 /* DMMU exception counter for low mem mapping */
327
        l.addi  r19,r0,0 /* DMMU exception counter for hi mem mapping */
328
        l.sw    0x0(r0),r0      /* Initialize RAM */
329
        l.sw    0x4(r0),r0      /* Initialize RAM */
330
        l.sw    0x8(r0),r0      /* Initialize RAM */
331
        l.sw    0xc(r0),r0      /* Initialize RAM */
332
        l.sw    0x10(r0),r0     /* Initialize RAM */
333
        l.sw    0x14(r0),r0     /* Initialize RAM */
334
        l.sw    0x18(r0),r0     /* Initialize RAM */
335
        l.sw    0x1c(r0),r0     /* Initialize RAM */
336
        l.sw    0x20(r0),r0     /* Initialize RAM */
337
        l.sw    0x24(r0),r0     /* Initialize RAM */
338
        l.sw    0x28(r0),r0     /* Initialize RAM */
339
        l.sw    0x2c(r0),r0     /* Initialize RAM */
340
        l.sw    0x30(r0),r0     /* Initialize RAM */
341
        l.sw    0x34(r0),r0     /* Initialize RAM */
342
        l.sw    0x38(r0),r0     /* Initialize RAM */
343
        l.sw    0x3c(r0),r0     /* Initialize RAM */
344
        l.sw    0x40(r0),r0     /* Initialize RAM */
345
        l.sw    0x44(r0),r0     /* Initialize RAM */
346
        l.sw    0x48(r0),r0     /* Initialize RAM */
347
        l.sw    0x4c(r0),r0     /* Initialize RAM */
348
        l.j     _align1
349
        //l.j _dmmu_except1
350
        l.nop
351
 
352
 
353
        /* Exceptions followed by NOPs */
354
 
355
        /* SW alignment exception */
356
_align1:
357
        l.movhi r11,0
358
        l.nop
359
        /* Test l.sh */
360
        l.ori r5,r0,0x1 /* Half-word access, offset 1 */
361
        l.sh 0x0(r5),r0
362
        l.addi r12,r12,1 /* Increment 2nd exception counter */
363
        l.ori r5,r0,0x3 /* Half-word access, offset 3 */
364
        l.sh 0x0(r5),r0
365
        l.addi r12,r12,1 /* Increment 2nd exception counter */
366
        /* Test l.lhz */
367
        l.ori r5,r0,0x1 /* Half-word access, offset 1 */
368
        l.lhz r3,0x0(r5)
369
        l.addi r12,r12,1 /* Increment 2nd exception counter */
370
        l.ori r5,r0,0x3 /* Half-word access, offset 3 */
371
        l.lhz r3,0x0(r5)
372
        l.addi r12,r12,1 /* Increment 2nd exception counter */
373
        /* Test l.lhs */
374
        l.ori r5,r0,0x1 /* Half-word access, offset 1 */
375
        l.lhs r3,0x0(r5)
376
        l.addi r12,r12,1 /* Increment 2nd exception counter */
377
        l.ori r5,r0,0x3 /* Half-word access, offset 3 */
378
        l.lhs r3,0x0(r5)
379
        l.addi r12,r12,1 /* Increment 2nd exception counter */
380
        /* Test l.sw */
381
        l.ori r5,r0,0x1 /* Word access, offset 1 */
382
        l.sw 0x0(r5), r0
383
        l.addi r12,r12,1 /* Increment 2nd exception counter */
384
        l.ori r5,r0,0x2 /* Word access, offset 2 */
385
        l.sw 0x0(r5), r0
386
        l.addi r12,r12,1 /* Increment 2nd exception counter */
387
        l.ori r5,r0,0x3 /* Word access, offset 3 */
388
        l.sw 0x0(r5), r0
389
        l.addi r12,r12,1 /* Increment 2nd exception counter */
390
        /* Test l.lwz */
391
        l.ori r5,r0,0x1 /* Word access, offset 1 */
392
        l.lwz r3,0x0(r5)
393
        l.addi r12,r12,1 /* Increment 2nd exception counter */
394
        l.ori r5,r0,0x2 /* Word access, offset 2 */
395
        l.lwz r3,0x0(r5)
396
        l.addi r12,r12,1 /* Increment 2nd exception counter */
397
        l.ori r5,r0,0x3 /* Word access, offset 3 */
398
        l.lwz r3,0x0(r5)
399
        l.addi r12,r12,1 /* Increment 2nd exception counter */
400
#if OR1200_HAS_LWS==1
401
        /* Test l.lws */
402
        l.ori r5,r0,0x1 /* Word access, offset 1 */
403
        l.lws r3,0x0(r5)
404
        l.addi r12,r12,1 /* Increment 2nd exception counter */
405
        l.ori r5,r0,0x2 /* Word access, offset 2 */
406
        l.lws r3,0x0(r5)
407
        l.addi r12,r12,1 /* Increment 2nd exception counter */
408
        l.ori r5,r0,0x3 /* Word access, offset 3 */
409
        l.lws r3,0x0(r5)
410
        l.addi r12,r12,1 /* Increment 2nd exception counter */
411
        l.nop
412
#endif
413
        /* Now test them in delay slots */
414
 
415
        l.ori r5,r0,0x1 /* Half-word access, offset 1 */
416
        l.j 1f
417
        l.sh 0x0(r5),r0
418
        l.nop
419
1:      l.addi r12,r12,1 /* Increment 2nd exception counter */
420
        l.ori r5,r0,0x3 /* Half-word access, offset 3 */
421
        l.j 2f
422
        l.sh 0x0(r5),r0
423
        l.nop
424
2:      l.addi r12,r12,1 /* Increment 2nd exception counter */
425
 
426
        /* Test l.lhz */
427
        l.ori r5,r0,0x1 /* Half-word access, offset 1 */
428
        l.j 3f
429
        l.lhz r3,0x0(r5)
430
        l.nop
431
3:      l.addi r12,r12,1 /* Increment 2nd exception counter */
432
        l.ori r5,r0,0x3 /* Half-word access, offset 3 */
433
        l.j 4f
434
        l.lhz r3,0x0(r5)
435
        l.nop
436
4:      l.addi r12,r12,1 /* Increment 2nd exception counter */
437
 
438
        /* Test l.lhs */
439
        l.ori r5,r0,0x1 /* Half-word access, offset 1 */
440
        l.j 5f
441
        l.lhs r3,0x0(r5)
442
        l.nop
443
5:      l.addi r12,r12,1 /* Increment 2nd exception counter */
444
        l.ori r5,r0,0x3 /* Half-word access, offset 3 */
445
        l.j 6f
446
        l.lhs r3,0x0(r5)
447
        l.nop
448
6:      l.addi r12,r12,1 /* Increment 2nd exception counter */
449
 
450
        /* Test l.sw */
451 412 julius
        l.ori   r5,r0,0x1 /* Word access, offset 1 */
452
        l.j     7f
453
        l.sw    0x0(r5), r0
454 349 julius
        l.nop
455 412 julius
7:      l.addi  r12,r12,1 /* Increment 2nd exception counter */
456
        l.ori   r5,r0,0x2 /* Word access, offset 2 */
457
        l.j     8f
458
        l.sw    0x0(r5), r0
459 349 julius
        l.nop
460 412 julius
8:      l.addi  r12,r12,1 /* Increment 2nd exception counter */
461
        l.ori   r5,r0,0x3 /* Word access, offset 3 */
462
        l.j     9f
463
        l.sh    0x0(r5), r0
464 349 julius
        l.nop
465 412 julius
9:      l.addi  r12,r12,1 /* Increment 2nd exception counter */
466 349 julius
 
467
        /* Test l.lwz */
468 412 julius
        l.ori   r5,r0,0x1 /* Word access, offset 1 */
469
        l.j     10f
470
        l.lwz   r3,0x0(r5)
471 349 julius
        l.nop
472 412 julius
10:     l.addi  r12,r12,1 /* Increment 2nd exception counter */
473
        l.ori   r5,r0,0x2 /* Word access, offset 2 */
474
        l.j     11f
475
        l.lwz   r3,0x0(r5)
476 349 julius
        l.nop
477 412 julius
11:     l.addi  r12,r12,1 /* Increment 2nd exception counter */
478
        l.ori   r5,r0,0x3 /* Word access, offset 3 */
479
        l.j     12f
480
        l.lwz   r3,0x0(r5)
481 349 julius
        l.nop
482 412 julius
12:     l.addi  r12,r12,1 /* Increment 2nd exception counter */
483 349 julius
#if OR1200_HAS_LWS==1
484
        /* Test l.lws */
485 412 julius
        l.ori   r5,r0,0x1 /* Word access, offset 1 */
486
        l.j     13f
487
        l.lws   r3,0x0(r5)
488 349 julius
        l.nop
489 412 julius
13:     l.addi  r12,r12,1 /* Increment 2nd exception counter */
490
        l.ori   r5,r0,0x2 /* Word access, offset 2 */
491
        l.j     14f
492
        l.lws   r3,0x0(r5)
493 349 julius
        l.nop
494 412 julius
14:     l.addi  r12,r12,1 /* Increment 2nd exception counter */
495
        l.ori   r5,r0,0x3 /* Word access, offset 3 */
496
        l.j     15f
497
        l.lws   r3,0x0(r5)
498 349 julius
        l.nop
499 412 julius
15:     l.addi  r12,r12,1 /* Increment 2nd exception counter */
500 349 julius
 
501
#endif
502
        /* Check 1st and 2nd exception counters are equal */
503
        l.sfeq  r11,r12                 /* Should be equal */
504
        l.bf    17f
505
        l.nop
506
        l.nop   1
507
17:     l.nop   2
508
        l.nop
509
 
510
        /* Illegal instruction exception */
511
_illegal1:
512
        l.nop
513
        l.nop
514
        l.movhi r5, hi(0x44004800) /* Put "l.jr r9" instruction in r5 */
515 412 julius
        l.ori   r5, r5, lo(0x44004800)
516
        l.sw    0x0(r0), r5 /* Write "l.j r9" to address 0x0 in RAM */
517 349 julius
        l.movhi r5, 0xff00 /* Put an illegal instruction in r5 */
518 412 julius
        l.sw    0x4(r0), r5   /* Write illegal instruction to RAM addr 0x4 */
519 349 julius
        l.mtspr r0,r0,SPR_ICBIR /* Invalidate line 0 of cache */
520
        /* Call 0x4, illegal opcode instruction */
521 412 julius
        l.ori   r6, r0, 0x4
522
        l.jalr  r6 /* Jump to address 0x4, landing on an illegal instruction */
523
        l.addi  r12,r12,1 /* Increment 2nd exception counter */
524
        l.nop /* Should return here */
525 349 julius
        l.nop
526
 
527
        /* Test in delay slot */
528
 
529
        l.movhi r5, 0xff00 /* Put an illegal instruction in r5 */
530 412 julius
        l.sw    0x4(r0), r5   /* Write illegal instruction to RAM addr 0x4 */
531
        l.mtspr r0,r0,SPR_ICBIR /* Invalidate line 0 of cache */
532
        l.jalr  r0 /* Jump to address 0, will be a jump back but with an illegal
533 349 julius
                     dslot instruction which will befixed by handler */
534 412 julius
        l.addi  r12,r12,1 /* Increment 2nd exception counter */
535 349 julius
        l.nop /* Should return here */
536
 
537
        /* Check 1st and 2nd exception counters are equal */
538
        l.sfeq  r11,r12                 /* Should be equal */
539 412 julius
        l.bf    1f
540 349 julius
        l.nop
541 412 julius
        l.or    r3, r12, r12
542
        l.nop   2 /* Report expected exception count */
543
        l.or    r3, r11, r11
544
        l.nop   2 /* Report actual exception count */
545
        l.nop   1
546 349 julius
1:      l.nop
547
        l.nop
548
 
549
 
550
_dbus1:
551
        l.nop
552
        l.movhi r12, 0 /* Reset exception counters */
553
        l.movhi r11, 0
554
        l.ori r30, r0, 0xd /* put 0xd in r30, indicate it's databus test */
555
        /* Cause access error */
556
        /* Load word */
557
        l.movhi r5, 0xee00 /* Address to cause an error */
558
        l.lwz r6, 0(r5)
559
        l.addi r12, r12, 1 /* Incremement secondary exception counter */
560
        /* Load half */
561
        l.movhi r5, 0xee00 /* Address to cause an error */
562
        l.lhz r6, 0(r5)
563
        l.addi r12, r12, 1 /* Incremement secondary exception counter */
564
        /* Load byte */
565
        l.movhi r5, 0xee00 /* Address to cause an error */
566
        l.lbz r6, 0(r5)
567
        l.addi r12, r12, 1 /* Incremement secondary exception counter */
568
        /* Store word */
569
        l.movhi r5, 0xee00 /* Address to cause an error */
570
        l.sw 0(r5), r6
571
        l.addi r12, r12, 1 /* Incremement secondary exception counter */
572
        /* Store half */
573
        l.movhi r5, 0xee00 /* Address to cause an error */
574
        l.sh 0(r5), r6
575
        l.addi r12, r12, 1 /* Incremement secondary exception counter */
576
        /* Store byte */
577
        l.movhi r5, 0xee00 /* Address to cause an error */
578
        l.sb 0(r5), r6
579
        l.addi r12, r12, 1 /* Incremement secondary exception counter */
580
        l.nop
581
        /* Delay slot tests */
582
        /* Load word */
583
        l.movhi r5, 0xee00 /* Address to cause an error */
584
        l.j 1f
585
        l.lwz r6, 0(r5) /* Data bus error in delay slot */
586
        l.nop
587
1:      l.addi r12, r12, 1
588
        /* Load half */
589
        l.movhi r5, 0xee00 /* Address to cause an error */
590
        l.j 2f
591
        l.lhz r6, 0(r5) /* Data bus error in delay slot */
592
        l.nop
593
2:      l.addi r12, r12, 1
594
        /* Load byte */
595
        l.movhi r5, 0xee00 /* Address to cause an error */
596
        l.j 3f
597
        l.lbz r6, 0(r5) /* Data bus error in delay slot */
598
        l.nop
599
3:      l.addi r12, r12, 1
600
        /* Store word */
601
        l.movhi r5, 0xee00 /* Address to cause an error */
602
        l.j 4f
603
        l.sw 0(r5), r6  /* Data bus error in delay slot */
604
        l.nop
605
4:      l.addi r12, r12, 1
606
        /* Store half */
607
        l.movhi r5, 0xee00 /* Address to cause an error */
608
        l.j 5f
609
        l.sh 0(r5), r6  /* Data bus error in delay slot */
610
        l.nop
611
5:      l.addi r12, r12, 1
612
        /* Store byte */
613
        l.movhi r5, 0xee00 /* Address to cause an error */
614
        l.j 6f
615
        l.sb 0(r5), r6  /* Data bus error in delay slot */
616
        l.nop
617
6:      l.addi r12, r12, 1
618
 
619
 
620
/* Check 1st and 2nd exception counters are equal */
621
        l.sfeq  r11,r12                 /* Should be equal */
622
        l.bf 7f
623
        l.nop
624
        l.or r3, r12, r12
625
        l.nop 2 /* Report expected exception count */
626
        l.or r3, r11, r11
627
        l.nop 2 /* Report actual exception count */
628
        l.nop 1
629
7:      l.nop
630
 
631
 
632
 
633
_ibus1:
634
        /* TODO: do this it with cache enabled/disabled */
635
        l.movhi r12, 0 /* Reset exception counters */
636
        l.movhi r11, 0
637
        l.movhi r30, 0x0 /* put 0x0 in r30,indicate it's instruction bus test*/
638
        /* Cause access error */
639
        l.movhi r5, 0xee00 /* Address to cause an error */
640
        l.jalr r5 /* Jump and link to bad address */
641
        l.nop
642
        l.addi r12, r12, 1 /* Incremement secondary exception counter */
643
        /* Check 1st and 2nd exception counters are equal */
644
        l.sfeq  r11,r12                 /* Should be equal */
645
        l.bf 1f
646
        l.nop
647
        l.or r3, r12, r12
648
        l.nop 2 /* Report expected exception count */
649
        l.or r3, r11, r11
650
        l.nop 2 /* Report actual exception count */
651
        l.nop 1
652
1:      l.nop
653
        l.nop
654
 
655
 
656
        /* Data MMU exception - try case where we need to translate address as
657
           we l.rfe to it */
658
        // Check the DMMU is the in the design, otherwise don't compile in this
659
        // test.
660
#ifndef OR1200_NO_DMMU
661 373 julius
        .extern lo_dmmu_en
662 349 julius
_dmmu_except1:
663
        /* Call DMMU invalidate function */
664
        l.movhi r4, hi(_dmmu_invalidate)
665
        l.ori r4, r4, lo(_dmmu_invalidate)
666
        l.jalr r4
667
        l.ori r3, r0, 64 /* Put number of entries in r3 */
668
 
669
        l.movhi r5, hi(0x01000000)
670
        /* Write a word to the place where we'll translate to */
671
        l.movhi r7, hi(0xaabbccdd)
672
        l.ori r7, r7, lo(0xaabbccdd)
673
        l.sw 0(r5), r7 /* Shouldn't trigger MMU */
674
        l.sfne r18, r0
675
        l.bf _dmmu_test_error
676
        l.nop
677
        l.sfne r19, r0
678
        l.bf _dmmu_test_error
679
        l.nop
680
 
681
        /* Now enable DMMU */
682 373 julius
        l.movhi r4, hi(lo_dmmu_en)
683
        l.ori r4, r4, lo(lo_dmmu_en)
684 349 julius
        l.jalr r4
685
        l.nop
686
 
687
        /* Now start test. 0xc0000000 should go to 0x01000000 */
688
        l.lwz r8, 0(r5) /* Should cause DMMU miss, lomem */
689
        /* Check value was OK */
690
        l.sfne r7, r8
691
        l.bf _dmmu_test_error
692
        l.nop
693
        l.sfnei r18, 0x1 /* Check for lo mem mapping */
694
        l.bf _dmmu_test_error
695
        l.nop
696
        l.sfne r19, r0 /* hi-mem counter should still be 0 */
697
        l.bf _dmmu_test_error
698
        l.nop
699
 
700
        /* Test accesses to mapped area */
701
        l.movhi r6, hi(0xc0000000)
702
        l.lwz r8, 0(r6) /* Should cause DMMU miss, himem */
703
        /* Check value was OK */
704
        l.sfne r7, r8
705
        l.bf _dmmu_test_error
706
        l.nop
707
        l.sfnei r18, 0x1 /* Check for lo mem mapping */
708
        l.bf _dmmu_test_error
709
        l.nop
710
        l.sfnei r19, 0x1 /* hi-mem counter should still be 0 */
711
        l.bf _dmmu_test_error
712
        l.nop
713
 
714
        /* Now start test. 0xc0000000 should go to 0x01000000 */
715
        l.lwz r8, 0(r5) /* Should cause DMMU miss, lomem */
716
        /* Check value was OK */
717
        l.sfne r7, r8
718
        l.bf _dmmu_test_error
719
        l.nop
720
        l.sfnei r18, 0x2 /* Check for lo mem mapping increment */
721
        l.bf _dmmu_test_error
722
        l.nop
723
        l.sfnei r19, 0x1 /* hi-mem counter should still be 1 */
724
        l.bf _dmmu_test_error
725
        l.nop
726
 
727
        l.addi r7, r7, 0x1111 /* Incremement value we're writing */
728
 
729
        l.sw 4(r6), r7 /* Should cause DMMU miss, himem */
730
        l.sfnei r18, 0x2 /* Check for lo mem mapping */
731
        l.bf _dmmu_test_error
732
        l.nop
733
        l.sfnei r19, 0x2 /* hi-mem counter should be 2 */
734
        l.bf _dmmu_test_error
735
        l.nop
736
 
737
        l.lwz r8, 4(r5) /* Should cause DMMU miss, lomem */
738
        /* Check value was OK */
739
        l.sfne r7, r8
740
        l.bf _dmmu_test_error
741
        l.nop
742
        l.sfnei r18, 0x3 /* Check for lo mem mapping increment */
743
        l.bf _dmmu_test_error
744
        l.nop
745
        l.sfnei r19, 0x2 /* hi-mem counter should still be 2 */
746
        l.bf _dmmu_test_error
747
        l.nop
748
 
749
        /* Fast DMMU exceptions should follow */
750
        l.addi r7, r7, 0x1111 /* Incremement value we're writing */
751
        l.sw 8(r6), r7 /* Should cause DMMU miss, himem */
752
        l.lwz r8, 8(r5) /* Should cause DMMU miss, lomem */
753
        l.addi r7, r7, 0x1111 /* Incremement value we're writing */
754
        l.sw 0xc(r6), r7 /* Should cause DMMU miss, himem */
755
        l.lwz r8, 0xc(r5) /* Should cause DMMU miss, lomem */
756
        l.addi r7, r7, 0x1111 /* Incremement value we're writing */
757
        l.sw 0x10(r6), r7 /* Should cause DMMU miss, himem */
758
        l.lwz r8, 0x10(r5) /* Should cause DMMU miss, lomem */
759
        l.addi r7, r7, 0x1111 /* Incremement value we're writing */
760
        l.sw 0x14(r6), r7 /* Should cause DMMU miss, himem */
761
        l.lwz r8, 0x14(r5) /* Should cause DMMU miss, lomem */
762
        l.addi r7, r7, 0x1111 /* Incremement value we're writing */
763
        l.sw 0x18(r6), r7 /* Should cause DMMU miss, himem */
764
        l.lwz r8, 0x18(r5) /* Should cause DMMU miss, lomem */
765
        l.addi r7, r7, 0x1111 /* Incremement value we're writing */
766
        l.sw 0x1c(r6), r7 /* Should cause DMMU miss, himem */
767
        l.lwz r8, 0x1c(r5) /* Should cause DMMU miss, lomem */
768
        l.addi r7, r7, 0x1111 /* Incremement value we're writing */
769
        l.sw 0x20(r6), r7 /* Should cause DMMU miss, himem */
770
        l.lwz r8, 0x20(r5) /* Should cause DMMU miss, lomem */
771
        l.addi r7, r7, 0x1111 /* Incremement value we're writing */
772
        l.sw 0x24(r6), r7 /* Should cause DMMU miss, himem */
773
        l.lwz r8, 0x24(r5) /* Should cause DMMU miss, lomem */
774
        /* Should now be 11 lowmem DTLB misses and 10 for high memory space */
775
        l.sfne r7, r8
776
        l.bf _dmmu_test_error
777
        l.nop
778
        l.sfnei r18, 0xb /* Check for lo mem mapping increment to 11 */
779
        l.bf _dmmu_test_error
780
        l.nop
781
        l.sfnei r19, 0xa /* hi-mem counter should be 10 */
782
        l.bf _dmmu_test_error
783
        l.nop
784
 
785
        l.j _dmmu_test_ok
786
        l.nop
787
 
788
 
789
_dmmu_test_error:
790
        l.movhi r3, hi(0xeeeeeeed)
791
        l.ori r3, r3, lo(0xeeeeeeed)
792
        l.nop 2
793
        l.nop 1
794
 
795
_dmmu_test_ok:
796
        l.nop
797
 
798
#endif // #ifndef OR1200_NO_DMMU
799
 
800
        /* End of tests - report and finish simulation */
801
        l.movhi r3,hi(0xdeaddead)
802
        l.ori   r3,r3,lo(0xdeaddead)
803
        l.nop   2
804
 
805
        l.movhi r3,hi(0x8000000d)
806
        l.ori   r3,r3,lo(0x8000000d)
807
        l.nop   2
808
 
809
        l.addi r3,r0,0
810 373 julius
        l.jal   exit
811 349 julius
        l.nop
812
 
813
 
814
        /* DMMU invalidate function */
815
        /* First parameter, r3, has number of DMMU entries (should be 64)*/
816
 
817
_dmmu_invalidate:
818
        /* Setup the Data MMU's TLBS */
819
        l.movhi r4, hi(SPR_DTLBMR_BASE(0))
820
        l.ori r4, r4, lo(SPR_DTLBMR_BASE(0))
821
 
822
        /* DTLB invalidate loop */
823
1:
824
        l.mtspr r4, r0, 0x0
825
        l.addi r4, r4, 0x1
826
        l.sfeq r3, r0
827
        l.bnf 1b
828
        l.addi r3, r3, -1
829
        l.jr r9
830
        l.nop
831
 

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