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[/] [opentech/] [web_uploads/] [changes_1_4_0.txt] - Blame information for rev 6

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Changes from version 1.3.0
 
OpenCores.org
======
Site and CVS are Updated
 
DESIGNS
======
 
- balloon (added)
- efi (updated)
- MegaSquirt (updated)
- OpenAutomationProject (added)
- free-ip (updated)
- pjrc (added)
- Pancham (updated)
- rstk (added)
- pjrc (added)
- servomaster (added)
- slc1657 (added)
- wb (updated)
 
 
 
TOOLS:
=====
 
 
In Design Entry
- gEDA (updated)
- emacs-modes (updated)
- eda-index (added)
 
In PLDs
- JHDL (updated)
- virtextools (added)
- vpr_virtex (added)
 
In Layout
- gerb2tif (updated)
- gerbmerge  (Added)
- gerv  (updated)
 
 
In Others
- jtag-tools (updated)
 
In Roms
- ppep (added)
- srecord (updated)
 
 
 
In PIC
- gpicd  (added)
 
 
In Simulation
- gtkwave  (updated)
- decida (added)
- gnucap (added)
- SystemC-Vergs (added)
- SystemPerl (added)
- ViPEC (added)
 
 
 
In Spice
- Spice+   (updated)
- gspice (updated)
- gwave (updated)
- ng-spice (updated)
- tclspice (updated)
 
 
In Synthsis
- Boolean Simplification  (updated)
- qmc (added)
 
 
In Verification
- Covered: Coverage Tool  (updated)
- atpg (added)
 
 
In Verilog
- Ircus (updated)
- IVI  (upated)
- csv-verilog-maker (added)
- cver (added)
- dinotrace (updated)
- Verilog-Perl (updated)
- Verilog-PLI (updated)
- Veritlator (added)
 
 
In VHDL
- Savant (updated)

Line No.	Rev	Author	Line
1	6	root	`Changes from version 1.3.0`
2
3			`OpenCores.org`
4			`======`
5			`Site and CVS are Updated`
6
7			`DESIGNS`
8			`======`
9
10			`- balloon (added)`
11			`- efi (updated)`
12			`- MegaSquirt (updated)`
13			`- OpenAutomationProject (added)`
14			`- free-ip (updated)`
15			`- pjrc (added)`
16			`- Pancham (updated)`
17			`- rstk (added)`
18			`- pjrc (added)`
19			`- servomaster (added)`
20			`- slc1657 (added)`
21			`- wb (updated)`
22
23
24
25			`TOOLS:`
26			`=====`
27
28
29			`In Design Entry`
30			`- gEDA (updated)`
31			`- emacs-modes (updated)`
32			`- eda-index (added)`
33
34			`In PLDs`
35			`- JHDL (updated)`
36			`- virtextools (added)`
37			`- vpr_virtex (added)`
38
39			`In Layout`
40			`- gerb2tif (updated)`
41			`- gerbmerge (Added)`
42			`- gerv (updated)`
43
44
45			`In Others`
46			`- jtag-tools (updated)`
47
48			`In Roms`
49			`- ppep (added)`
50			`- srecord (updated)`
51
52
53
54			`In PIC`
55			`- gpicd (added)`
56
57
58			`In Simulation`
59			`- gtkwave (updated)`
60			`- decida (added)`
61			`- gnucap (added)`
62			`- SystemC-Vergs (added)`
63			`- SystemPerl (added)`
64			`- ViPEC (added)`
65
66
67
68			`In Spice`
69			`- Spice+ (updated)`
70			`- gspice (updated)`
71			`- gwave (updated)`
72			`- ng-spice (updated)`
73			`- tclspice (updated)`
74
75
76			`In Synthsis`
77			`- Boolean Simplification (updated)`
78			`- qmc (added)`
79
80
81			`In Verification`
82			`- Covered: Coverage Tool (updated)`
83			`- atpg (added)`
84
85
86			`In Verilog`
87			`- Ircus (updated)`
88			`- IVI (upated)`
89			`- csv-verilog-maker (added)`
90			`- cver (added)`
91			`- dinotrace (updated)`
92			`- Verilog-Perl (updated)`
93			`- Verilog-PLI (updated)`
94			`- Veritlator (added)`
95
96
97			`In VHDL`
98			`- Savant (updated)`

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Subversion Repositories opentech

[/] [opentech/] [web_uploads/] [changes_1_4_0.txt] - Blame information for rev 6