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[/] [opentech/] [web_uploads/] [changes_1_5_1.txt] - Blame information for rev 6

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Changes from version 1.4.1
 
OpenCores.org
======
Site and CVS are Updated
 
DESIGNS
======
- UTNios processor (updated)
- Handasa Arabia site (updated)
- VLSI technology library (updated)
- Free Model Foundation models (updated)
- Elphel designs (updated)
 
TOOLS:
=====
In Design Entry
- gEDA (updated)
- TinyCad (updated)
- xcircuit (updated)
- HDLmaker (updated)
- veditor_Eclipse (updated)
- la2vcd (updated)
 
In pcb
-  KICAD (added)
- PCB Editor  (updated)
 
In PLDs
- JHLD (updated)
- Vertix tools
 
In uC
- gputils (updated)
- PiKdev (added)
- ketchlab (updated)
- MicroDev (added)
- gpsim (updated)
- Broccoli18 (updated)
- Odyssey (added)
- SDCC (updated)
 
In  Analysis
- Salut (updated)
- Electronics Solver (updated)
 
In Spice
- adms (updated)
 
In simulation
- Qucs (updated)
-thud (updated)
- SIMSYNCH (added)
-digitel (updated)
-decida (updated)
-udl (updated)
-IDASS (updated)
 
in Synthesis
- MVSIS (added)
- bexpred (updated)
 
In IC layout/vlsi
- Alliance (updated)
- electric (updated)
-MGEN (updated)
-magic (updated)
- chipmunk (updated)
- QCADesign (added)
 
In Verification
- NuSMV (updated)
- Covered: Coverage Tool  (updated)
- system perl (added)
- Teal (added)
- MyHDL (updated)
- confluence (updated)
 
 
In instruments
- qoscc (updated)
-QtDMM (updated)
-zmeter (updated)
-GPIB-Tcl (updated)
 
In Others
- EDA-Index (updated)
 
In Verilog
- Ircus (updated)
- sc2v (added)
- Mariana (added)
- Vtracer (updated)
- GPLCver (updated)
- dinotrace (updated)
- verilog perl (updated)
- verilog PLI (updated0
 
 
- VHDL
- Alliance (updated)
- electric (updated)
- Freehdl (updated)
-signs (added)
- VHDL parser (added)
 
in ROMs
- Srecord (updated)
 
In Modeling
- simuted (added)
- Gezel (added)
- Plois (added)
- Potlemy II (added)

Line No.	Rev	Author	Line
1	6	root	`Changes from version 1.4.1`
2
3			`OpenCores.org`
4			`======`
5			`Site and CVS are Updated`
6
7			`DESIGNS`
8			`======`
9			`- UTNios processor (updated)`
10			`- Handasa Arabia site (updated)`
11			`- VLSI technology library (updated)`
12			`- Free Model Foundation models (updated)`
13			`- Elphel designs (updated)`
14
15			`TOOLS:`
16			`=====`
17			`In Design Entry`
18			`- gEDA (updated)`
19			`- TinyCad (updated)`
20			`- xcircuit (updated)`
21			`- HDLmaker (updated)`
22			`- veditor_Eclipse (updated)`
23			`- la2vcd (updated)`
24
25			`In pcb`
26			`- KICAD (added)`
27			`- PCB Editor (updated)`
28
29			`In PLDs`
30			`- JHLD (updated)`
31			`- Vertix tools`
32
33			`In uC`
34			`- gputils (updated)`
35			`- PiKdev (added)`
36			`- ketchlab (updated)`
37			`- MicroDev (added)`
38			`- gpsim (updated)`
39			`- Broccoli18 (updated)`
40			`- Odyssey (added)`
41			`- SDCC (updated)`
42
43			`In Analysis`
44			`- Salut (updated)`
45			`- Electronics Solver (updated)`
46
47			`In Spice`
48			`- adms (updated)`
49
50			`In simulation`
51			`- Qucs (updated)`
52			`-thud (updated)`
53			`- SIMSYNCH (added)`
54			`-digitel (updated)`
55			`-decida (updated)`
56			`-udl (updated)`
57			`-IDASS (updated)`
58
59			`in Synthesis`
60			`- MVSIS (added)`
61			`- bexpred (updated)`
62
63			`In IC layout/vlsi`
64			`- Alliance (updated)`
65			`- electric (updated)`
66			`-MGEN (updated)`
67			`-magic (updated)`
68			`- chipmunk (updated)`
69			`- QCADesign (added)`
70
71			`In Verification`
72			`- NuSMV (updated)`
73			`- Covered: Coverage Tool (updated)`
74			`- system perl (added)`
75			`- Teal (added)`
76			`- MyHDL (updated)`
77			`- confluence (updated)`
78
79
80			`In instruments`
81			`- qoscc (updated)`
82			`-QtDMM (updated)`
83			`-zmeter (updated)`
84			`-GPIB-Tcl (updated)`
85
86			`In Others`
87			`- EDA-Index (updated)`
88
89			`In Verilog`
90			`- Ircus (updated)`
91			`- sc2v (added)`
92			`- Mariana (added)`
93			`- Vtracer (updated)`
94			`- GPLCver (updated)`
95			`- dinotrace (updated)`
96			`- verilog perl (updated)`
97			`- verilog PLI (updated0`
98
99
100			`- VHDL`
101			`- Alliance (updated)`
102			`- electric (updated)`
103			`- Freehdl (updated)`
104			`-signs (added)`
105			`- VHDL parser (added)`
106
107			`in ROMs`
108			`- Srecord (updated)`
109
110			`In Modeling`
111			`- simuted (added)`
112			`- Gezel (added)`
113			`- Plois (added)`
114			`- Potlemy II (added)`

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Subversion Repositories opentech

[/] [opentech/] [web_uploads/] [changes_1_5_1.txt] - Blame information for rev 6