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[/] [opentech/] [web_uploads/] [changes_1_6_1.txt] - Blame information for rev 6

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Changes from version 1.6.0
 
OpenCores.org
======
Site and CVS are Updated
 
DESIGNS
======
- Free Model Foundation models (updated)
- simplyrisc (added)
- Gadgetboard (updated)
- freeio (updated)
- vlsitechnology_lib (updated)
- OpenCPU (added)
- Ronja Project (updated)
 
 
TOOLS:
=====
[Analysis]
 
 
[Design Entry]
- emacs-modes (updated)
- gEDA (updated)
- hdlmaker (updated)
- KICAD (updated)
- TinyCad (updated)
- veditor_Eclipse (updated)
- xcircuit (updated)
 
 
[Instruments]
- qoscc (updated)
- QtDMM (updated)
 
[Modeling]
- ptolemy (updated)
 
 
[pcb]
- gerber2pdf (updated)
- gerbmerge (updated)
- gerbv (updated)
- opencircuit_pcb (updated)
- pcb (updated)
 
 
[PLD]
- jhdl (updated)
 
 
[ROMs]
- srecords (updated)
 
[Simulation]
- cider (added)
- Qucs (updated)
 
 
[Spice]
- ASCO (updated)
- easyspice (added)
- eispice (added)
- gnucap (updated)
- kjwaves (added)
- pyspice (updated)
 
[SystemLevel]
- GreenSOCs (updated)
- SystemC-vregs (added)
- SystemPerl (updated)
 
[Testing]
- pystdf (added)
 
[uC]
- EVBU (added)
- Sam_I_Am (added)
 
 
[Verification]
- jove (updated)
 
 
[Verilog]
- Covered (updated)
- dinotrace (updated)
- Icarus (updated)
- ScriptSim (added)
- vbs (updated)
- verilator (updated)
- Verilog-Perl (updated)
- Verilog-Pli (updated)
- VHDL2Vlg (updated)
- voneline (added)
 
 
[VHDL]
- signs (updated)
- freehdl (updated)
 
[VLSI/IC layout]
- Alliance (updated)
- electric (updated)
- IRSIM (updated)
- LayoutEditor (updated)
- magic (updated)
- netgen (updated)
- toped (added)
- xchiplogo (added)
 
 
 
[Synthesis]
 
 
[Others]
 
 
 
[Extras]
- Xemacs (updated)
- nedit (updated)
- wincvs (updated)

Line No.	Rev	Author	Line
1	6	root	`Changes from version 1.6.0`
2
3			`OpenCores.org`
4			`======`
5			`Site and CVS are Updated`
6
7			`DESIGNS`
8			`======`
9			`- Free Model Foundation models (updated)`
10			`- simplyrisc (added)`
11			`- Gadgetboard (updated)`
12			`- freeio (updated)`
13			`- vlsitechnology_lib (updated)`
14			`- OpenCPU (added)`
15			`- Ronja Project (updated)`
16
17
18			`TOOLS:`
19			`=====`
20			`[Analysis]`
21
22
23			`[Design Entry]`
24			`- emacs-modes (updated)`
25			`- gEDA (updated)`
26			`- hdlmaker (updated)`
27			`- KICAD (updated)`
28			`- TinyCad (updated)`
29			`- veditor_Eclipse (updated)`
30			`- xcircuit (updated)`
31
32
33			`[Instruments]`
34			`- qoscc (updated)`
35			`- QtDMM (updated)`
36
37			`[Modeling]`
38			`- ptolemy (updated)`
39
40
41			`[pcb]`
42			`- gerber2pdf (updated)`
43			`- gerbmerge (updated)`
44			`- gerbv (updated)`
45			`- opencircuit_pcb (updated)`
46			`- pcb (updated)`
47
48
49			`[PLD]`
50			`- jhdl (updated)`
51
52
53			`[ROMs]`
54			`- srecords (updated)`
55
56			`[Simulation]`
57			`- cider (added)`
58			`- Qucs (updated)`
59
60
61			`[Spice]`
62			`- ASCO (updated)`
63			`- easyspice (added)`
64			`- eispice (added)`
65			`- gnucap (updated)`
66			`- kjwaves (added)`
67			`- pyspice (updated)`
68
69			`[SystemLevel]`
70			`- GreenSOCs (updated)`
71			`- SystemC-vregs (added)`
72			`- SystemPerl (updated)`
73
74			`[Testing]`
75			`- pystdf (added)`
76
77			`[uC]`
78			`- EVBU (added)`
79			`- Sam_I_Am (added)`
80
81
82			`[Verification]`
83			`- jove (updated)`
84
85
86			`[Verilog]`
87			`- Covered (updated)`
88			`- dinotrace (updated)`
89			`- Icarus (updated)`
90			`- ScriptSim (added)`
91			`- vbs (updated)`
92			`- verilator (updated)`
93			`- Verilog-Perl (updated)`
94			`- Verilog-Pli (updated)`
95			`- VHDL2Vlg (updated)`
96			`- voneline (added)`
97
98
99			`[VHDL]`
100			`- signs (updated)`
101			`- freehdl (updated)`
102
103			`[VLSI/IC layout]`
104			`- Alliance (updated)`
105			`- electric (updated)`
106			`- IRSIM (updated)`
107			`- LayoutEditor (updated)`
108			`- magic (updated)`
109			`- netgen (updated)`
110			`- toped (added)`
111			`- xchiplogo (added)`
112
113
114
115			`[Synthesis]`
116
117
118			`[Others]`
119
120
121
122			`[Extras]`
123			`- Xemacs (updated)`
124			`- nedit (updated)`
125			`- wincvs (updated)`

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Subversion Repositories opentech

[/] [opentech/] [web_uploads/] [changes_1_6_1.txt] - Blame information for rev 6